Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24368

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3657

1

T10

1

T11

40

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22218

1

T1

13

T2

146

T3

20

auto[1]

5807

1

T5

1

T7

14

T8

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	217	1			T247	20		T92	10		T250	1
values[0]	28	1			T184	19		T258	9		-	-
values[1]	652	1			T6	12		T7	14		T10	1
values[2]	834	1			T12	1		T161	12		T39	4
values[3]	741	1			T12	1		T15	13		T53	9
values[4]	609	1			T12	1		T45	13		T46	15
values[5]	2906	1			T8	38		T11	10		T13	39
values[6]	745	1			T6	24		T11	30		T51	21
values[7]	626	1			T164	1		T165	22		T153	2
values[8]	677	1			T10	1		T51	6		T149	5
values[9]	1126	1			T5	1		T51	22		T149	29
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	655	1			T6	12		T150	4		T64	23
values[1]	842	1			T12	1		T150	23		T151	11
values[2]	684	1			T12	1		T15	13		T53	9
values[3]	2972	1			T8	38		T12	1		T13	39
values[4]	543	1			T11	40		T51	21		T169	11
values[5]	789	1			T6	24		T161	12		T165	20
values[6]	583	1			T164	1		T165	22		T153	2
values[7]	824	1			T10	1		T51	28		T149	19
values[8]	905	1			T5	1		T149	15		T169	30
values[9]	173	1			T185	12		T248	1		T327	1
minimum	19055	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	7		T151	1		T263	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T150	4		T64	13		T161	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T151	1		T166	10		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	1		T150	11		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	1		T15	6		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T152	12		T154	1		T244	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1627	1			T8	38		T12	1		T13	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T64	1		T165	12		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T169	11		T152	10		T40	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	19		T51	9		T187	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	13		T161	12		T41	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T165	11		T173	8		T157	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T165	12		T153	1		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T164	1		T153	1		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T51	16		T149	5		T161	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T10	1		T149	14		T65	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T5	1		T169	30		T187	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T149	15		T173	15		T242	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T185	6		T327	1		T316	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T248	1		T194	4		T255	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18787	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T184	8		T260	10		T178	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	5		T151	8		T49	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T64	10		T39	2		T152	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T151	10		T243	9		T170	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T150	12		T177	15		T191	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T15	7		T53	8		T151	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T152	11		T244	4		T209	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T46	14		T52	16		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T64	1		T165	4		T170	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T152	10		T40	14		T217	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	21		T51	12		T187	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	11		T41	6		T190	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T165	9		T173	7		T262	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T165	10		T243	15		T184	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T246	9		T251	7		T252	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T51	12		T247	7		T209	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T65	9		T173	1		T185	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T187	17		T217	11		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T173	5		T247	8		T20	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T185	6		T316	21		T328	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T194	2		T255	5		T329	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	13		T15	1		T39	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T184	11		T260	9		T296	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T92	10		T250	1		T327	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T247	12		T330	11		T255	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T184	8		T258	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	7		T7	1		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T150	4		T64	13		T152	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T151	2		T166	10		T243	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	1		T161	12		T39	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	1		T15	6		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T150	11		T163	1		T152	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	1		T45	13		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T165	12		T154	1		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T8	38		T13	39		T14	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	1		T64	1		T187	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	13		T161	12		T242	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	18		T51	9		T165	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T165	12		T153	1		T41	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T164	1		T153	1		T168	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T51	3		T149	5		T161	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	1		T65	13		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T5	1		T51	13		T169	30
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T149	29		T224	9		T173	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T316	21		T331	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T247	8		T330	15		T255	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T184	11		T258	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T6	5		T7	13		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T64	10		T152	9		T260	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T151	18		T243	9		T170	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T39	2		T191	4		T261	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T15	7		T53	8		T151	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T150	12		T152	11		T244	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T46	14		T65	1		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T165	4		T170	2		T209	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T52	16		T158	8		T152	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	9		T64	1		T187	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	11		T190	2		T50	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	12		T51	12		T165	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T165	10		T41	6		T243	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T262	13		T251	7		T252	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T51	3		T247	7		T209	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T65	9		T173	1		T185	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T51	9		T187	17		T185	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T173	5		T20	1		T296	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	6		T151	9		T263	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T150	1		T64	11		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T151	11		T166	1		T243	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	1		T150	13		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	1		T15	12		T53	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T152	12		T154	1		T244	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T8	3		T12	1		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T64	2		T165	5		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T169	1		T152	11		T40	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	23		T51	13		T187	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	12		T161	1		T41	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T165	10		T173	8		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T165	11		T153	1		T243	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T164	1		T153	1		T246	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T51	14		T149	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	1		T149	1		T65	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	1		T169	2		T187	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T149	1		T173	6		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T185	7		T327	1		T316	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T248	1		T194	4		T255	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18906	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T184	12		T260	10		T178	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	6		T263	12		T267	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T150	3		T64	12		T161	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T166	9		T170	4		T157	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T150	10		T156	13		T177	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T15	1		T187	2		T166	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T152	11		T244	13		T167	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T8	35		T13	36		T14	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T165	11		T155	2		T170	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T169	10		T152	9		T40	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	17		T51	8		T187	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	12		T161	11		T41	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T165	10		T173	7		T157	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T165	11		T56	8		T270	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T91	1		T265	6		T251	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T51	14		T149	4		T161	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T149	13		T65	12		T224	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T169	28		T187	13		T263	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T149	14		T173	14		T242	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T185	5		T316	14		T328	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T194	2		T255	4		T329	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T155	11		T332	11		T333	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T184	7		T260	9		T178	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T92	1		T250	1		T327	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T247	9		T330	16		T255	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T184	12		T258	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T6	6		T7	14		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T150	1		T64	11		T152	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T151	20		T166	1		T243	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	1		T161	1		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	1		T15	12		T53	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T150	13		T163	1		T152	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	1		T45	1		T46	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T165	5		T154	1		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T8	3		T13	3		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T11	10		T64	2		T187	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T6	12		T161	1		T242	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	13		T51	13		T165	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T165	11		T153	1		T41	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T164	1		T153	1		T168	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T51	4		T149	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	1		T65	10		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T5	1		T51	10		T169	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T149	2		T224	1		T173	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T92	9		T316	14		T331	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T247	11		T330	10		T255	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T184	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	6		T263	12		T155	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T150	3		T64	12		T152	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T166	9		T170	4		T157	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T161	11		T156	13		T309	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T15	1		T166	2		T244	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T150	10		T152	11		T244	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T45	12		T187	2		T242	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T165	11		T170	6		T334	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T8	35		T13	36		T14	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T187	7		T155	2		T268	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	12		T161	11		T242	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	17		T51	8		T165	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T165	11		T41	5		T56	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T168	14		T91	1		T262	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T51	2		T149	4		T161	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T65	12		T224	15		T185	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T51	12		T169	28		T187	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T149	27		T224	8		T173	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17