Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24397

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3628

1

T5

1

T6

24

T11

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21595

1

T1

13

T2

146

T3

20

auto[1]

6430

1

T6

24

T7

14

T8

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	37	1			T265	7		T338	1		T339	9
values[0]	78	1			T152	19		T340	17		T341	5
values[1]	691	1			T10	1		T12	1		T15	13
values[2]	2983	1			T5	1		T8	38		T13	39
values[3]	560	1			T53	9		T151	11		T152	23
values[4]	470	1			T149	15		T169	30		T165	20
values[5]	649	1			T7	14		T12	1		T164	1
values[6]	810	1			T6	24		T10	1		T11	40
values[7]	882	1			T12	1		T150	4		T64	2
values[8]	653	1			T46	15		T164	1		T151	12
values[9]	1348	1			T6	12		T45	13		T51	43
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	972	1			T10	1		T12	1		T15	13
values[1]	2932	1			T5	1		T8	38		T13	39
values[2]	477	1			T151	11		T173	20		T167	15
values[3]	593	1			T149	15		T169	30		T163	1
values[4]	647	1			T11	10		T12	1		T164	1
values[5]	753	1			T6	24		T7	14		T10	1
values[6]	858	1			T12	1		T64	2		T161	15
values[7]	702	1			T46	15		T65	22		T39	2
values[8]	1024	1			T6	12		T45	13		T51	43
values[9]	178	1			T170	18		T267	9		T209	11
minimum	18889	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	1		T12	1		T15	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T152	10		T154	1		T263	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T8	38		T13	39		T14	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	1		T53	1		T149	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T151	1		T167	8		T217	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T173	15		T167	7		T342	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T245	1		T244	9		T247	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T149	15		T169	30		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	1		T164	1		T224	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	1		T153	1		T287	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	1		T10	1		T11	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	13		T187	3		T166	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T64	1		T161	15		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	1		T151	1		T187	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T46	1		T39	1		T165	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T65	13		T152	10		T166	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T6	7		T45	13		T51	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T51	13		T149	5		T169	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T170	5		T176	2		T195	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T267	9		T209	1		T332	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18746	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T259	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	7		T51	3		T64	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T152	9		T262	13		T324	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T52	16		T158	8		T152	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T53	8		T247	7		T59	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T151	10		T217	11		T273	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T173	5		T324	10		T191	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T244	12		T247	8		T343	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T165	9		T243	9		T286	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T170	2		T18	1		T50	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	9		T93	13		T310	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	13		T11	12		T187	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	11		T49	4		T253	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T64	1		T244	4		T217	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T151	11		T187	6		T165	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T46	14		T39	1		T165	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T65	9		T152	10		T243	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	5		T51	12		T150	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T51	9		T151	8		T40	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T170	13		T176	1		T333	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T209	10		T256	4		T291	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	1		T39	5		T41	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T265	7		T339	1		T344	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T338	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T340	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T152	10		T341	1		T320	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	1		T12	1		T15	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T154	1		T259	1		T263	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T8	38		T13	39		T14	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	1		T149	14		T157	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T151	1		T152	12		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T53	1		T173	15		T167	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T217	12		T251	1		T309	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T149	15		T169	30		T165	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	1		T12	1		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T163	1		T153	1		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	1		T11	18		T39	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T6	13		T11	1		T166	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T150	4		T64	1		T161	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	1		T187	11		T152	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T46	1		T164	1		T165	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T151	1		T165	12		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	404	1			T6	7		T45	13		T51	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T51	13		T149	5		T65	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T339	8		T344	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T340	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T152	9		T341	4		T320	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	7		T51	3		T89	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T262	13		T265	13		T268	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	978	1			T52	16		T158	8		T64	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T247	7		T324	16		T276	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T151	10		T152	11		T173	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T53	8		T173	5		T59	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T217	11		T274	10		T335	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T165	9		T314	9		T345	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	13		T244	12		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T243	9		T286	11		T310	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	12		T243	2		T184	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	11		T11	9		T49	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T64	1		T39	1		T187	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T187	6		T152	10		T190	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	14		T165	4		T185	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T151	11		T165	10		T243	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T6	5		T51	12		T150	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T51	9		T65	9		T151	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	1		T12	1		T15	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T152	10		T154	1		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T8	3		T13	3		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T53	9		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T151	11		T167	1		T217	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T173	6		T167	1		T342	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T245	1		T244	13		T247	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T149	1		T169	2		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	1		T164	1		T224	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T11	10		T153	1		T287	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T7	14		T10	1		T11	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	12		T187	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T64	2		T161	2		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T12	1		T151	12		T187	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T46	15		T39	2		T165	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T65	10		T152	11		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T6	6		T45	1		T51	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T51	10		T149	1		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T170	14		T176	2		T195	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T267	1		T209	11		T332	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18876	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T259	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T51	2		T64	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T152	9		T263	4		T262	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T8	35		T13	36		T14	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T149	13		T157	9		T168	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T167	7		T217	11		T273	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T173	14		T167	6		T178	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T244	8		T247	11		T198	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T149	14		T169	28		T165	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T224	8		T242	8		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T287	14		T310	12		T288	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	17		T150	3		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	12		T187	2		T166	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T161	13		T244	13		T156	33
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T187	7		T165	11		T166	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T165	11		T41	5		T173	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T65	12		T152	9		T166	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T6	6		T45	12		T51	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T51	12		T149	4		T169	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T170	4		T176	1		T346	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T267	8		T332	16		T294	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T118	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T265	1		T339	9		T344	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T338	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T340	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T152	10		T341	5		T320	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	1		T12	1		T15	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T154	1		T259	1		T263	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T8	3		T13	3		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T149	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T151	11		T152	12		T173	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T53	9		T173	6		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T217	12		T251	1		T309	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T149	1		T169	2		T165	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	14		T12	1		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T163	1		T153	1		T243	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T10	1		T11	13		T39	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	12		T11	10		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T150	1		T64	2		T161	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T12	1		T187	8		T152	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T46	15		T164	1		T165	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T151	12		T165	11		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	400	1			T6	6		T45	1		T51	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	392	1			T51	10		T149	1		T65	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T265	6		T344	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T340	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T152	9		T118	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T51	2		T157	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T263	4		T262	12		T265	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T8	35		T13	36		T14	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T149	13		T157	9		T168	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T152	11		T167	7		T247	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T173	14		T167	6		T192	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T217	11		T309	6		T274	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T149	14		T169	28		T165	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T224	8		T244	8		T155	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T286	8		T310	12		T288	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	17		T39	1		T242	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	12		T166	2		T287	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T150	3		T161	13		T187	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T187	9		T152	9		T166	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T165	11		T242	10		T185	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T165	11		T166	9		T263	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T6	6		T45	12		T51	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T51	12		T149	4		T65	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17