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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.24


Total test records in report: 919
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T352 /workspace/coverage/default/8.adc_ctrl_stress_all.37473639 May 05 02:51:45 PM PDT 24 May 05 03:11:33 PM PDT 24 562369180542 ps
T795 /workspace/coverage/default/9.adc_ctrl_alert_test.1364835026 May 05 02:51:52 PM PDT 24 May 05 02:51:53 PM PDT 24 422261513 ps
T796 /workspace/coverage/default/9.adc_ctrl_fsm_reset.477406585 May 05 02:51:51 PM PDT 24 May 05 02:58:17 PM PDT 24 122638663441 ps
T797 /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.4140389649 May 05 02:52:00 PM PDT 24 May 05 03:16:21 PM PDT 24 615186057057 ps
T69 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3800183191 May 05 02:38:42 PM PDT 24 May 05 02:38:45 PM PDT 24 468152672 ps
T128 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2589862522 May 05 02:38:12 PM PDT 24 May 05 02:38:15 PM PDT 24 561566985 ps
T70 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1011903987 May 05 02:38:37 PM PDT 24 May 05 02:38:39 PM PDT 24 631006765 ps
T35 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2762706242 May 05 02:38:16 PM PDT 24 May 05 02:38:18 PM PDT 24 2491344411 ps
T66 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.879954235 May 05 02:38:11 PM PDT 24 May 05 02:38:15 PM PDT 24 4457834083 ps
T74 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1151540163 May 05 02:38:33 PM PDT 24 May 05 02:38:35 PM PDT 24 512223325 ps
T96 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2895097835 May 05 02:38:30 PM PDT 24 May 05 02:38:33 PM PDT 24 561637083 ps
T75 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.573796779 May 05 02:38:19 PM PDT 24 May 05 02:38:21 PM PDT 24 476619267 ps
T60 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1626341383 May 05 02:38:36 PM PDT 24 May 05 02:38:45 PM PDT 24 3707780724 ps
T63 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.753289541 May 05 02:38:10 PM PDT 24 May 05 02:38:19 PM PDT 24 4111529236 ps
T61 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1341973672 May 05 02:38:23 PM PDT 24 May 05 02:38:25 PM PDT 24 357797973 ps
T798 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1656825565 May 05 02:38:18 PM PDT 24 May 05 02:38:20 PM PDT 24 329030313 ps
T76 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2877111102 May 05 02:38:36 PM PDT 24 May 05 02:38:39 PM PDT 24 736692115 ps
T79 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2588411223 May 05 02:38:39 PM PDT 24 May 05 02:38:43 PM PDT 24 663139244 ps
T129 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3546111861 May 05 02:38:43 PM PDT 24 May 05 02:38:44 PM PDT 24 345282131 ps
T62 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1161177632 May 05 02:38:24 PM PDT 24 May 05 02:38:39 PM PDT 24 11124505480 ps
T139 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3027722485 May 05 02:38:28 PM PDT 24 May 05 02:38:32 PM PDT 24 3798416963 ps
T144 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.857269420 May 05 02:38:10 PM PDT 24 May 05 02:38:16 PM PDT 24 1241335230 ps
T799 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2336294882 May 05 02:38:45 PM PDT 24 May 05 02:38:47 PM PDT 24 368982772 ps
T145 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1861093997 May 05 02:38:13 PM PDT 24 May 05 02:38:21 PM PDT 24 1165078505 ps
T140 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1093707978 May 05 02:38:33 PM PDT 24 May 05 02:38:35 PM PDT 24 2125334126 ps
T97 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2077135801 May 05 02:38:30 PM PDT 24 May 05 02:38:32 PM PDT 24 632927505 ps
T141 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3810836801 May 05 02:38:18 PM PDT 24 May 05 02:38:21 PM PDT 24 563697966 ps
T98 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2756463975 May 05 02:38:31 PM PDT 24 May 05 02:38:33 PM PDT 24 435561845 ps
T800 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.225152906 May 05 02:38:41 PM PDT 24 May 05 02:38:42 PM PDT 24 351689819 ps
T142 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2117080207 May 05 02:38:31 PM PDT 24 May 05 02:38:37 PM PDT 24 4779882817 ps
T801 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2213578723 May 05 02:38:18 PM PDT 24 May 05 02:38:21 PM PDT 24 491731352 ps
T802 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1654257710 May 05 02:38:40 PM PDT 24 May 05 02:38:41 PM PDT 24 450558972 ps
T803 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1133732539 May 05 02:38:18 PM PDT 24 May 05 02:38:20 PM PDT 24 493608889 ps
T80 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1543489945 May 05 02:38:13 PM PDT 24 May 05 02:38:17 PM PDT 24 410640824 ps
T804 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1272762023 May 05 02:38:34 PM PDT 24 May 05 02:38:36 PM PDT 24 319302752 ps
T67 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2392649494 May 05 02:38:23 PM PDT 24 May 05 02:38:28 PM PDT 24 9410359343 ps
T81 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.563292975 May 05 02:38:05 PM PDT 24 May 05 02:38:08 PM PDT 24 667593511 ps
T805 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3119463309 May 05 02:38:50 PM PDT 24 May 05 02:38:52 PM PDT 24 316529949 ps
T806 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.306365798 May 05 02:38:45 PM PDT 24 May 05 02:38:47 PM PDT 24 504086976 ps
T807 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1384790299 May 05 02:38:51 PM PDT 24 May 05 02:38:52 PM PDT 24 488463704 ps
T808 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2994094109 May 05 02:38:46 PM PDT 24 May 05 02:38:48 PM PDT 24 513578603 ps
T809 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.631161368 May 05 02:38:10 PM PDT 24 May 05 02:38:13 PM PDT 24 889521725 ps
T810 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2769989030 May 05 02:38:28 PM PDT 24 May 05 02:38:32 PM PDT 24 479781994 ps
T130 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1546563822 May 05 02:38:38 PM PDT 24 May 05 02:38:41 PM PDT 24 386638015 ps
T68 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2736844410 May 05 02:38:35 PM PDT 24 May 05 02:38:55 PM PDT 24 8004681328 ps
T131 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.676595265 May 05 02:38:12 PM PDT 24 May 05 02:38:15 PM PDT 24 1239773172 ps
T132 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2021138092 May 05 02:38:24 PM PDT 24 May 05 02:39:54 PM PDT 24 40226985852 ps
T811 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1106427297 May 05 02:38:45 PM PDT 24 May 05 02:38:46 PM PDT 24 448997772 ps
T143 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3676753971 May 05 02:38:35 PM PDT 24 May 05 02:38:38 PM PDT 24 5400838273 ps
T812 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3916904525 May 05 02:38:39 PM PDT 24 May 05 02:38:40 PM PDT 24 564288867 ps
T813 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4118353989 May 05 02:38:23 PM PDT 24 May 05 02:38:27 PM PDT 24 2169430892 ps
T814 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.627896224 May 05 02:38:44 PM PDT 24 May 05 02:38:46 PM PDT 24 414641947 ps
T368 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1341367459 May 05 02:38:21 PM PDT 24 May 05 02:38:29 PM PDT 24 8466506346 ps
T815 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2151740779 May 05 02:38:38 PM PDT 24 May 05 02:38:50 PM PDT 24 4111163657 ps
T369 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1904572608 May 05 02:38:18 PM PDT 24 May 05 02:38:24 PM PDT 24 8895537872 ps
T816 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1929348624 May 05 02:38:46 PM PDT 24 May 05 02:38:48 PM PDT 24 552537637 ps
T817 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2396614940 May 05 02:38:18 PM PDT 24 May 05 02:38:21 PM PDT 24 443417036 ps
T133 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3636422920 May 05 02:38:15 PM PDT 24 May 05 02:40:47 PM PDT 24 38440093156 ps
T82 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2706724985 May 05 02:38:38 PM PDT 24 May 05 02:38:44 PM PDT 24 7990443431 ps
T818 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1398174470 May 05 02:38:44 PM PDT 24 May 05 02:38:46 PM PDT 24 342077405 ps
T83 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3442145257 May 05 02:38:34 PM PDT 24 May 05 02:38:55 PM PDT 24 7953379619 ps
T370 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1999701602 May 05 02:38:22 PM PDT 24 May 05 02:38:34 PM PDT 24 4253391196 ps
T819 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1233850693 May 05 02:38:19 PM PDT 24 May 05 02:38:23 PM PDT 24 850184363 ps
T134 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3425699365 May 05 02:38:38 PM PDT 24 May 05 02:38:39 PM PDT 24 407541190 ps
T820 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3420514414 May 05 02:38:24 PM PDT 24 May 05 02:38:27 PM PDT 24 365849886 ps
T821 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3224206535 May 05 02:38:19 PM PDT 24 May 05 02:38:30 PM PDT 24 4115227002 ps
T822 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2234792145 May 05 02:38:46 PM PDT 24 May 05 02:38:47 PM PDT 24 453033273 ps
T823 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3082794746 May 05 02:38:09 PM PDT 24 May 05 02:38:11 PM PDT 24 459907159 ps
T824 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2527557558 May 05 02:38:45 PM PDT 24 May 05 02:38:47 PM PDT 24 409297849 ps
T135 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1843018889 May 05 02:38:13 PM PDT 24 May 05 02:38:18 PM PDT 24 1233695976 ps
T825 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3292745291 May 05 02:38:18 PM PDT 24 May 05 02:39:17 PM PDT 24 27132324115 ps
T136 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2493688470 May 05 02:38:10 PM PDT 24 May 05 02:38:13 PM PDT 24 697457460 ps
T826 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1702864135 May 05 02:38:31 PM PDT 24 May 05 02:38:38 PM PDT 24 4199975385 ps
T827 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2549607894 May 05 02:38:29 PM PDT 24 May 05 02:38:31 PM PDT 24 323099154 ps
T828 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2077160410 May 05 02:38:24 PM PDT 24 May 05 02:38:27 PM PDT 24 388142896 ps
T829 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1360223675 May 05 02:38:49 PM PDT 24 May 05 02:38:51 PM PDT 24 296046234 ps
T830 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1291292418 May 05 02:38:40 PM PDT 24 May 05 02:38:45 PM PDT 24 4637430430 ps
T831 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4084448788 May 05 02:38:50 PM PDT 24 May 05 02:38:51 PM PDT 24 374226890 ps
T832 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.746833818 May 05 02:38:24 PM PDT 24 May 05 02:38:26 PM PDT 24 452751610 ps
T833 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1186284236 May 05 02:38:26 PM PDT 24 May 05 02:38:29 PM PDT 24 502555355 ps
T834 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.376099013 May 05 02:38:14 PM PDT 24 May 05 02:38:17 PM PDT 24 2429953196 ps
T835 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3219317309 May 05 02:38:31 PM PDT 24 May 05 02:38:34 PM PDT 24 405116192 ps
T84 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.998805493 May 05 02:38:40 PM PDT 24 May 05 02:38:55 PM PDT 24 8443249992 ps
T836 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.383989923 May 05 02:38:45 PM PDT 24 May 05 02:38:46 PM PDT 24 300406961 ps
T837 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.815466940 May 05 02:38:49 PM PDT 24 May 05 02:38:51 PM PDT 24 492294496 ps
T838 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3331366299 May 05 02:38:10 PM PDT 24 May 05 02:38:15 PM PDT 24 4840740299 ps
T839 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2303736053 May 05 02:38:43 PM PDT 24 May 05 02:38:45 PM PDT 24 635999286 ps
T840 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1815724390 May 05 02:38:22 PM PDT 24 May 05 02:38:26 PM PDT 24 2712708960 ps
T841 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3282542101 May 05 02:38:12 PM PDT 24 May 05 02:38:13 PM PDT 24 590710059 ps
T842 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2746695981 May 05 02:38:29 PM PDT 24 May 05 02:38:41 PM PDT 24 4105673384 ps
T843 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2799692170 May 05 02:38:30 PM PDT 24 May 05 02:38:33 PM PDT 24 427924778 ps
T844 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.344505039 May 05 02:38:38 PM PDT 24 May 05 02:38:55 PM PDT 24 5007978943 ps
T845 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2091616762 May 05 02:38:24 PM PDT 24 May 05 02:38:27 PM PDT 24 647377775 ps
T846 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4007813647 May 05 02:38:39 PM PDT 24 May 05 02:38:46 PM PDT 24 4821724282 ps
T847 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1594208139 May 05 02:38:05 PM PDT 24 May 05 02:38:06 PM PDT 24 419300648 ps
T848 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3976346307 May 05 02:38:30 PM PDT 24 May 05 02:38:32 PM PDT 24 414408156 ps
T849 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1231129323 May 05 02:38:29 PM PDT 24 May 05 02:38:40 PM PDT 24 4037960203 ps
T850 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2452287965 May 05 02:38:09 PM PDT 24 May 05 02:38:46 PM PDT 24 26581668953 ps
T851 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3786717534 May 05 02:38:44 PM PDT 24 May 05 02:38:45 PM PDT 24 330795016 ps
T852 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.238196153 May 05 02:38:30 PM PDT 24 May 05 02:38:31 PM PDT 24 374629573 ps
T853 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1790478856 May 05 02:38:09 PM PDT 24 May 05 02:38:10 PM PDT 24 355777250 ps
T854 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3578931951 May 05 02:38:40 PM PDT 24 May 05 02:38:44 PM PDT 24 391958443 ps
T137 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2226068810 May 05 02:38:12 PM PDT 24 May 05 02:38:14 PM PDT 24 1278285867 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1158491362 May 05 02:38:13 PM PDT 24 May 05 02:38:16 PM PDT 24 415853106 ps
T138 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3075241582 May 05 02:38:10 PM PDT 24 May 05 02:38:12 PM PDT 24 494086869 ps
T856 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.368036750 May 05 02:38:11 PM PDT 24 May 05 02:38:23 PM PDT 24 4364553613 ps
T857 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2220290780 May 05 02:38:44 PM PDT 24 May 05 02:38:46 PM PDT 24 335804583 ps
T858 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2336920760 May 05 02:38:24 PM PDT 24 May 05 02:38:29 PM PDT 24 720186408 ps
T859 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4119969131 May 05 02:38:28 PM PDT 24 May 05 02:38:30 PM PDT 24 618659248 ps
T860 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2884106492 May 05 02:38:30 PM PDT 24 May 05 02:38:32 PM PDT 24 337578499 ps
T861 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1520612016 May 05 02:38:13 PM PDT 24 May 05 02:38:14 PM PDT 24 345655068 ps
T862 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2699751111 May 05 02:38:50 PM PDT 24 May 05 02:38:52 PM PDT 24 467733469 ps
T863 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3644128592 May 05 02:38:46 PM PDT 24 May 05 02:38:48 PM PDT 24 293098424 ps
T864 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3810057813 May 05 02:38:43 PM PDT 24 May 05 02:38:45 PM PDT 24 318910910 ps
T865 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.818916322 May 05 02:38:15 PM PDT 24 May 05 02:38:17 PM PDT 24 425612769 ps
T866 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4147294923 May 05 02:38:04 PM PDT 24 May 05 02:38:16 PM PDT 24 9460628152 ps
T867 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2725865067 May 05 02:38:26 PM PDT 24 May 05 02:38:30 PM PDT 24 1698467693 ps
T868 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.403883781 May 05 02:38:44 PM PDT 24 May 05 02:38:46 PM PDT 24 313763076 ps
T869 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1029670273 May 05 02:38:11 PM PDT 24 May 05 02:38:15 PM PDT 24 2298769942 ps
T870 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3054286137 May 05 02:38:09 PM PDT 24 May 05 02:38:11 PM PDT 24 367185405 ps
T871 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3825588588 May 05 02:38:38 PM PDT 24 May 05 02:38:40 PM PDT 24 492516735 ps
T872 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.663106024 May 05 02:38:50 PM PDT 24 May 05 02:38:52 PM PDT 24 400497610 ps
T873 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.68034470 May 05 02:38:36 PM PDT 24 May 05 02:38:39 PM PDT 24 560311908 ps
T874 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2533419718 May 05 02:38:27 PM PDT 24 May 05 02:38:30 PM PDT 24 626626850 ps
T875 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2513450992 May 05 02:38:20 PM PDT 24 May 05 02:38:35 PM PDT 24 4301471054 ps
T876 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3818947928 May 05 02:38:19 PM PDT 24 May 05 02:38:24 PM PDT 24 4185324448 ps
T877 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.305656133 May 05 02:38:14 PM PDT 24 May 05 02:38:16 PM PDT 24 360175987 ps
T878 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2107092241 May 05 02:38:26 PM PDT 24 May 05 02:38:29 PM PDT 24 477588503 ps
T879 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2832734057 May 05 02:38:52 PM PDT 24 May 05 02:38:54 PM PDT 24 338744554 ps
T880 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.647281872 May 05 02:38:37 PM PDT 24 May 05 02:38:40 PM PDT 24 505133739 ps
T881 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3808183827 May 05 02:38:26 PM PDT 24 May 05 02:38:28 PM PDT 24 320372729 ps
T882 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4217118094 May 05 02:38:39 PM PDT 24 May 05 02:38:57 PM PDT 24 5105169130 ps
T883 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1100807512 May 05 02:38:24 PM PDT 24 May 05 02:38:32 PM PDT 24 8594986687 ps
T884 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.4004856136 May 05 02:38:30 PM PDT 24 May 05 02:38:34 PM PDT 24 535364430 ps
T885 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1102986273 May 05 02:38:38 PM PDT 24 May 05 02:38:40 PM PDT 24 546817160 ps
T886 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.411290693 May 05 02:38:38 PM PDT 24 May 05 02:38:40 PM PDT 24 445606371 ps
T887 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1643479864 May 05 02:38:50 PM PDT 24 May 05 02:38:52 PM PDT 24 465880526 ps
T888 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1339544290 May 05 02:38:30 PM PDT 24 May 05 02:38:32 PM PDT 24 372584469 ps
T889 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.337859800 May 05 02:38:13 PM PDT 24 May 05 02:38:15 PM PDT 24 493347660 ps
T890 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.4056731275 May 05 02:38:28 PM PDT 24 May 05 02:38:30 PM PDT 24 381641306 ps
T891 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.982744239 May 05 02:38:40 PM PDT 24 May 05 02:38:42 PM PDT 24 499430906 ps
T892 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1417732570 May 05 02:38:45 PM PDT 24 May 05 02:38:50 PM PDT 24 2353576912 ps
T893 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2680065843 May 05 02:38:13 PM PDT 24 May 05 02:38:15 PM PDT 24 566710914 ps
T894 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3769603414 May 05 02:38:10 PM PDT 24 May 05 02:38:12 PM PDT 24 342725322 ps
T895 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3427729900 May 05 02:38:24 PM PDT 24 May 05 02:38:26 PM PDT 24 318734002 ps
T896 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1348115363 May 05 02:38:14 PM PDT 24 May 05 02:38:17 PM PDT 24 757670378 ps
T897 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4176111685 May 05 02:38:26 PM PDT 24 May 05 02:38:28 PM PDT 24 393784862 ps
T898 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.491807206 May 05 02:38:42 PM PDT 24 May 05 02:38:43 PM PDT 24 586696927 ps
T899 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2616203015 May 05 02:38:08 PM PDT 24 May 05 02:38:11 PM PDT 24 472834619 ps
T900 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1830224753 May 05 02:38:37 PM PDT 24 May 05 02:38:38 PM PDT 24 340287564 ps
T901 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.564213058 May 05 02:38:45 PM PDT 24 May 05 02:38:47 PM PDT 24 285637751 ps
T902 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3939440542 May 05 02:38:42 PM PDT 24 May 05 02:38:44 PM PDT 24 466200722 ps
T903 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1781143927 May 05 02:38:49 PM PDT 24 May 05 02:38:50 PM PDT 24 385199502 ps
T904 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1833149155 May 05 02:38:15 PM PDT 24 May 05 02:38:21 PM PDT 24 8088431297 ps
T905 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4135861986 May 05 02:38:30 PM PDT 24 May 05 02:38:38 PM PDT 24 8532258517 ps
T906 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2422929543 May 05 02:38:41 PM PDT 24 May 05 02:38:43 PM PDT 24 722175029 ps
T907 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3002208644 May 05 02:38:38 PM PDT 24 May 05 02:38:50 PM PDT 24 8237615895 ps
T908 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2878498551 May 05 02:38:24 PM PDT 24 May 05 02:38:26 PM PDT 24 491988396 ps
T909 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3472923708 May 05 02:38:44 PM PDT 24 May 05 02:38:45 PM PDT 24 517699281 ps
T910 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3952144799 May 05 02:38:24 PM PDT 24 May 05 02:38:27 PM PDT 24 660043878 ps
T911 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2235346782 May 05 02:38:34 PM PDT 24 May 05 02:38:36 PM PDT 24 428505156 ps
T912 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3089185938 May 05 02:38:35 PM PDT 24 May 05 02:38:36 PM PDT 24 436461268 ps
T913 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3585241111 May 05 02:38:44 PM PDT 24 May 05 02:38:46 PM PDT 24 587864256 ps
T914 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2277765088 May 05 02:38:49 PM PDT 24 May 05 02:38:50 PM PDT 24 336525638 ps
T915 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4139268900 May 05 02:38:18 PM PDT 24 May 05 02:38:19 PM PDT 24 498337477 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3252658717 May 05 02:38:13 PM PDT 24 May 05 02:38:15 PM PDT 24 766545533 ps
T917 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3750615606 May 05 02:38:40 PM PDT 24 May 05 02:38:42 PM PDT 24 468330540 ps
T918 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.746840075 May 05 02:38:50 PM PDT 24 May 05 02:38:51 PM PDT 24 304872187 ps
T919 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1529275594 May 05 02:38:30 PM PDT 24 May 05 02:38:33 PM PDT 24 465186247 ps

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.4021820746
Short name T8
Test name
Test status
Simulation time 614384563116 ps
CPU time 1394.95 seconds
Started May 05 02:56:45 PM PDT 24
Finished May 05 03:20:01 PM PDT 24
Peak memory 202304 kb
Host smart-ea09d188-0c5d-4dbc-8f4b-271b621786a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021820746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.4021820746
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.866112100
Short name T43
Test name
Test status
Simulation time 87220712353 ps
CPU time 331.48 seconds
Started May 05 02:55:53 PM PDT 24
Finished May 05 03:01:25 PM PDT 24
Peak memory 202640 kb
Host smart-93d86c09-3a50-4ed1-8c83-db63322a8c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866112100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.866112100
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2625106415
Short name T51
Test name
Test status
Simulation time 564787065287 ps
CPU time 587.19 seconds
Started May 05 02:57:41 PM PDT 24
Finished May 05 03:07:28 PM PDT 24
Peak memory 202348 kb
Host smart-9b23f687-f460-4571-8ae7-5bc57b758138
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625106415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2625106415
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1408209064
Short name T18
Test name
Test status
Simulation time 47082843089 ps
CPU time 116.37 seconds
Started May 05 02:54:21 PM PDT 24
Finished May 05 02:56:18 PM PDT 24
Peak memory 210628 kb
Host smart-47b7b523-d073-4fa2-abb7-e31ed20df44b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408209064 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1408209064
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3366531536
Short name T165
Test name
Test status
Simulation time 529021930172 ps
CPU time 1266.45 seconds
Started May 05 02:57:20 PM PDT 24
Finished May 05 03:18:27 PM PDT 24
Peak memory 202296 kb
Host smart-c0a98bce-2c6f-4ed6-b4b1-5d2bbe7b7a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366531536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3366531536
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1276882371
Short name T152
Test name
Test status
Simulation time 486932553282 ps
CPU time 305.2 seconds
Started May 05 02:53:47 PM PDT 24
Finished May 05 02:58:53 PM PDT 24
Peak memory 202284 kb
Host smart-e8e67bd2-54b1-4605-92b8-009317016b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276882371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1276882371
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2302559073
Short name T187
Test name
Test status
Simulation time 532258916456 ps
CPU time 1022.41 seconds
Started May 05 02:51:36 PM PDT 24
Finished May 05 03:08:39 PM PDT 24
Peak memory 202384 kb
Host smart-e8b1b520-f281-4321-a120-aa37e2d18ab3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302559073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2302559073
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1640965280
Short name T6
Test name
Test status
Simulation time 338715316683 ps
CPU time 829.92 seconds
Started May 05 02:57:43 PM PDT 24
Finished May 05 03:11:34 PM PDT 24
Peak memory 202284 kb
Host smart-5b1842ad-ddb5-4c6c-ab5d-9772da2a0771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640965280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1640965280
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2390522050
Short name T56
Test name
Test status
Simulation time 449342042852 ps
CPU time 932.46 seconds
Started May 05 02:53:08 PM PDT 24
Finished May 05 03:08:41 PM PDT 24
Peak memory 202700 kb
Host smart-3cc5dd2a-32bb-4f22-97a6-f04c8d9e84f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390522050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2390522050
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2178552226
Short name T173
Test name
Test status
Simulation time 494199042661 ps
CPU time 850.74 seconds
Started May 05 02:56:10 PM PDT 24
Finished May 05 03:10:21 PM PDT 24
Peak memory 202292 kb
Host smart-9fb3f865-1399-402e-a713-1d5d1c0b1229
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178552226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2178552226
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3846640848
Short name T170
Test name
Test status
Simulation time 325031459546 ps
CPU time 110.65 seconds
Started May 05 02:52:47 PM PDT 24
Finished May 05 02:54:38 PM PDT 24
Peak memory 202280 kb
Host smart-94611f97-748a-43e7-929b-d70cd9869e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846640848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3846640848
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2877111102
Short name T76
Test name
Test status
Simulation time 736692115 ps
CPU time 2.81 seconds
Started May 05 02:38:36 PM PDT 24
Finished May 05 02:38:39 PM PDT 24
Peak memory 217804 kb
Host smart-df42b8e5-e0a9-43f7-947f-8f14db882f41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877111102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2877111102
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2221362588
Short name T167
Test name
Test status
Simulation time 535281068055 ps
CPU time 676.94 seconds
Started May 05 02:51:16 PM PDT 24
Finished May 05 03:02:33 PM PDT 24
Peak memory 202220 kb
Host smart-7a4d7fae-62d4-4703-bcc0-4dc792bd4651
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221362588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2221362588
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2682591069
Short name T71
Test name
Test status
Simulation time 8055240941 ps
CPU time 4.38 seconds
Started May 05 02:51:21 PM PDT 24
Finished May 05 02:51:26 PM PDT 24
Peak memory 218872 kb
Host smart-5401e77f-b24f-486a-8aac-f61d4108c874
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682591069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2682591069
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2419518497
Short name T156
Test name
Test status
Simulation time 536244495826 ps
CPU time 116.97 seconds
Started May 05 02:53:29 PM PDT 24
Finished May 05 02:55:26 PM PDT 24
Peak memory 202296 kb
Host smart-b44ed496-d986-48b1-a2b8-f6a0ec67b471
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419518497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2419518497
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1120613912
Short name T253
Test name
Test status
Simulation time 505625133420 ps
CPU time 302.24 seconds
Started May 05 02:56:32 PM PDT 24
Finished May 05 03:01:35 PM PDT 24
Peak memory 202184 kb
Host smart-bbf87cd7-201a-4316-b973-c2770183c31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120613912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1120613912
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2425246560
Short name T199
Test name
Test status
Simulation time 496497338215 ps
CPU time 259.83 seconds
Started May 05 02:53:04 PM PDT 24
Finished May 05 02:57:24 PM PDT 24
Peak memory 202312 kb
Host smart-c02b7309-c4cb-4a6f-bcaf-06d34efda16e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425246560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2425246560
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1341973672
Short name T61
Test name
Test status
Simulation time 357797973 ps
CPU time 1.65 seconds
Started May 05 02:38:23 PM PDT 24
Finished May 05 02:38:25 PM PDT 24
Peak memory 201200 kb
Host smart-59e6c2b7-9926-45d1-acb1-204168725ad2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341973672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1341973672
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.4011457755
Short name T11
Test name
Test status
Simulation time 377882844981 ps
CPU time 448.04 seconds
Started May 05 02:54:52 PM PDT 24
Finished May 05 03:02:20 PM PDT 24
Peak memory 202300 kb
Host smart-cb849b2b-2efc-4b64-8eed-01eb7b173007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011457755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.4011457755
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3656989214
Short name T247
Test name
Test status
Simulation time 337625930783 ps
CPU time 781.67 seconds
Started May 05 02:53:57 PM PDT 24
Finished May 05 03:06:59 PM PDT 24
Peak memory 202320 kb
Host smart-9cf8ebd1-9914-4c9b-9a91-f4e24bcc78de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656989214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3656989214
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.220267181
Short name T263
Test name
Test status
Simulation time 623575554045 ps
CPU time 760.17 seconds
Started May 05 02:51:37 PM PDT 24
Finished May 05 03:04:18 PM PDT 24
Peak memory 202384 kb
Host smart-d9bf974b-839b-4000-9363-f68518b267b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220267181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.220267181
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2331601738
Short name T40
Test name
Test status
Simulation time 413407825931 ps
CPU time 357.82 seconds
Started May 05 02:56:20 PM PDT 24
Finished May 05 03:02:18 PM PDT 24
Peak memory 210980 kb
Host smart-811e8430-4d3c-437a-aa46-75c5a8de034d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331601738 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2331601738
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2902178207
Short name T351
Test name
Test status
Simulation time 637916249737 ps
CPU time 730.68 seconds
Started May 05 02:57:09 PM PDT 24
Finished May 05 03:09:20 PM PDT 24
Peak memory 210932 kb
Host smart-adb3d6df-cb4f-4086-8f82-47a1430339da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902178207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2902178207
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2049178412
Short name T161
Test name
Test status
Simulation time 533763954788 ps
CPU time 589.06 seconds
Started May 05 02:57:16 PM PDT 24
Finished May 05 03:07:06 PM PDT 24
Peak memory 202320 kb
Host smart-aa1329bd-0cbd-4545-a49a-100c0bce95e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049178412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2049178412
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1405585372
Short name T184
Test name
Test status
Simulation time 428211307620 ps
CPU time 1160.38 seconds
Started May 05 02:53:14 PM PDT 24
Finished May 05 03:12:35 PM PDT 24
Peak memory 210824 kb
Host smart-b924c7df-03d2-45c6-bfb6-942371bfe152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405585372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1405585372
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2523593640
Short name T151
Test name
Test status
Simulation time 495828508523 ps
CPU time 643.91 seconds
Started May 05 02:53:43 PM PDT 24
Finished May 05 03:04:28 PM PDT 24
Peak memory 202260 kb
Host smart-190f2039-641e-45c4-ac4a-8298199d3965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523593640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2523593640
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1194308641
Short name T330
Test name
Test status
Simulation time 528941806417 ps
CPU time 147.13 seconds
Started May 05 02:56:03 PM PDT 24
Finished May 05 02:58:30 PM PDT 24
Peak memory 202360 kb
Host smart-7524545c-5f29-4558-9a5e-ffc148271728
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194308641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1194308641
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3268237917
Short name T305
Test name
Test status
Simulation time 347312568439 ps
CPU time 860.33 seconds
Started May 05 02:55:22 PM PDT 24
Finished May 05 03:09:43 PM PDT 24
Peak memory 202280 kb
Host smart-5e698511-5988-43e2-9ca6-3952bf3b9180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268237917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3268237917
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3976441786
Short name T242
Test name
Test status
Simulation time 578469629654 ps
CPU time 865.55 seconds
Started May 05 02:57:12 PM PDT 24
Finished May 05 03:11:38 PM PDT 24
Peak memory 202356 kb
Host smart-044dc479-b904-4e10-941b-5e9b9467423c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976441786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3976441786
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3442145257
Short name T83
Test name
Test status
Simulation time 7953379619 ps
CPU time 19.96 seconds
Started May 05 02:38:34 PM PDT 24
Finished May 05 02:38:55 PM PDT 24
Peak memory 201464 kb
Host smart-21c2e7d6-edd1-411f-a67c-3ceab72c881e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442145257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3442145257
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3743476090
Short name T214
Test name
Test status
Simulation time 302158298 ps
CPU time 1.31 seconds
Started May 05 02:53:08 PM PDT 24
Finished May 05 02:53:10 PM PDT 24
Peak memory 201992 kb
Host smart-8dbd3457-f864-483a-a4dc-9071249a9b80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743476090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3743476090
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.46387887
Short name T316
Test name
Test status
Simulation time 387068300446 ps
CPU time 225.52 seconds
Started May 05 02:56:15 PM PDT 24
Finished May 05 03:00:01 PM PDT 24
Peak memory 202372 kb
Host smart-24ae634f-2041-4ef5-a7af-71b37b254a7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46387887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gatin
g.46387887
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2490657587
Short name T226
Test name
Test status
Simulation time 328113300404 ps
CPU time 201.98 seconds
Started May 05 02:51:36 PM PDT 24
Finished May 05 02:54:58 PM PDT 24
Peak memory 202300 kb
Host smart-39542824-24c0-4574-ab7e-1ba250e5ef9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490657587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2490657587
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1194686805
Short name T273
Test name
Test status
Simulation time 381721728229 ps
CPU time 885.57 seconds
Started May 05 02:51:50 PM PDT 24
Finished May 05 03:06:36 PM PDT 24
Peak memory 202308 kb
Host smart-66860e36-1d60-465e-ab39-6f31c5e076a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194686805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1194686805
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.4077563958
Short name T340
Test name
Test status
Simulation time 371344856113 ps
CPU time 413.4 seconds
Started May 05 02:55:06 PM PDT 24
Finished May 05 03:02:00 PM PDT 24
Peak memory 202276 kb
Host smart-4f4fd56c-2a6a-45d8-b456-9a25e88b0b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077563958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.4077563958
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2812945146
Short name T256
Test name
Test status
Simulation time 491391270439 ps
CPU time 1166.26 seconds
Started May 05 02:56:11 PM PDT 24
Finished May 05 03:15:37 PM PDT 24
Peak memory 202464 kb
Host smart-fe2d5770-4f0e-4668-9c99-cab6aae7ad86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812945146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2812945146
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2600585204
Short name T64
Test name
Test status
Simulation time 357076544527 ps
CPU time 497.52 seconds
Started May 05 02:52:07 PM PDT 24
Finished May 05 03:00:25 PM PDT 24
Peak memory 202272 kb
Host smart-b6b4f7e8-ca5f-4782-ab0a-14a805104fd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600585204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2600585204
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.131499614
Short name T228
Test name
Test status
Simulation time 522891233177 ps
CPU time 280.97 seconds
Started May 05 02:53:06 PM PDT 24
Finished May 05 02:57:47 PM PDT 24
Peak memory 202296 kb
Host smart-8e4a41ef-1482-4a32-b067-e6de00b744a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131499614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.131499614
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.549426114
Short name T317
Test name
Test status
Simulation time 520104131854 ps
CPU time 1248.21 seconds
Started May 05 02:52:16 PM PDT 24
Finished May 05 03:13:04 PM PDT 24
Peak memory 202304 kb
Host smart-28879320-d46e-460c-9c41-01d4f3bf5a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549426114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.549426114
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.676733539
Short name T306
Test name
Test status
Simulation time 508605007807 ps
CPU time 301.15 seconds
Started May 05 02:53:22 PM PDT 24
Finished May 05 02:58:24 PM PDT 24
Peak memory 202376 kb
Host smart-453d6d73-d0f0-46bb-acee-46f0ddb9bdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676733539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.676733539
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1141560792
Short name T265
Test name
Test status
Simulation time 398646757883 ps
CPU time 224.32 seconds
Started May 05 02:56:38 PM PDT 24
Finished May 05 03:00:22 PM PDT 24
Peak memory 202364 kb
Host smart-1d79b65f-804d-47e0-a3a2-de8b6861a5d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141560792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1141560792
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3154103419
Short name T354
Test name
Test status
Simulation time 367793525785 ps
CPU time 887.57 seconds
Started May 05 02:52:46 PM PDT 24
Finished May 05 03:07:34 PM PDT 24
Peak memory 202284 kb
Host smart-572f4310-7c6b-495e-85eb-62e811377723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154103419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3154103419
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2983627440
Short name T192
Test name
Test status
Simulation time 506441140972 ps
CPU time 615.89 seconds
Started May 05 02:57:28 PM PDT 24
Finished May 05 03:07:44 PM PDT 24
Peak memory 202300 kb
Host smart-86d83820-99f6-404f-b56c-c93ab4b51686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983627440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2983627440
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3804751173
Short name T279
Test name
Test status
Simulation time 337268719400 ps
CPU time 408.38 seconds
Started May 05 02:52:01 PM PDT 24
Finished May 05 02:58:50 PM PDT 24
Peak memory 202304 kb
Host smart-4fc23a23-2567-449e-bd79-fe18a723ecda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804751173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3804751173
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1927184896
Short name T217
Test name
Test status
Simulation time 549366959846 ps
CPU time 513.64 seconds
Started May 05 02:52:09 PM PDT 24
Finished May 05 03:00:43 PM PDT 24
Peak memory 202288 kb
Host smart-e5402e7b-c09b-4c72-96e9-73624134eff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927184896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1927184896
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.607547363
Short name T193
Test name
Test status
Simulation time 360880607309 ps
CPU time 67.6 seconds
Started May 05 02:56:42 PM PDT 24
Finished May 05 02:57:50 PM PDT 24
Peak memory 202300 kb
Host smart-d9bbccc2-e5d2-49a2-92b7-b02ca71f6620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607547363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.607547363
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.753289541
Short name T63
Test name
Test status
Simulation time 4111529236 ps
CPU time 8.49 seconds
Started May 05 02:38:10 PM PDT 24
Finished May 05 02:38:19 PM PDT 24
Peak memory 201476 kb
Host smart-f4fe0867-dce7-4d31-b515-b5efc8635fea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753289541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.753289541
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2276319100
Short name T294
Test name
Test status
Simulation time 564329936094 ps
CPU time 647.23 seconds
Started May 05 02:53:55 PM PDT 24
Finished May 05 03:04:42 PM PDT 24
Peak memory 202400 kb
Host smart-998c32df-f02b-4625-8f8e-db9cf160c03a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276319100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2276319100
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3536389846
Short name T243
Test name
Test status
Simulation time 486651841332 ps
CPU time 1021.19 seconds
Started May 05 02:57:09 PM PDT 24
Finished May 05 03:14:11 PM PDT 24
Peak memory 202248 kb
Host smart-2df0ab30-39a5-4577-b07c-d7cb4733a8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536389846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3536389846
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3914547850
Short name T288
Test name
Test status
Simulation time 348578740075 ps
CPU time 427.98 seconds
Started May 05 02:51:13 PM PDT 24
Finished May 05 02:58:22 PM PDT 24
Peak memory 202260 kb
Host smart-344d6fa2-63c2-4d54-b619-5d57edf255b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914547850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3914547850
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.168237708
Short name T270
Test name
Test status
Simulation time 374647097519 ps
CPU time 914.25 seconds
Started May 05 02:52:35 PM PDT 24
Finished May 05 03:07:50 PM PDT 24
Peak memory 202240 kb
Host smart-40560be2-1518-4f0b-9fab-778d94e69d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168237708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
168237708
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.4185646208
Short name T25
Test name
Test status
Simulation time 177018576285 ps
CPU time 211.89 seconds
Started May 05 02:54:00 PM PDT 24
Finished May 05 02:57:32 PM PDT 24
Peak memory 219004 kb
Host smart-4d729d26-e735-4971-9fff-e9c1cd1fb149
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185646208 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.4185646208
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3974424514
Short name T308
Test name
Test status
Simulation time 413625766854 ps
CPU time 274.09 seconds
Started May 05 02:54:08 PM PDT 24
Finished May 05 02:58:42 PM PDT 24
Peak memory 210968 kb
Host smart-a4ec80a5-7beb-42f4-8f62-2b9bfb23278f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974424514 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3974424514
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1023680241
Short name T38
Test name
Test status
Simulation time 300990268395 ps
CPU time 943.54 seconds
Started May 05 02:56:03 PM PDT 24
Finished May 05 03:11:47 PM PDT 24
Peak memory 218996 kb
Host smart-e9cbd477-fcf4-4910-bec4-15866b6727a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023680241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1023680241
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3891072394
Short name T264
Test name
Test status
Simulation time 513982457907 ps
CPU time 1198.13 seconds
Started May 05 02:52:01 PM PDT 24
Finished May 05 03:12:00 PM PDT 24
Peak memory 202272 kb
Host smart-406c9367-57a7-41cb-891e-e51871fb7f60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891072394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3891072394
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2872950390
Short name T289
Test name
Test status
Simulation time 366567475657 ps
CPU time 812.09 seconds
Started May 05 02:53:04 PM PDT 24
Finished May 05 03:06:37 PM PDT 24
Peak memory 202276 kb
Host smart-0ab51e36-cec3-4157-a105-5d7de173aaa9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872950390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2872950390
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3502550900
Short name T259
Test name
Test status
Simulation time 164841824952 ps
CPU time 45.49 seconds
Started May 05 02:51:43 PM PDT 24
Finished May 05 02:52:29 PM PDT 24
Peak memory 202300 kb
Host smart-9f820e1a-50cb-456f-8c00-c4206d907798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502550900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3502550900
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1637495948
Short name T15
Test name
Test status
Simulation time 83487049751 ps
CPU time 111.73 seconds
Started May 05 02:51:56 PM PDT 24
Finished May 05 02:53:48 PM PDT 24
Peak memory 210568 kb
Host smart-5b259e5c-4733-4fa1-b5e3-bea73da29ea6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637495948 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1637495948
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3849057253
Short name T347
Test name
Test status
Simulation time 529863744798 ps
CPU time 331.93 seconds
Started May 05 02:55:41 PM PDT 24
Finished May 05 03:01:14 PM PDT 24
Peak memory 202304 kb
Host smart-f64625c3-5172-419e-a6f0-172f8a468b2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849057253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3849057253
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1968978779
Short name T269
Test name
Test status
Simulation time 167328934597 ps
CPU time 385.83 seconds
Started May 05 02:56:24 PM PDT 24
Finished May 05 03:02:50 PM PDT 24
Peak memory 202296 kb
Host smart-35b40775-6a84-45e0-836b-0ee240764527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968978779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1968978779
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1001182152
Short name T240
Test name
Test status
Simulation time 215332516649 ps
CPU time 39.76 seconds
Started May 05 02:56:32 PM PDT 24
Finished May 05 02:57:12 PM PDT 24
Peak memory 202228 kb
Host smart-94339209-5eb9-4424-9685-0bb87e8a0966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001182152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1001182152
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.4222367354
Short name T58
Test name
Test status
Simulation time 371000083598 ps
CPU time 1276.64 seconds
Started May 05 02:53:00 PM PDT 24
Finished May 05 03:14:17 PM PDT 24
Peak memory 210820 kb
Host smart-48d69c07-7b09-4768-8984-d5e7cc9fc537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222367354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.4222367354
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3027401857
Short name T224
Test name
Test status
Simulation time 340624170920 ps
CPU time 211.23 seconds
Started May 05 02:53:35 PM PDT 24
Finished May 05 02:57:07 PM PDT 24
Peak memory 202356 kb
Host smart-915fceb4-f708-4ae5-93ca-b672a895c10e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027401857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3027401857
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1857215289
Short name T307
Test name
Test status
Simulation time 24147169138 ps
CPU time 55.61 seconds
Started May 05 02:53:55 PM PDT 24
Finished May 05 02:54:51 PM PDT 24
Peak memory 210612 kb
Host smart-e5176045-931b-491a-83fb-8f34bb0d842d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857215289 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1857215289
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.203753177
Short name T46
Test name
Test status
Simulation time 165989038095 ps
CPU time 372.97 seconds
Started May 05 02:56:16 PM PDT 24
Finished May 05 03:02:30 PM PDT 24
Peak memory 202380 kb
Host smart-193a05d0-13d9-441a-9181-d5d13c9276f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203753177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.203753177
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2197022630
Short name T315
Test name
Test status
Simulation time 166819719840 ps
CPU time 191.66 seconds
Started May 05 02:56:16 PM PDT 24
Finished May 05 02:59:28 PM PDT 24
Peak memory 202292 kb
Host smart-edce48a9-6902-46da-a329-322207a88186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197022630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2197022630
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1268235975
Short name T338
Test name
Test status
Simulation time 357197377291 ps
CPU time 223.9 seconds
Started May 05 02:56:52 PM PDT 24
Finished May 05 03:00:36 PM PDT 24
Peak memory 202260 kb
Host smart-971d850c-2991-47a5-8083-bb36a8b4eb6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268235975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1268235975
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2849768510
Short name T371
Test name
Test status
Simulation time 522785133323 ps
CPU time 961.8 seconds
Started May 05 02:51:40 PM PDT 24
Finished May 05 03:07:42 PM PDT 24
Peak memory 210976 kb
Host smart-0328ccde-5122-4c10-9eb1-8bbc55c6cd06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849768510 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2849768510
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3479876061
Short name T169
Test name
Test status
Simulation time 534361368523 ps
CPU time 1203.73 seconds
Started May 05 02:51:15 PM PDT 24
Finished May 05 03:11:19 PM PDT 24
Peak memory 202400 kb
Host smart-374deae0-8b0e-4560-8888-84d310573453
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479876061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3479876061
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1657977291
Short name T277
Test name
Test status
Simulation time 107684795032 ps
CPU time 166.37 seconds
Started May 05 02:52:04 PM PDT 24
Finished May 05 02:54:51 PM PDT 24
Peak memory 210740 kb
Host smart-a8af57a8-076b-4e06-b83c-85df722c2e15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657977291 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1657977291
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2580072657
Short name T257
Test name
Test status
Simulation time 341401549131 ps
CPU time 205.19 seconds
Started May 05 02:52:29 PM PDT 24
Finished May 05 02:55:54 PM PDT 24
Peak memory 202300 kb
Host smart-6b8c98ee-3991-48b5-a652-03ccac16ff10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580072657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2580072657
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3128079165
Short name T344
Test name
Test status
Simulation time 164170734596 ps
CPU time 196.97 seconds
Started May 05 02:52:25 PM PDT 24
Finished May 05 02:55:42 PM PDT 24
Peak memory 202208 kb
Host smart-873d659f-66d7-4097-93e4-fe35bfa652b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128079165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3128079165
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2632805913
Short name T276
Test name
Test status
Simulation time 360620764799 ps
CPU time 896.7 seconds
Started May 05 02:53:00 PM PDT 24
Finished May 05 03:07:58 PM PDT 24
Peak memory 202220 kb
Host smart-7e7c6bcc-a92e-49fc-aab3-0e350082ee75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632805913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2632805913
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2233346131
Short name T236
Test name
Test status
Simulation time 105999424547 ps
CPU time 345.7 seconds
Started May 05 02:53:32 PM PDT 24
Finished May 05 02:59:18 PM PDT 24
Peak memory 202632 kb
Host smart-7b352154-d359-4c8c-85ad-bd6e4830be03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233346131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2233346131
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.310922940
Short name T59
Test name
Test status
Simulation time 283222771935 ps
CPU time 373.18 seconds
Started May 05 02:53:51 PM PDT 24
Finished May 05 03:00:05 PM PDT 24
Peak memory 210804 kb
Host smart-babf9503-39ef-4224-b2b4-3ea7b72b5d27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310922940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
310922940
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.913064284
Short name T118
Test name
Test status
Simulation time 356356047284 ps
CPU time 63.2 seconds
Started May 05 02:54:18 PM PDT 24
Finished May 05 02:55:22 PM PDT 24
Peak memory 202372 kb
Host smart-1e8e2ea5-e064-438e-9647-93317a5dd66f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913064284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.913064284
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.4156247378
Short name T155
Test name
Test status
Simulation time 375676622904 ps
CPU time 252.82 seconds
Started May 05 02:55:05 PM PDT 24
Finished May 05 02:59:18 PM PDT 24
Peak memory 202376 kb
Host smart-51537ca5-10b4-476f-8291-a2346678613c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156247378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.4156247378
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1829154017
Short name T235
Test name
Test status
Simulation time 69288189708 ps
CPU time 255.45 seconds
Started May 05 02:56:19 PM PDT 24
Finished May 05 03:00:35 PM PDT 24
Peak memory 202712 kb
Host smart-c8409775-d89f-45e8-849e-09635fcc5917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829154017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1829154017
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1826014145
Short name T238
Test name
Test status
Simulation time 122252833293 ps
CPU time 679.75 seconds
Started May 05 02:56:41 PM PDT 24
Finished May 05 03:08:01 PM PDT 24
Peak memory 202640 kb
Host smart-8a491377-2faf-4624-9da3-fd58c1d70999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826014145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1826014145
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1160877670
Short name T201
Test name
Test status
Simulation time 14044063286 ps
CPU time 19.18 seconds
Started May 05 02:57:41 PM PDT 24
Finished May 05 02:58:00 PM PDT 24
Peak memory 210652 kb
Host smart-41412245-bf2c-419d-ba87-8ebb77d76f51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160877670 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1160877670
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.37473639
Short name T352
Test name
Test status
Simulation time 562369180542 ps
CPU time 1186.92 seconds
Started May 05 02:51:45 PM PDT 24
Finished May 05 03:11:33 PM PDT 24
Peak memory 202380 kb
Host smart-255929bb-2533-4532-8e71-01c392cf01e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37473639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.37473639
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.857269420
Short name T144
Test name
Test status
Simulation time 1241335230 ps
CPU time 5.07 seconds
Started May 05 02:38:10 PM PDT 24
Finished May 05 02:38:16 PM PDT 24
Peak memory 201400 kb
Host smart-f8729953-b933-459e-9003-e9f4272d3c0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857269420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.857269420
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2021138092
Short name T132
Test name
Test status
Simulation time 40226985852 ps
CPU time 88.91 seconds
Started May 05 02:38:24 PM PDT 24
Finished May 05 02:39:54 PM PDT 24
Peak memory 201516 kb
Host smart-89eceed7-5d83-46bb-854c-5a7438af6155
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021138092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2021138092
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.631161368
Short name T809
Test name
Test status
Simulation time 889521725 ps
CPU time 2.76 seconds
Started May 05 02:38:10 PM PDT 24
Finished May 05 02:38:13 PM PDT 24
Peak memory 201188 kb
Host smart-9109d053-b5d7-4262-b625-8d1b659e4914
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631161368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.631161368
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3420514414
Short name T820
Test name
Test status
Simulation time 365849886 ps
CPU time 1.7 seconds
Started May 05 02:38:24 PM PDT 24
Finished May 05 02:38:27 PM PDT 24
Peak memory 201308 kb
Host smart-96741658-ce41-4524-917c-f281dd777901
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420514414 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3420514414
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3075241582
Short name T138
Test name
Test status
Simulation time 494086869 ps
CPU time 1.89 seconds
Started May 05 02:38:10 PM PDT 24
Finished May 05 02:38:12 PM PDT 24
Peak memory 201240 kb
Host smart-bc6607e7-4173-4b97-a985-88d3e14d543f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075241582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3075241582
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1594208139
Short name T847
Test name
Test status
Simulation time 419300648 ps
CPU time 0.89 seconds
Started May 05 02:38:05 PM PDT 24
Finished May 05 02:38:06 PM PDT 24
Peak memory 201208 kb
Host smart-df43f33b-b338-4174-b09e-198256267348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594208139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1594208139
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1029670273
Short name T869
Test name
Test status
Simulation time 2298769942 ps
CPU time 3.38 seconds
Started May 05 02:38:11 PM PDT 24
Finished May 05 02:38:15 PM PDT 24
Peak memory 201280 kb
Host smart-346e104c-7a2c-4b12-8952-173d84b6bfec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029670273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1029670273
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.563292975
Short name T81
Test name
Test status
Simulation time 667593511 ps
CPU time 1.9 seconds
Started May 05 02:38:05 PM PDT 24
Finished May 05 02:38:08 PM PDT 24
Peak memory 201424 kb
Host smart-caba5489-461f-4a07-8f0a-93d9613e949a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563292975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.563292975
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4147294923
Short name T866
Test name
Test status
Simulation time 9460628152 ps
CPU time 11.48 seconds
Started May 05 02:38:04 PM PDT 24
Finished May 05 02:38:16 PM PDT 24
Peak memory 201552 kb
Host smart-12db0c13-630b-4d8c-98e1-10c7ec1516a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147294923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.4147294923
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2493688470
Short name T136
Test name
Test status
Simulation time 697457460 ps
CPU time 2.89 seconds
Started May 05 02:38:10 PM PDT 24
Finished May 05 02:38:13 PM PDT 24
Peak memory 201436 kb
Host smart-32028d9c-0569-47c1-b6bd-da0d6bbe6e1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493688470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2493688470
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2452287965
Short name T850
Test name
Test status
Simulation time 26581668953 ps
CPU time 36.96 seconds
Started May 05 02:38:09 PM PDT 24
Finished May 05 02:38:46 PM PDT 24
Peak memory 201448 kb
Host smart-7da0a8be-458f-4042-9447-d6ebc0811212
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452287965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2452287965
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3952144799
Short name T910
Test name
Test status
Simulation time 660043878 ps
CPU time 1.52 seconds
Started May 05 02:38:24 PM PDT 24
Finished May 05 02:38:27 PM PDT 24
Peak memory 201220 kb
Host smart-10b0151a-a6d1-47b8-a7d9-0bedeab528c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952144799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3952144799
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1158491362
Short name T855
Test name
Test status
Simulation time 415853106 ps
CPU time 2.22 seconds
Started May 05 02:38:13 PM PDT 24
Finished May 05 02:38:16 PM PDT 24
Peak memory 201288 kb
Host smart-0b41bd31-6b93-4226-8351-07bfd3378d9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158491362 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1158491362
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3769603414
Short name T894
Test name
Test status
Simulation time 342725322 ps
CPU time 1.66 seconds
Started May 05 02:38:10 PM PDT 24
Finished May 05 02:38:12 PM PDT 24
Peak memory 201224 kb
Host smart-01131dc6-10d0-45d7-b735-b904256180a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769603414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3769603414
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1790478856
Short name T853
Test name
Test status
Simulation time 355777250 ps
CPU time 1.03 seconds
Started May 05 02:38:09 PM PDT 24
Finished May 05 02:38:10 PM PDT 24
Peak memory 201172 kb
Host smart-7424d553-74eb-4bba-ad46-502523de9db7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790478856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1790478856
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2616203015
Short name T899
Test name
Test status
Simulation time 472834619 ps
CPU time 2.09 seconds
Started May 05 02:38:08 PM PDT 24
Finished May 05 02:38:11 PM PDT 24
Peak memory 217752 kb
Host smart-4ed59fac-df6c-4f7b-bf6f-5e0432f075a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616203015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2616203015
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1100807512
Short name T883
Test name
Test status
Simulation time 8594986687 ps
CPU time 6.79 seconds
Started May 05 02:38:24 PM PDT 24
Finished May 05 02:38:32 PM PDT 24
Peak memory 201444 kb
Host smart-8e478de7-4271-412b-b5f4-41c19d1a3fc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100807512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1100807512
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3219317309
Short name T835
Test name
Test status
Simulation time 405116192 ps
CPU time 1.3 seconds
Started May 05 02:38:31 PM PDT 24
Finished May 05 02:38:34 PM PDT 24
Peak memory 201264 kb
Host smart-03d8f073-1166-4fae-ba9d-a41b5d9fd065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219317309 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3219317309
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1529275594
Short name T919
Test name
Test status
Simulation time 465186247 ps
CPU time 1.92 seconds
Started May 05 02:38:30 PM PDT 24
Finished May 05 02:38:33 PM PDT 24
Peak memory 201228 kb
Host smart-5c5d04e4-9d41-4861-a5e0-7032c9f1828e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529275594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1529275594
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2549607894
Short name T827
Test name
Test status
Simulation time 323099154 ps
CPU time 0.99 seconds
Started May 05 02:38:29 PM PDT 24
Finished May 05 02:38:31 PM PDT 24
Peak memory 201232 kb
Host smart-05b17733-cc3c-4161-8ad1-b08a02db1252
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549607894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2549607894
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1231129323
Short name T849
Test name
Test status
Simulation time 4037960203 ps
CPU time 9.82 seconds
Started May 05 02:38:29 PM PDT 24
Finished May 05 02:38:40 PM PDT 24
Peak memory 201488 kb
Host smart-a92202d3-2e48-470f-b76f-852f525370c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231129323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1231129323
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2769989030
Short name T810
Test name
Test status
Simulation time 479781994 ps
CPU time 3.12 seconds
Started May 05 02:38:28 PM PDT 24
Finished May 05 02:38:32 PM PDT 24
Peak memory 201496 kb
Host smart-48e3ddc7-53f8-4946-8007-31f5ce6c3f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769989030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2769989030
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4135861986
Short name T905
Test name
Test status
Simulation time 8532258517 ps
CPU time 6.77 seconds
Started May 05 02:38:30 PM PDT 24
Finished May 05 02:38:38 PM PDT 24
Peak memory 201468 kb
Host smart-2f33a2d2-fd16-42c1-ac01-81fe34465c33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135861986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.4135861986
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2895097835
Short name T96
Test name
Test status
Simulation time 561637083 ps
CPU time 1.88 seconds
Started May 05 02:38:30 PM PDT 24
Finished May 05 02:38:33 PM PDT 24
Peak memory 201248 kb
Host smart-e8bb8d3d-ed69-40c6-b834-a3939461fa57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895097835 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2895097835
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1339544290
Short name T888
Test name
Test status
Simulation time 372584469 ps
CPU time 1.63 seconds
Started May 05 02:38:30 PM PDT 24
Finished May 05 02:38:32 PM PDT 24
Peak memory 201228 kb
Host smart-c9f2c148-5a87-4c4d-b7d6-c80e51ccee78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339544290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1339544290
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3976346307
Short name T848
Test name
Test status
Simulation time 414408156 ps
CPU time 1.03 seconds
Started May 05 02:38:30 PM PDT 24
Finished May 05 02:38:32 PM PDT 24
Peak memory 201232 kb
Host smart-f678d43a-1a7d-4865-aa68-cfe9d9173b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976346307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3976346307
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3027722485
Short name T139
Test name
Test status
Simulation time 3798416963 ps
CPU time 3.9 seconds
Started May 05 02:38:28 PM PDT 24
Finished May 05 02:38:32 PM PDT 24
Peak memory 201508 kb
Host smart-a98a8457-29ba-4843-9f51-7e58a0ee5a57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027722485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3027722485
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2533419718
Short name T874
Test name
Test status
Simulation time 626626850 ps
CPU time 2.27 seconds
Started May 05 02:38:27 PM PDT 24
Finished May 05 02:38:30 PM PDT 24
Peak memory 201488 kb
Host smart-7ca0f660-e3d7-4da8-98ee-ea52bdcb805b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533419718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2533419718
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2746695981
Short name T842
Test name
Test status
Simulation time 4105673384 ps
CPU time 11.58 seconds
Started May 05 02:38:29 PM PDT 24
Finished May 05 02:38:41 PM PDT 24
Peak memory 201460 kb
Host smart-89edb955-9c2b-414a-8209-e816a55cf203
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746695981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2746695981
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4119969131
Short name T859
Test name
Test status
Simulation time 618659248 ps
CPU time 1.26 seconds
Started May 05 02:38:28 PM PDT 24
Finished May 05 02:38:30 PM PDT 24
Peak memory 201196 kb
Host smart-baff6db1-3290-4a62-8c3a-8f0588b1d68f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119969131 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4119969131
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.238196153
Short name T852
Test name
Test status
Simulation time 374629573 ps
CPU time 1 seconds
Started May 05 02:38:30 PM PDT 24
Finished May 05 02:38:31 PM PDT 24
Peak memory 201204 kb
Host smart-80e9a380-76fc-495c-964e-6a5f1f9dd114
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238196153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.238196153
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.4056731275
Short name T890
Test name
Test status
Simulation time 381641306 ps
CPU time 1.43 seconds
Started May 05 02:38:28 PM PDT 24
Finished May 05 02:38:30 PM PDT 24
Peak memory 201140 kb
Host smart-f9f2644c-2a7d-4a47-9cd2-29883ba538aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056731275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.4056731275
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2117080207
Short name T142
Test name
Test status
Simulation time 4779882817 ps
CPU time 6.06 seconds
Started May 05 02:38:31 PM PDT 24
Finished May 05 02:38:37 PM PDT 24
Peak memory 201464 kb
Host smart-34ec4c3f-5bdd-4861-bee9-3bccba0a5bde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117080207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2117080207
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2799692170
Short name T843
Test name
Test status
Simulation time 427924778 ps
CPU time 2.77 seconds
Started May 05 02:38:30 PM PDT 24
Finished May 05 02:38:33 PM PDT 24
Peak memory 217772 kb
Host smart-477df794-78b4-4a88-b4e3-62e7cf068045
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799692170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2799692170
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1702864135
Short name T826
Test name
Test status
Simulation time 4199975385 ps
CPU time 6.44 seconds
Started May 05 02:38:31 PM PDT 24
Finished May 05 02:38:38 PM PDT 24
Peak memory 201536 kb
Host smart-c0f94b4c-fd59-45e7-b950-743c398f1277
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702864135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1702864135
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1272762023
Short name T804
Test name
Test status
Simulation time 319302752 ps
CPU time 1.6 seconds
Started May 05 02:38:34 PM PDT 24
Finished May 05 02:38:36 PM PDT 24
Peak memory 201248 kb
Host smart-f980c504-4bfd-44c1-8965-d8789acbd21d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272762023 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1272762023
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3089185938
Short name T912
Test name
Test status
Simulation time 436461268 ps
CPU time 1.21 seconds
Started May 05 02:38:35 PM PDT 24
Finished May 05 02:38:36 PM PDT 24
Peak memory 201220 kb
Host smart-8de38987-0b5a-4cda-bef8-7c3a748a42bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089185938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3089185938
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1830224753
Short name T900
Test name
Test status
Simulation time 340287564 ps
CPU time 0.83 seconds
Started May 05 02:38:37 PM PDT 24
Finished May 05 02:38:38 PM PDT 24
Peak memory 201220 kb
Host smart-24ce8e95-0b67-434e-8ef7-8879bc6f5d32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830224753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1830224753
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3676753971
Short name T143
Test name
Test status
Simulation time 5400838273 ps
CPU time 2.54 seconds
Started May 05 02:38:35 PM PDT 24
Finished May 05 02:38:38 PM PDT 24
Peak memory 201420 kb
Host smart-0f7f11a6-ce51-45a5-8b26-43c6b459d4a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676753971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3676753971
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.4004856136
Short name T884
Test name
Test status
Simulation time 535364430 ps
CPU time 2.83 seconds
Started May 05 02:38:30 PM PDT 24
Finished May 05 02:38:34 PM PDT 24
Peak memory 201496 kb
Host smart-f1c8a3ec-5254-4b39-b764-b6f07957611a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004856136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.4004856136
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2736844410
Short name T68
Test name
Test status
Simulation time 8004681328 ps
CPU time 20.33 seconds
Started May 05 02:38:35 PM PDT 24
Finished May 05 02:38:55 PM PDT 24
Peak memory 201432 kb
Host smart-cc6a8ce5-ba4e-4369-aae3-871e29e7d230
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736844410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2736844410
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.411290693
Short name T886
Test name
Test status
Simulation time 445606371 ps
CPU time 1.38 seconds
Started May 05 02:38:38 PM PDT 24
Finished May 05 02:38:40 PM PDT 24
Peak memory 201228 kb
Host smart-5de9fef0-bf6b-4dcc-9f0e-d09e727512ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411290693 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.411290693
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1546563822
Short name T130
Test name
Test status
Simulation time 386638015 ps
CPU time 1.68 seconds
Started May 05 02:38:38 PM PDT 24
Finished May 05 02:38:41 PM PDT 24
Peak memory 201156 kb
Host smart-9dcf62fb-9806-4f4c-a1fd-0968106c7263
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546563822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1546563822
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3916904525
Short name T812
Test name
Test status
Simulation time 564288867 ps
CPU time 0.93 seconds
Started May 05 02:38:39 PM PDT 24
Finished May 05 02:38:40 PM PDT 24
Peak memory 201196 kb
Host smart-493c769c-f720-4ed8-afb8-d5e3d36a65f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916904525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3916904525
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1093707978
Short name T140
Test name
Test status
Simulation time 2125334126 ps
CPU time 1.55 seconds
Started May 05 02:38:33 PM PDT 24
Finished May 05 02:38:35 PM PDT 24
Peak memory 201184 kb
Host smart-930121ea-a954-4323-9175-e432b01f2056
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093707978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1093707978
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3002208644
Short name T907
Test name
Test status
Simulation time 8237615895 ps
CPU time 11.18 seconds
Started May 05 02:38:38 PM PDT 24
Finished May 05 02:38:50 PM PDT 24
Peak memory 201496 kb
Host smart-08c1a622-3868-4b17-8d47-f2efbe1a455b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002208644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3002208644
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1151540163
Short name T74
Test name
Test status
Simulation time 512223325 ps
CPU time 1.37 seconds
Started May 05 02:38:33 PM PDT 24
Finished May 05 02:38:35 PM PDT 24
Peak memory 201240 kb
Host smart-dc6db431-3b69-4ff9-8296-53516fd643ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151540163 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1151540163
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.68034470
Short name T873
Test name
Test status
Simulation time 560311908 ps
CPU time 2.13 seconds
Started May 05 02:38:36 PM PDT 24
Finished May 05 02:38:39 PM PDT 24
Peak memory 201172 kb
Host smart-60ff2ead-e368-4420-9e91-dfe430845fd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68034470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.68034470
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.647281872
Short name T880
Test name
Test status
Simulation time 505133739 ps
CPU time 1.83 seconds
Started May 05 02:38:37 PM PDT 24
Finished May 05 02:38:40 PM PDT 24
Peak memory 201220 kb
Host smart-7fd71b6d-053d-44c4-bc6d-5e1b8f406186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647281872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.647281872
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1626341383
Short name T60
Test name
Test status
Simulation time 3707780724 ps
CPU time 8.6 seconds
Started May 05 02:38:36 PM PDT 24
Finished May 05 02:38:45 PM PDT 24
Peak memory 201468 kb
Host smart-c0d79cd7-fa0f-4b59-a5f1-87756556f484
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626341383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1626341383
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3825588588
Short name T871
Test name
Test status
Simulation time 492516735 ps
CPU time 1.34 seconds
Started May 05 02:38:38 PM PDT 24
Finished May 05 02:38:40 PM PDT 24
Peak memory 201280 kb
Host smart-51d141c9-12a0-4531-9a2c-ed90bc7b145d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825588588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3825588588
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2151740779
Short name T815
Test name
Test status
Simulation time 4111163657 ps
CPU time 11.05 seconds
Started May 05 02:38:38 PM PDT 24
Finished May 05 02:38:50 PM PDT 24
Peak memory 201492 kb
Host smart-cdd3ca52-cf65-440e-a32d-bdc13bafff4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151740779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2151740779
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3800183191
Short name T69
Test name
Test status
Simulation time 468152672 ps
CPU time 2.25 seconds
Started May 05 02:38:42 PM PDT 24
Finished May 05 02:38:45 PM PDT 24
Peak memory 201252 kb
Host smart-3b3a4549-dc71-49dc-b8b9-c69888401660
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800183191 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3800183191
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3425699365
Short name T134
Test name
Test status
Simulation time 407541190 ps
CPU time 0.92 seconds
Started May 05 02:38:38 PM PDT 24
Finished May 05 02:38:39 PM PDT 24
Peak memory 201228 kb
Host smart-b7a89c27-cd6c-4a09-b3b5-d36d0cfc383b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425699365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3425699365
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2235346782
Short name T911
Test name
Test status
Simulation time 428505156 ps
CPU time 1.48 seconds
Started May 05 02:38:34 PM PDT 24
Finished May 05 02:38:36 PM PDT 24
Peak memory 201236 kb
Host smart-2bb11074-69bd-4c94-9776-178edef3bebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235346782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2235346782
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4007813647
Short name T846
Test name
Test status
Simulation time 4821724282 ps
CPU time 6.99 seconds
Started May 05 02:38:39 PM PDT 24
Finished May 05 02:38:46 PM PDT 24
Peak memory 201520 kb
Host smart-609f11f6-ce57-4807-92e5-716096c90df7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007813647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.4007813647
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1011903987
Short name T70
Test name
Test status
Simulation time 631006765 ps
CPU time 2.19 seconds
Started May 05 02:38:37 PM PDT 24
Finished May 05 02:38:39 PM PDT 24
Peak memory 201468 kb
Host smart-a3530836-d2fe-4ff2-8772-861a6eb0aa47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011903987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1011903987
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.491807206
Short name T898
Test name
Test status
Simulation time 586696927 ps
CPU time 1.16 seconds
Started May 05 02:38:42 PM PDT 24
Finished May 05 02:38:43 PM PDT 24
Peak memory 201276 kb
Host smart-ea267ab1-c71d-4db7-ab17-e97cd193174d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491807206 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.491807206
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3546111861
Short name T129
Test name
Test status
Simulation time 345282131 ps
CPU time 0.88 seconds
Started May 05 02:38:43 PM PDT 24
Finished May 05 02:38:44 PM PDT 24
Peak memory 201156 kb
Host smart-97e40572-3ff4-4aa4-8ae1-ed8c301473d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546111861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3546111861
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.982744239
Short name T891
Test name
Test status
Simulation time 499430906 ps
CPU time 1.09 seconds
Started May 05 02:38:40 PM PDT 24
Finished May 05 02:38:42 PM PDT 24
Peak memory 201160 kb
Host smart-19f55e76-7ed6-40a6-a5b7-db4e0277f088
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982744239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.982744239
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1417732570
Short name T892
Test name
Test status
Simulation time 2353576912 ps
CPU time 4.52 seconds
Started May 05 02:38:45 PM PDT 24
Finished May 05 02:38:50 PM PDT 24
Peak memory 201256 kb
Host smart-bee3246e-e035-4c41-a4c3-22598b551fc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417732570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1417732570
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2588411223
Short name T79
Test name
Test status
Simulation time 663139244 ps
CPU time 3 seconds
Started May 05 02:38:39 PM PDT 24
Finished May 05 02:38:43 PM PDT 24
Peak memory 201548 kb
Host smart-206cbf67-da2e-4680-a986-62e9a9e0d484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588411223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2588411223
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.998805493
Short name T84
Test name
Test status
Simulation time 8443249992 ps
CPU time 14.38 seconds
Started May 05 02:38:40 PM PDT 24
Finished May 05 02:38:55 PM PDT 24
Peak memory 201504 kb
Host smart-2b72ebd7-56c1-493b-8b73-c92798e4e666
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998805493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.998805493
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.627896224
Short name T814
Test name
Test status
Simulation time 414641947 ps
CPU time 2.05 seconds
Started May 05 02:38:44 PM PDT 24
Finished May 05 02:38:46 PM PDT 24
Peak memory 201272 kb
Host smart-fdf8271d-bb95-40c2-a3d1-1202bf9b10d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627896224 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.627896224
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1102986273
Short name T885
Test name
Test status
Simulation time 546817160 ps
CPU time 1.12 seconds
Started May 05 02:38:38 PM PDT 24
Finished May 05 02:38:40 PM PDT 24
Peak memory 201212 kb
Host smart-2bc7ec85-099f-44d7-9f88-ef662f2f6ca3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102986273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1102986273
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3472923708
Short name T909
Test name
Test status
Simulation time 517699281 ps
CPU time 0.73 seconds
Started May 05 02:38:44 PM PDT 24
Finished May 05 02:38:45 PM PDT 24
Peak memory 201212 kb
Host smart-38c61a24-7f09-415c-9581-ac68b48aaa5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472923708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3472923708
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.344505039
Short name T844
Test name
Test status
Simulation time 5007978943 ps
CPU time 16.32 seconds
Started May 05 02:38:38 PM PDT 24
Finished May 05 02:38:55 PM PDT 24
Peak memory 201484 kb
Host smart-69c977d8-2ade-4f71-8569-15b5929e9734
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344505039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.344505039
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2303736053
Short name T839
Test name
Test status
Simulation time 635999286 ps
CPU time 1.62 seconds
Started May 05 02:38:43 PM PDT 24
Finished May 05 02:38:45 PM PDT 24
Peak memory 201520 kb
Host smart-3d1b76e6-2329-49d7-a03d-391e2d52b66a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303736053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2303736053
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2706724985
Short name T82
Test name
Test status
Simulation time 7990443431 ps
CPU time 6.55 seconds
Started May 05 02:38:38 PM PDT 24
Finished May 05 02:38:44 PM PDT 24
Peak memory 201480 kb
Host smart-83393e7b-b85f-4bb9-b303-1ff2e385a00d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706724985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2706724985
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2220290780
Short name T857
Test name
Test status
Simulation time 335804583 ps
CPU time 1.56 seconds
Started May 05 02:38:44 PM PDT 24
Finished May 05 02:38:46 PM PDT 24
Peak memory 201224 kb
Host smart-37898536-1ad2-4496-9c2d-3783b2cd746b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220290780 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2220290780
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3585241111
Short name T913
Test name
Test status
Simulation time 587864256 ps
CPU time 0.87 seconds
Started May 05 02:38:44 PM PDT 24
Finished May 05 02:38:46 PM PDT 24
Peak memory 201188 kb
Host smart-c35e38a3-540a-4a02-b49b-e893a407a9bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585241111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3585241111
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3810057813
Short name T864
Test name
Test status
Simulation time 318910910 ps
CPU time 1.18 seconds
Started May 05 02:38:43 PM PDT 24
Finished May 05 02:38:45 PM PDT 24
Peak memory 201152 kb
Host smart-031060e0-4302-49ee-b2aa-930cdeea15e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810057813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3810057813
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4217118094
Short name T882
Test name
Test status
Simulation time 5105169130 ps
CPU time 17.08 seconds
Started May 05 02:38:39 PM PDT 24
Finished May 05 02:38:57 PM PDT 24
Peak memory 201440 kb
Host smart-c1de09b5-15c4-4987-8996-f9bbbe9d8843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217118094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.4217118094
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3578931951
Short name T854
Test name
Test status
Simulation time 391958443 ps
CPU time 2.8 seconds
Started May 05 02:38:40 PM PDT 24
Finished May 05 02:38:44 PM PDT 24
Peak memory 201492 kb
Host smart-a7c5c461-c8a1-4604-a88f-9aaf831e532c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578931951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3578931951
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1291292418
Short name T830
Test name
Test status
Simulation time 4637430430 ps
CPU time 4.33 seconds
Started May 05 02:38:40 PM PDT 24
Finished May 05 02:38:45 PM PDT 24
Peak memory 201464 kb
Host smart-43713abf-8dcb-4776-a662-1cc783957373
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291292418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1291292418
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1861093997
Short name T145
Test name
Test status
Simulation time 1165078505 ps
CPU time 6.91 seconds
Started May 05 02:38:13 PM PDT 24
Finished May 05 02:38:21 PM PDT 24
Peak memory 201436 kb
Host smart-4636484d-c690-4759-9491-99da0372d5b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861093997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1861093997
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1161177632
Short name T62
Test name
Test status
Simulation time 11124505480 ps
CPU time 14.17 seconds
Started May 05 02:38:24 PM PDT 24
Finished May 05 02:38:39 PM PDT 24
Peak memory 201488 kb
Host smart-d65b1df8-c0e6-4be4-925b-fa8cb7e3e3af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161177632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1161177632
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2226068810
Short name T137
Test name
Test status
Simulation time 1278285867 ps
CPU time 1.51 seconds
Started May 05 02:38:12 PM PDT 24
Finished May 05 02:38:14 PM PDT 24
Peak memory 201216 kb
Host smart-7c8fbeed-f12f-4210-a13f-627f68fb4984
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226068810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2226068810
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3082794746
Short name T823
Test name
Test status
Simulation time 459907159 ps
CPU time 1.27 seconds
Started May 05 02:38:09 PM PDT 24
Finished May 05 02:38:11 PM PDT 24
Peak memory 201236 kb
Host smart-69eb1fa7-747f-4590-a79e-840133f7fa01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082794746 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3082794746
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2680065843
Short name T893
Test name
Test status
Simulation time 566710914 ps
CPU time 1.18 seconds
Started May 05 02:38:13 PM PDT 24
Finished May 05 02:38:15 PM PDT 24
Peak memory 201228 kb
Host smart-6a63af41-7d70-4c7d-98c1-5dc535d54b32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680065843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2680065843
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3054286137
Short name T870
Test name
Test status
Simulation time 367185405 ps
CPU time 0.83 seconds
Started May 05 02:38:09 PM PDT 24
Finished May 05 02:38:11 PM PDT 24
Peak memory 201156 kb
Host smart-349f47ca-1ffe-44ba-9b72-dfdb5518b9aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054286137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3054286137
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3331366299
Short name T838
Test name
Test status
Simulation time 4840740299 ps
CPU time 4.45 seconds
Started May 05 02:38:10 PM PDT 24
Finished May 05 02:38:15 PM PDT 24
Peak memory 201436 kb
Host smart-d396d3ce-9520-4713-a469-1ad0c2a77f1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331366299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3331366299
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2077160410
Short name T828
Test name
Test status
Simulation time 388142896 ps
CPU time 2.1 seconds
Started May 05 02:38:24 PM PDT 24
Finished May 05 02:38:27 PM PDT 24
Peak memory 201544 kb
Host smart-8fa8c8b0-6dc5-45ea-a613-d9106bd33340
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077160410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2077160410
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.879954235
Short name T66
Test name
Test status
Simulation time 4457834083 ps
CPU time 2.75 seconds
Started May 05 02:38:11 PM PDT 24
Finished May 05 02:38:15 PM PDT 24
Peak memory 201504 kb
Host smart-3c9b46fb-eb7d-4a71-aabb-4feb2b42fe52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879954235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.879954235
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3750615606
Short name T917
Test name
Test status
Simulation time 468330540 ps
CPU time 1.75 seconds
Started May 05 02:38:40 PM PDT 24
Finished May 05 02:38:42 PM PDT 24
Peak memory 201228 kb
Host smart-ca58bcad-6ece-46db-9a14-1776692e2982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750615606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3750615606
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.564213058
Short name T901
Test name
Test status
Simulation time 285637751 ps
CPU time 1.36 seconds
Started May 05 02:38:45 PM PDT 24
Finished May 05 02:38:47 PM PDT 24
Peak memory 201192 kb
Host smart-193b22dd-638f-4e39-a518-011f3efcd87f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564213058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.564213058
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2422929543
Short name T906
Test name
Test status
Simulation time 722175029 ps
CPU time 0.69 seconds
Started May 05 02:38:41 PM PDT 24
Finished May 05 02:38:43 PM PDT 24
Peak memory 201216 kb
Host smart-5138ce3c-8d63-4ac8-a8a8-a55ccff75b22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422929543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2422929543
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.225152906
Short name T800
Test name
Test status
Simulation time 351689819 ps
CPU time 0.71 seconds
Started May 05 02:38:41 PM PDT 24
Finished May 05 02:38:42 PM PDT 24
Peak memory 201140 kb
Host smart-280362f0-ee8d-42f4-9055-1563481bf961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225152906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.225152906
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3939440542
Short name T902
Test name
Test status
Simulation time 466200722 ps
CPU time 1.22 seconds
Started May 05 02:38:42 PM PDT 24
Finished May 05 02:38:44 PM PDT 24
Peak memory 201140 kb
Host smart-2ae195df-ae4c-49f3-ab65-4dae4a73b307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939440542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3939440542
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1654257710
Short name T802
Test name
Test status
Simulation time 450558972 ps
CPU time 0.88 seconds
Started May 05 02:38:40 PM PDT 24
Finished May 05 02:38:41 PM PDT 24
Peak memory 201180 kb
Host smart-eda53d75-ec90-40f7-93a7-9612e5ead94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654257710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1654257710
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2234792145
Short name T822
Test name
Test status
Simulation time 453033273 ps
CPU time 0.89 seconds
Started May 05 02:38:46 PM PDT 24
Finished May 05 02:38:47 PM PDT 24
Peak memory 201196 kb
Host smart-5bbc5581-adb2-4340-8ac9-b3925198b618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234792145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2234792145
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.383989923
Short name T836
Test name
Test status
Simulation time 300406961 ps
CPU time 0.96 seconds
Started May 05 02:38:45 PM PDT 24
Finished May 05 02:38:46 PM PDT 24
Peak memory 201172 kb
Host smart-e0977410-213c-4b7d-9b45-0e2590905104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383989923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.383989923
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3786717534
Short name T851
Test name
Test status
Simulation time 330795016 ps
CPU time 0.79 seconds
Started May 05 02:38:44 PM PDT 24
Finished May 05 02:38:45 PM PDT 24
Peak memory 201172 kb
Host smart-711145cb-6d90-46e4-acd7-60f6d49f24b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786717534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3786717534
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1398174470
Short name T818
Test name
Test status
Simulation time 342077405 ps
CPU time 1.36 seconds
Started May 05 02:38:44 PM PDT 24
Finished May 05 02:38:46 PM PDT 24
Peak memory 201188 kb
Host smart-2a28d210-e8f5-460f-bc43-d0001b13b61a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398174470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1398174470
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2589862522
Short name T128
Test name
Test status
Simulation time 561566985 ps
CPU time 2.55 seconds
Started May 05 02:38:12 PM PDT 24
Finished May 05 02:38:15 PM PDT 24
Peak memory 201448 kb
Host smart-a187c5dd-7e19-4b2f-8587-025aa8a0f3de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589862522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2589862522
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3292745291
Short name T825
Test name
Test status
Simulation time 27132324115 ps
CPU time 58.29 seconds
Started May 05 02:38:18 PM PDT 24
Finished May 05 02:39:17 PM PDT 24
Peak memory 201472 kb
Host smart-f374bc39-f1e8-4f71-a25d-b09d749748d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292745291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3292745291
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1843018889
Short name T135
Test name
Test status
Simulation time 1233695976 ps
CPU time 3.84 seconds
Started May 05 02:38:13 PM PDT 24
Finished May 05 02:38:18 PM PDT 24
Peak memory 201196 kb
Host smart-6d280eb9-408d-416f-bc70-fbf37e270755
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843018889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1843018889
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3252658717
Short name T916
Test name
Test status
Simulation time 766545533 ps
CPU time 1.15 seconds
Started May 05 02:38:13 PM PDT 24
Finished May 05 02:38:15 PM PDT 24
Peak memory 201292 kb
Host smart-9da178ad-a9f8-4365-ada7-4671f6f2b844
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252658717 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3252658717
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.305656133
Short name T877
Test name
Test status
Simulation time 360175987 ps
CPU time 1.59 seconds
Started May 05 02:38:14 PM PDT 24
Finished May 05 02:38:16 PM PDT 24
Peak memory 201216 kb
Host smart-f7e96e67-95a4-4e8e-b892-ae250791aa46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305656133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.305656133
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3427729900
Short name T895
Test name
Test status
Simulation time 318734002 ps
CPU time 1.02 seconds
Started May 05 02:38:24 PM PDT 24
Finished May 05 02:38:26 PM PDT 24
Peak memory 201244 kb
Host smart-b0091381-b3de-4561-b61f-644d76463ab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427729900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3427729900
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2762706242
Short name T35
Test name
Test status
Simulation time 2491344411 ps
CPU time 2.46 seconds
Started May 05 02:38:16 PM PDT 24
Finished May 05 02:38:18 PM PDT 24
Peak memory 201296 kb
Host smart-58a286b8-8904-4732-9756-c9a7f9a76560
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762706242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2762706242
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2336920760
Short name T858
Test name
Test status
Simulation time 720186408 ps
CPU time 3.6 seconds
Started May 05 02:38:24 PM PDT 24
Finished May 05 02:38:29 PM PDT 24
Peak memory 217540 kb
Host smart-0b0c443f-dfad-402e-ae88-e238e9a5890b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336920760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2336920760
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.368036750
Short name T856
Test name
Test status
Simulation time 4364553613 ps
CPU time 12.18 seconds
Started May 05 02:38:11 PM PDT 24
Finished May 05 02:38:23 PM PDT 24
Peak memory 201500 kb
Host smart-86c4594f-4789-44c9-ae91-d9e6fa9a81da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368036750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.368036750
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2336294882
Short name T799
Test name
Test status
Simulation time 368982772 ps
CPU time 0.84 seconds
Started May 05 02:38:45 PM PDT 24
Finished May 05 02:38:47 PM PDT 24
Peak memory 201228 kb
Host smart-54d59064-4c3a-4104-8bdf-0b780281792b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336294882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2336294882
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2699751111
Short name T862
Test name
Test status
Simulation time 467733469 ps
CPU time 1.13 seconds
Started May 05 02:38:50 PM PDT 24
Finished May 05 02:38:52 PM PDT 24
Peak memory 201184 kb
Host smart-369c6bd1-cafc-4799-afeb-8978d3c95d87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699751111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2699751111
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2527557558
Short name T824
Test name
Test status
Simulation time 409297849 ps
CPU time 1.56 seconds
Started May 05 02:38:45 PM PDT 24
Finished May 05 02:38:47 PM PDT 24
Peak memory 201176 kb
Host smart-e06eea25-f80f-4083-adac-cc87c671d419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527557558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2527557558
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.403883781
Short name T868
Test name
Test status
Simulation time 313763076 ps
CPU time 1.35 seconds
Started May 05 02:38:44 PM PDT 24
Finished May 05 02:38:46 PM PDT 24
Peak memory 201196 kb
Host smart-adc3eb16-003a-46a7-bf30-be42048af37b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403883781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.403883781
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2994094109
Short name T808
Test name
Test status
Simulation time 513578603 ps
CPU time 1.92 seconds
Started May 05 02:38:46 PM PDT 24
Finished May 05 02:38:48 PM PDT 24
Peak memory 201204 kb
Host smart-f7937d8b-cc72-4f8f-b45e-10c9ed9799e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994094109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2994094109
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3644128592
Short name T863
Test name
Test status
Simulation time 293098424 ps
CPU time 1.33 seconds
Started May 05 02:38:46 PM PDT 24
Finished May 05 02:38:48 PM PDT 24
Peak memory 201208 kb
Host smart-b7aca1c6-5516-45de-95e7-1641aadcd004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644128592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3644128592
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.663106024
Short name T872
Test name
Test status
Simulation time 400497610 ps
CPU time 1.5 seconds
Started May 05 02:38:50 PM PDT 24
Finished May 05 02:38:52 PM PDT 24
Peak memory 201188 kb
Host smart-9d90c1b6-b58b-4bd0-aee0-1e4a43de7919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663106024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.663106024
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1781143927
Short name T903
Test name
Test status
Simulation time 385199502 ps
CPU time 1.05 seconds
Started May 05 02:38:49 PM PDT 24
Finished May 05 02:38:50 PM PDT 24
Peak memory 201196 kb
Host smart-c491029b-4291-43fa-a6f1-f2dbccb4b922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781143927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1781143927
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1106427297
Short name T811
Test name
Test status
Simulation time 448997772 ps
CPU time 0.77 seconds
Started May 05 02:38:45 PM PDT 24
Finished May 05 02:38:46 PM PDT 24
Peak memory 201184 kb
Host smart-14be44d2-613d-4905-97b3-b333c90177ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106427297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1106427297
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.306365798
Short name T806
Test name
Test status
Simulation time 504086976 ps
CPU time 1.42 seconds
Started May 05 02:38:45 PM PDT 24
Finished May 05 02:38:47 PM PDT 24
Peak memory 201228 kb
Host smart-ce5888b3-736e-45e1-a1ef-4e458cfa54d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306365798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.306365798
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1348115363
Short name T896
Test name
Test status
Simulation time 757670378 ps
CPU time 2.45 seconds
Started May 05 02:38:14 PM PDT 24
Finished May 05 02:38:17 PM PDT 24
Peak memory 201400 kb
Host smart-68a8c929-9662-4f90-94ce-2b8860ef4707
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348115363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1348115363
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3636422920
Short name T133
Test name
Test status
Simulation time 38440093156 ps
CPU time 151.85 seconds
Started May 05 02:38:15 PM PDT 24
Finished May 05 02:40:47 PM PDT 24
Peak memory 201524 kb
Host smart-3fead6a5-1dd1-4bd4-94aa-96cf899b3242
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636422920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3636422920
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.676595265
Short name T131
Test name
Test status
Simulation time 1239773172 ps
CPU time 2.03 seconds
Started May 05 02:38:12 PM PDT 24
Finished May 05 02:38:15 PM PDT 24
Peak memory 201204 kb
Host smart-ea638a55-d0f5-4bf4-8e10-7eafc97e1565
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676595265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.676595265
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3282542101
Short name T841
Test name
Test status
Simulation time 590710059 ps
CPU time 0.94 seconds
Started May 05 02:38:12 PM PDT 24
Finished May 05 02:38:13 PM PDT 24
Peak memory 201344 kb
Host smart-33a80d0a-0d2a-4fb0-82dc-9ef01c738be4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282542101 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3282542101
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.337859800
Short name T889
Test name
Test status
Simulation time 493347660 ps
CPU time 1.83 seconds
Started May 05 02:38:13 PM PDT 24
Finished May 05 02:38:15 PM PDT 24
Peak memory 201228 kb
Host smart-6e8045f9-55cb-4bea-8d81-bed5450fa2b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337859800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.337859800
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1520612016
Short name T861
Test name
Test status
Simulation time 345655068 ps
CPU time 1.04 seconds
Started May 05 02:38:13 PM PDT 24
Finished May 05 02:38:14 PM PDT 24
Peak memory 201220 kb
Host smart-25184944-34a7-487b-896f-b967435b34fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520612016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1520612016
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.376099013
Short name T834
Test name
Test status
Simulation time 2429953196 ps
CPU time 2.34 seconds
Started May 05 02:38:14 PM PDT 24
Finished May 05 02:38:17 PM PDT 24
Peak memory 201272 kb
Host smart-a4fd4950-9874-4442-ab41-a50e6a8b8b38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376099013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.376099013
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.818916322
Short name T865
Test name
Test status
Simulation time 425612769 ps
CPU time 1.83 seconds
Started May 05 02:38:15 PM PDT 24
Finished May 05 02:38:17 PM PDT 24
Peak memory 201492 kb
Host smart-97df948f-d837-4e97-9a43-adb495a39eaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818916322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.818916322
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1833149155
Short name T904
Test name
Test status
Simulation time 8088431297 ps
CPU time 6.16 seconds
Started May 05 02:38:15 PM PDT 24
Finished May 05 02:38:21 PM PDT 24
Peak memory 201480 kb
Host smart-fe4b58ef-b83b-4dcd-9937-a1dca8db2564
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833149155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1833149155
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1929348624
Short name T816
Test name
Test status
Simulation time 552537637 ps
CPU time 0.96 seconds
Started May 05 02:38:46 PM PDT 24
Finished May 05 02:38:48 PM PDT 24
Peak memory 201220 kb
Host smart-22e34d22-4ddf-4dfe-b501-95b4bf2f3f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929348624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1929348624
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1643479864
Short name T887
Test name
Test status
Simulation time 465880526 ps
CPU time 1.23 seconds
Started May 05 02:38:50 PM PDT 24
Finished May 05 02:38:52 PM PDT 24
Peak memory 201224 kb
Host smart-32d8bcbb-9576-45d4-8e85-14da4776d743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643479864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1643479864
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2277765088
Short name T914
Test name
Test status
Simulation time 336525638 ps
CPU time 0.77 seconds
Started May 05 02:38:49 PM PDT 24
Finished May 05 02:38:50 PM PDT 24
Peak memory 201216 kb
Host smart-4b3b6a70-8ded-4281-98a6-0251be3db6e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277765088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2277765088
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.815466940
Short name T837
Test name
Test status
Simulation time 492294496 ps
CPU time 1.25 seconds
Started May 05 02:38:49 PM PDT 24
Finished May 05 02:38:51 PM PDT 24
Peak memory 201224 kb
Host smart-40698388-78e1-435c-809c-2c203e00528a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815466940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.815466940
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4084448788
Short name T831
Test name
Test status
Simulation time 374226890 ps
CPU time 0.86 seconds
Started May 05 02:38:50 PM PDT 24
Finished May 05 02:38:51 PM PDT 24
Peak memory 201160 kb
Host smart-a4afc686-7fca-456b-8fdf-5faca735638f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084448788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.4084448788
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1384790299
Short name T807
Test name
Test status
Simulation time 488463704 ps
CPU time 0.67 seconds
Started May 05 02:38:51 PM PDT 24
Finished May 05 02:38:52 PM PDT 24
Peak memory 201232 kb
Host smart-59d09f9e-a448-40bf-b38d-a107050e2416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384790299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1384790299
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3119463309
Short name T805
Test name
Test status
Simulation time 316529949 ps
CPU time 1.27 seconds
Started May 05 02:38:50 PM PDT 24
Finished May 05 02:38:52 PM PDT 24
Peak memory 201224 kb
Host smart-d6477865-9527-4c9d-8e96-15825145046d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119463309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3119463309
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.746840075
Short name T918
Test name
Test status
Simulation time 304872187 ps
CPU time 0.98 seconds
Started May 05 02:38:50 PM PDT 24
Finished May 05 02:38:51 PM PDT 24
Peak memory 201216 kb
Host smart-9e70466b-4aed-4e20-ab8d-9d2353543bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746840075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.746840075
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2832734057
Short name T879
Test name
Test status
Simulation time 338744554 ps
CPU time 1.4 seconds
Started May 05 02:38:52 PM PDT 24
Finished May 05 02:38:54 PM PDT 24
Peak memory 201204 kb
Host smart-cbf87f43-4662-4c83-a42d-aea1e196a836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832734057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2832734057
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1360223675
Short name T829
Test name
Test status
Simulation time 296046234 ps
CPU time 1.01 seconds
Started May 05 02:38:49 PM PDT 24
Finished May 05 02:38:51 PM PDT 24
Peak memory 201180 kb
Host smart-ef8abc17-2568-4bc6-93c1-1eae85486a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360223675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1360223675
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1133732539
Short name T803
Test name
Test status
Simulation time 493608889 ps
CPU time 2.17 seconds
Started May 05 02:38:18 PM PDT 24
Finished May 05 02:38:20 PM PDT 24
Peak memory 201284 kb
Host smart-f6d11a2c-8a8d-47c5-b86d-535ab089757e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133732539 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1133732539
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2396614940
Short name T817
Test name
Test status
Simulation time 443417036 ps
CPU time 1.72 seconds
Started May 05 02:38:18 PM PDT 24
Finished May 05 02:38:21 PM PDT 24
Peak memory 201184 kb
Host smart-f43113b6-59af-490e-8e25-459a5dc3f9b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396614940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2396614940
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1656825565
Short name T798
Test name
Test status
Simulation time 329030313 ps
CPU time 0.81 seconds
Started May 05 02:38:18 PM PDT 24
Finished May 05 02:38:20 PM PDT 24
Peak memory 201172 kb
Host smart-f654d967-d4fd-4eab-898d-6f72f1ca704a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656825565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1656825565
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2513450992
Short name T875
Test name
Test status
Simulation time 4301471054 ps
CPU time 14.82 seconds
Started May 05 02:38:20 PM PDT 24
Finished May 05 02:38:35 PM PDT 24
Peak memory 201472 kb
Host smart-80bc9b73-d3d9-467b-9124-9caf403104bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513450992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2513450992
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1543489945
Short name T80
Test name
Test status
Simulation time 410640824 ps
CPU time 3.45 seconds
Started May 05 02:38:13 PM PDT 24
Finished May 05 02:38:17 PM PDT 24
Peak memory 217684 kb
Host smart-7096726f-c057-462f-ab2a-4454382266cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543489945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1543489945
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1904572608
Short name T369
Test name
Test status
Simulation time 8895537872 ps
CPU time 4.96 seconds
Started May 05 02:38:18 PM PDT 24
Finished May 05 02:38:24 PM PDT 24
Peak memory 201388 kb
Host smart-8b13fb76-6f59-43de-a933-beb24bc60d55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904572608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1904572608
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2213578723
Short name T801
Test name
Test status
Simulation time 491731352 ps
CPU time 2.02 seconds
Started May 05 02:38:18 PM PDT 24
Finished May 05 02:38:21 PM PDT 24
Peak memory 201284 kb
Host smart-ed79e81d-d696-4eed-8640-c907e4af137d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213578723 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2213578723
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3810836801
Short name T141
Test name
Test status
Simulation time 563697966 ps
CPU time 1.95 seconds
Started May 05 02:38:18 PM PDT 24
Finished May 05 02:38:21 PM PDT 24
Peak memory 201204 kb
Host smart-b852ea81-5198-450d-82a4-126938197959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810836801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3810836801
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4139268900
Short name T915
Test name
Test status
Simulation time 498337477 ps
CPU time 0.8 seconds
Started May 05 02:38:18 PM PDT 24
Finished May 05 02:38:19 PM PDT 24
Peak memory 201160 kb
Host smart-e49f4772-e1c2-4f12-859e-a71a48fb95e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139268900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.4139268900
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3818947928
Short name T876
Test name
Test status
Simulation time 4185324448 ps
CPU time 4.37 seconds
Started May 05 02:38:19 PM PDT 24
Finished May 05 02:38:24 PM PDT 24
Peak memory 201504 kb
Host smart-cdfb5ffe-53d5-462f-be13-64e9e623d3b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818947928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3818947928
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1233850693
Short name T819
Test name
Test status
Simulation time 850184363 ps
CPU time 3.15 seconds
Started May 05 02:38:19 PM PDT 24
Finished May 05 02:38:23 PM PDT 24
Peak memory 210704 kb
Host smart-ca149a23-09d4-41ec-86c5-1bca75c59cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233850693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1233850693
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3224206535
Short name T821
Test name
Test status
Simulation time 4115227002 ps
CPU time 10.9 seconds
Started May 05 02:38:19 PM PDT 24
Finished May 05 02:38:30 PM PDT 24
Peak memory 201476 kb
Host smart-5d2c813b-3dc3-435a-9aff-ded1def3f544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224206535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3224206535
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2756463975
Short name T98
Test name
Test status
Simulation time 435561845 ps
CPU time 2.01 seconds
Started May 05 02:38:31 PM PDT 24
Finished May 05 02:38:33 PM PDT 24
Peak memory 201288 kb
Host smart-416b92b1-35e6-4dd7-91be-40ff7ccbaa26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756463975 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2756463975
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3808183827
Short name T881
Test name
Test status
Simulation time 320372729 ps
CPU time 0.93 seconds
Started May 05 02:38:26 PM PDT 24
Finished May 05 02:38:28 PM PDT 24
Peak memory 201228 kb
Host smart-3c32a549-bd7c-4c9d-859b-dfe08ae6db85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808183827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3808183827
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2884106492
Short name T860
Test name
Test status
Simulation time 337578499 ps
CPU time 0.79 seconds
Started May 05 02:38:30 PM PDT 24
Finished May 05 02:38:32 PM PDT 24
Peak memory 201228 kb
Host smart-cd835e9e-ad1d-4bf5-8bdf-80aa6c89695a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884106492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2884106492
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2725865067
Short name T867
Test name
Test status
Simulation time 1698467693 ps
CPU time 4.14 seconds
Started May 05 02:38:26 PM PDT 24
Finished May 05 02:38:30 PM PDT 24
Peak memory 201232 kb
Host smart-204bc098-b159-4b70-88e0-44dbc405ba79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725865067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2725865067
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.573796779
Short name T75
Test name
Test status
Simulation time 476619267 ps
CPU time 1.92 seconds
Started May 05 02:38:19 PM PDT 24
Finished May 05 02:38:21 PM PDT 24
Peak memory 201492 kb
Host smart-b61c70ad-65a8-4243-b204-173b1b939965
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573796779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.573796779
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1341367459
Short name T368
Test name
Test status
Simulation time 8466506346 ps
CPU time 7.79 seconds
Started May 05 02:38:21 PM PDT 24
Finished May 05 02:38:29 PM PDT 24
Peak memory 201496 kb
Host smart-e80bc1e8-5a35-4c9e-bd89-317e8f9c7754
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341367459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1341367459
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2077135801
Short name T97
Test name
Test status
Simulation time 632927505 ps
CPU time 1.09 seconds
Started May 05 02:38:30 PM PDT 24
Finished May 05 02:38:32 PM PDT 24
Peak memory 201260 kb
Host smart-e8c2c2b2-5fc1-4b8a-973a-baf7d50f0d26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077135801 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2077135801
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.746833818
Short name T832
Test name
Test status
Simulation time 452751610 ps
CPU time 0.83 seconds
Started May 05 02:38:24 PM PDT 24
Finished May 05 02:38:26 PM PDT 24
Peak memory 201204 kb
Host smart-52f56992-6f9a-4546-9498-627d74684dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746833818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.746833818
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4118353989
Short name T813
Test name
Test status
Simulation time 2169430892 ps
CPU time 4.34 seconds
Started May 05 02:38:23 PM PDT 24
Finished May 05 02:38:27 PM PDT 24
Peak memory 201288 kb
Host smart-4d2204c6-cec5-4eb3-a2a8-07086179ec02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118353989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.4118353989
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2091616762
Short name T845
Test name
Test status
Simulation time 647377775 ps
CPU time 2.28 seconds
Started May 05 02:38:24 PM PDT 24
Finished May 05 02:38:27 PM PDT 24
Peak memory 217720 kb
Host smart-24637fde-707d-4516-9b1c-c41f85277242
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091616762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2091616762
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2392649494
Short name T67
Test name
Test status
Simulation time 9410359343 ps
CPU time 4.63 seconds
Started May 05 02:38:23 PM PDT 24
Finished May 05 02:38:28 PM PDT 24
Peak memory 201500 kb
Host smart-6a77da69-a122-47c7-a94f-d214a7e5dc52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392649494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2392649494
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2878498551
Short name T908
Test name
Test status
Simulation time 491988396 ps
CPU time 1.06 seconds
Started May 05 02:38:24 PM PDT 24
Finished May 05 02:38:26 PM PDT 24
Peak memory 201268 kb
Host smart-fab1a055-84f0-49ba-a6b9-1cb022c794e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878498551 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2878498551
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2107092241
Short name T878
Test name
Test status
Simulation time 477588503 ps
CPU time 2.05 seconds
Started May 05 02:38:26 PM PDT 24
Finished May 05 02:38:29 PM PDT 24
Peak memory 201228 kb
Host smart-f439d9e3-864b-4451-840d-b89f0f1c49bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107092241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2107092241
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4176111685
Short name T897
Test name
Test status
Simulation time 393784862 ps
CPU time 0.87 seconds
Started May 05 02:38:26 PM PDT 24
Finished May 05 02:38:28 PM PDT 24
Peak memory 201224 kb
Host smart-91a14732-29ef-410f-a942-edd3ccb4d03b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176111685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4176111685
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1815724390
Short name T840
Test name
Test status
Simulation time 2712708960 ps
CPU time 3.35 seconds
Started May 05 02:38:22 PM PDT 24
Finished May 05 02:38:26 PM PDT 24
Peak memory 201256 kb
Host smart-68e2aa0f-7b31-40c9-bced-012b54b255cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815724390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1815724390
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1186284236
Short name T833
Test name
Test status
Simulation time 502555355 ps
CPU time 2.77 seconds
Started May 05 02:38:26 PM PDT 24
Finished May 05 02:38:29 PM PDT 24
Peak memory 201496 kb
Host smart-4b568772-c0df-4ca6-8c9f-10ddd0f2c98d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186284236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1186284236
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1999701602
Short name T370
Test name
Test status
Simulation time 4253391196 ps
CPU time 11.16 seconds
Started May 05 02:38:22 PM PDT 24
Finished May 05 02:38:34 PM PDT 24
Peak memory 201460 kb
Host smart-4b6e68df-e83e-4484-b946-5fdb4b21796b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999701602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1999701602
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2013620101
Short name T595
Test name
Test status
Simulation time 361293319 ps
CPU time 1.41 seconds
Started May 05 02:51:14 PM PDT 24
Finished May 05 02:51:16 PM PDT 24
Peak memory 202012 kb
Host smart-cc5ac5e3-6680-40ce-9cf4-e531c8538341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013620101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2013620101
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1073384325
Short name T353
Test name
Test status
Simulation time 336629551365 ps
CPU time 221.24 seconds
Started May 05 02:51:15 PM PDT 24
Finished May 05 02:54:57 PM PDT 24
Peak memory 202284 kb
Host smart-dea3294d-b975-423f-8aa1-86ab61b5db21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073384325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1073384325
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1731059796
Short name T772
Test name
Test status
Simulation time 325778652741 ps
CPU time 203 seconds
Started May 05 02:51:13 PM PDT 24
Finished May 05 02:54:36 PM PDT 24
Peak memory 202384 kb
Host smart-51e2cb41-b2bd-40e6-9932-16e86b4fd9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731059796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1731059796
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.166283995
Short name T560
Test name
Test status
Simulation time 167447811395 ps
CPU time 344.71 seconds
Started May 05 02:51:15 PM PDT 24
Finished May 05 02:57:00 PM PDT 24
Peak memory 202292 kb
Host smart-d895b402-7df8-4850-ba4d-7ad72e8db47d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=166283995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.166283995
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3345129696
Short name T196
Test name
Test status
Simulation time 163165408926 ps
CPU time 104.43 seconds
Started May 05 02:51:14 PM PDT 24
Finished May 05 02:52:59 PM PDT 24
Peak memory 202340 kb
Host smart-0fda50cf-6659-480b-894d-9b148c36b890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345129696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3345129696
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.543100464
Short name T388
Test name
Test status
Simulation time 160797918723 ps
CPU time 360.42 seconds
Started May 05 02:51:15 PM PDT 24
Finished May 05 02:57:16 PM PDT 24
Peak memory 202304 kb
Host smart-efea9f80-0dbe-400b-9d5f-e4177a0eec8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=543100464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.543100464
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.568414687
Short name T422
Test name
Test status
Simulation time 616247882233 ps
CPU time 653.68 seconds
Started May 05 02:51:12 PM PDT 24
Finished May 05 03:02:06 PM PDT 24
Peak memory 202368 kb
Host smart-3cd96d1e-e725-4eb4-b67c-dbc2d3c1209d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568414687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.568414687
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.142054723
Short name T231
Test name
Test status
Simulation time 133586726437 ps
CPU time 701.4 seconds
Started May 05 02:51:14 PM PDT 24
Finished May 05 03:02:57 PM PDT 24
Peak memory 202752 kb
Host smart-e394df44-bb8c-4b35-b3ed-a520a1f48dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142054723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.142054723
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3377507736
Short name T697
Test name
Test status
Simulation time 42948448353 ps
CPU time 87.62 seconds
Started May 05 02:51:14 PM PDT 24
Finished May 05 02:52:42 PM PDT 24
Peak memory 202076 kb
Host smart-cab7d702-5f92-4154-8bc9-505a71f3952f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377507736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3377507736
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.906135757
Short name T603
Test name
Test status
Simulation time 4116362916 ps
CPU time 10.06 seconds
Started May 05 02:51:15 PM PDT 24
Finished May 05 02:51:26 PM PDT 24
Peak memory 202116 kb
Host smart-8fffe43d-1cda-4726-85c8-02d48cf52bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906135757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.906135757
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3126911014
Short name T73
Test name
Test status
Simulation time 3965937192 ps
CPU time 5.27 seconds
Started May 05 02:51:14 PM PDT 24
Finished May 05 02:51:20 PM PDT 24
Peak memory 217800 kb
Host smart-07e1ef7b-0f75-4813-89a3-5b5726c7399b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126911014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3126911014
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1483731881
Short name T451
Test name
Test status
Simulation time 5782483538 ps
CPU time 6.8 seconds
Started May 05 02:51:13 PM PDT 24
Finished May 05 02:51:20 PM PDT 24
Peak memory 202140 kb
Host smart-57cc9cc8-6a82-4059-aea3-2cec332f5780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483731881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1483731881
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3556846287
Short name T521
Test name
Test status
Simulation time 42001463428 ps
CPU time 60.02 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 02:52:19 PM PDT 24
Peak memory 202300 kb
Host smart-ebd8e359-0a39-49e3-a813-dcde316cc1ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556846287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3556846287
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4107463242
Short name T759
Test name
Test status
Simulation time 60500204019 ps
CPU time 69.87 seconds
Started May 05 02:51:17 PM PDT 24
Finished May 05 02:52:27 PM PDT 24
Peak memory 210616 kb
Host smart-49310ecb-36b9-4689-9cd2-480317d0d2ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107463242 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.4107463242
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2382205301
Short name T546
Test name
Test status
Simulation time 435848455 ps
CPU time 0.85 seconds
Started May 05 02:51:17 PM PDT 24
Finished May 05 02:51:18 PM PDT 24
Peak memory 201952 kb
Host smart-50725b25-585a-4cfc-9c8f-a46ae1f17488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382205301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2382205301
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1906544
Short name T290
Test name
Test status
Simulation time 175411584796 ps
CPU time 96.17 seconds
Started May 05 02:51:16 PM PDT 24
Finished May 05 02:52:52 PM PDT 24
Peak memory 202268 kb
Host smart-a6b11557-05bd-4127-ac14-6feb57d3435d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gat
ing_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating.1906544
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2233173974
Short name T611
Test name
Test status
Simulation time 513046853988 ps
CPU time 1173.96 seconds
Started May 05 02:51:15 PM PDT 24
Finished May 05 03:10:49 PM PDT 24
Peak memory 202280 kb
Host smart-37879733-4e83-473e-afd4-b1d1e4be4a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233173974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2233173974
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1647054525
Short name T717
Test name
Test status
Simulation time 169457575621 ps
CPU time 395.02 seconds
Started May 05 02:51:13 PM PDT 24
Finished May 05 02:57:49 PM PDT 24
Peak memory 202376 kb
Host smart-d990d74e-60ba-4ede-8ffa-3e3fd77ed5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647054525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1647054525
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3719187948
Short name T654
Test name
Test status
Simulation time 488922962124 ps
CPU time 1141.5 seconds
Started May 05 02:51:14 PM PDT 24
Finished May 05 03:10:17 PM PDT 24
Peak memory 202388 kb
Host smart-097b10a0-4967-4a0a-8793-04cb48e73a6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719187948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3719187948
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3021566546
Short name T519
Test name
Test status
Simulation time 172526866242 ps
CPU time 360.75 seconds
Started May 05 02:51:13 PM PDT 24
Finished May 05 02:57:14 PM PDT 24
Peak memory 202308 kb
Host smart-535f65b1-acec-4475-baaa-f6faa31276cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021566546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3021566546
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.147250624
Short name T431
Test name
Test status
Simulation time 484571716079 ps
CPU time 1068.7 seconds
Started May 05 02:51:14 PM PDT 24
Finished May 05 03:09:03 PM PDT 24
Peak memory 202292 kb
Host smart-885af5c7-0cc6-4364-95a7-247567bc1bfd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=147250624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.147250624
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.55874413
Short name T172
Test name
Test status
Simulation time 598897536460 ps
CPU time 272.52 seconds
Started May 05 02:51:15 PM PDT 24
Finished May 05 02:55:48 PM PDT 24
Peak memory 202344 kb
Host smart-8af4267c-4879-4bf7-94b1-933689020f55
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55874413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ad
c_ctrl_filters_wakeup_fixed.55874413
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2087967964
Short name T55
Test name
Test status
Simulation time 111372701727 ps
CPU time 424.89 seconds
Started May 05 02:51:14 PM PDT 24
Finished May 05 02:58:19 PM PDT 24
Peak memory 202680 kb
Host smart-83f9b5c0-c147-4223-9aeb-c929e7787d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087967964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2087967964
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1704178574
Short name T702
Test name
Test status
Simulation time 31671933674 ps
CPU time 19.55 seconds
Started May 05 02:51:14 PM PDT 24
Finished May 05 02:51:34 PM PDT 24
Peak memory 202100 kb
Host smart-536caa3c-2295-4d23-8a8e-e34c96ac3cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704178574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1704178574
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1166759588
Short name T712
Test name
Test status
Simulation time 3157414842 ps
CPU time 7.91 seconds
Started May 05 02:51:15 PM PDT 24
Finished May 05 02:51:24 PM PDT 24
Peak memory 202096 kb
Host smart-065fc415-b238-4e4e-8061-05b96f7c2117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166759588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1166759588
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3789696113
Short name T72
Test name
Test status
Simulation time 7715357867 ps
CPU time 18.43 seconds
Started May 05 02:51:17 PM PDT 24
Finished May 05 02:51:36 PM PDT 24
Peak memory 218848 kb
Host smart-146212b5-763e-4265-8697-affbdcb4042f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789696113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3789696113
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.479931382
Short name T489
Test name
Test status
Simulation time 6006545091 ps
CPU time 7.56 seconds
Started May 05 02:51:13 PM PDT 24
Finished May 05 02:51:21 PM PDT 24
Peak memory 202132 kb
Host smart-1f00defe-9764-43b4-9c9b-87ed69f40270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479931382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.479931382
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.416961566
Short name T467
Test name
Test status
Simulation time 171673089790 ps
CPU time 212.64 seconds
Started May 05 02:51:17 PM PDT 24
Finished May 05 02:54:50 PM PDT 24
Peak memory 202320 kb
Host smart-1ffb831f-2d6a-4c29-9d28-b18d99687df5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416961566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.416961566
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1479913158
Short name T110
Test name
Test status
Simulation time 231038822643 ps
CPU time 558.05 seconds
Started May 05 02:51:15 PM PDT 24
Finished May 05 03:00:34 PM PDT 24
Peak memory 219152 kb
Host smart-efd8a619-b5a1-4fa5-a674-2ae7921269cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479913158 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1479913158
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2168309785
Short name T435
Test name
Test status
Simulation time 372505752 ps
CPU time 0.81 seconds
Started May 05 02:51:54 PM PDT 24
Finished May 05 02:51:55 PM PDT 24
Peak memory 201972 kb
Host smart-19ebceff-97be-4012-b6b1-25878d9ebe8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168309785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2168309785
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3429393665
Short name T756
Test name
Test status
Simulation time 337776984736 ps
CPU time 63.34 seconds
Started May 05 02:51:58 PM PDT 24
Finished May 05 02:53:02 PM PDT 24
Peak memory 202356 kb
Host smart-6f8737c9-18f7-464e-a2aa-1107d62f2401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429393665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3429393665
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3227170169
Short name T190
Test name
Test status
Simulation time 336167650818 ps
CPU time 795.74 seconds
Started May 05 02:51:55 PM PDT 24
Finished May 05 03:05:11 PM PDT 24
Peak memory 202276 kb
Host smart-49f8330f-cac8-49a7-af34-87698dbb27fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227170169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3227170169
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.525067987
Short name T684
Test name
Test status
Simulation time 162758901105 ps
CPU time 70.52 seconds
Started May 05 02:51:53 PM PDT 24
Finished May 05 02:53:04 PM PDT 24
Peak memory 202304 kb
Host smart-202d45a1-4806-4a4c-be2d-36246bdf87d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=525067987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.525067987
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.147186145
Short name T679
Test name
Test status
Simulation time 495472067852 ps
CPU time 1004.93 seconds
Started May 05 02:51:50 PM PDT 24
Finished May 05 03:08:36 PM PDT 24
Peak memory 202480 kb
Host smart-9ceeb1b8-3497-498a-9381-84f1d4dce900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147186145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.147186145
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3336827903
Short name T588
Test name
Test status
Simulation time 168996744977 ps
CPU time 181.44 seconds
Started May 05 02:51:54 PM PDT 24
Finished May 05 02:54:56 PM PDT 24
Peak memory 202276 kb
Host smart-855c1501-465e-4e0f-8b7f-2f92cad1de93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336827903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3336827903
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.4150864992
Short name T544
Test name
Test status
Simulation time 184376545399 ps
CPU time 128.59 seconds
Started May 05 02:51:52 PM PDT 24
Finished May 05 02:54:01 PM PDT 24
Peak memory 202308 kb
Host smart-849ed651-74c0-4f2b-ac2d-a95973be28d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150864992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.4150864992
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1817351503
Short name T616
Test name
Test status
Simulation time 194406155605 ps
CPU time 209.05 seconds
Started May 05 02:51:53 PM PDT 24
Finished May 05 02:55:22 PM PDT 24
Peak memory 202360 kb
Host smart-0fbdcc4d-6ac0-4ee4-b1af-4598c6df7df8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817351503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1817351503
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.888102444
Short name T125
Test name
Test status
Simulation time 101794475252 ps
CPU time 350.36 seconds
Started May 05 02:51:57 PM PDT 24
Finished May 05 02:57:48 PM PDT 24
Peak memory 202660 kb
Host smart-c3a4631d-0918-4346-854d-2478d4260f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888102444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.888102444
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1679404354
Short name T398
Test name
Test status
Simulation time 42939227945 ps
CPU time 93.94 seconds
Started May 05 02:51:56 PM PDT 24
Finished May 05 02:53:30 PM PDT 24
Peak memory 202108 kb
Host smart-ce7c401f-5b97-47a9-b05e-1889ba52cae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679404354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1679404354
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3556194703
Short name T146
Test name
Test status
Simulation time 5276206207 ps
CPU time 13.55 seconds
Started May 05 02:51:55 PM PDT 24
Finished May 05 02:52:09 PM PDT 24
Peak memory 202072 kb
Host smart-d228a867-1df9-4c3f-be62-d4f95b9830bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556194703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3556194703
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.363568826
Short name T470
Test name
Test status
Simulation time 6185117618 ps
CPU time 7.87 seconds
Started May 05 02:51:53 PM PDT 24
Finished May 05 02:52:02 PM PDT 24
Peak memory 202140 kb
Host smart-9e812200-ea19-477b-ae29-5a8581ecac54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363568826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.363568826
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.469729301
Short name T312
Test name
Test status
Simulation time 322846890158 ps
CPU time 200.79 seconds
Started May 05 02:51:55 PM PDT 24
Finished May 05 02:55:17 PM PDT 24
Peak memory 202372 kb
Host smart-8b32ea96-e730-4fa5-9c54-027284b851ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469729301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
469729301
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.4267818351
Short name T502
Test name
Test status
Simulation time 458231981 ps
CPU time 1.15 seconds
Started May 05 02:52:03 PM PDT 24
Finished May 05 02:52:04 PM PDT 24
Peak memory 201992 kb
Host smart-b6a1f05f-348f-4c43-ac47-0c8b125543b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267818351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.4267818351
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3475395770
Short name T583
Test name
Test status
Simulation time 343691528405 ps
CPU time 191.96 seconds
Started May 05 02:52:00 PM PDT 24
Finished May 05 02:55:13 PM PDT 24
Peak memory 202304 kb
Host smart-45c117dd-d9b6-4a56-b3a6-1b4b91e9d0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475395770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3475395770
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.4053399046
Short name T335
Test name
Test status
Simulation time 491353943506 ps
CPU time 1157.89 seconds
Started May 05 02:52:00 PM PDT 24
Finished May 05 03:11:19 PM PDT 24
Peak memory 202332 kb
Host smart-b3d8311d-2db5-484d-9ab8-69063ca2c845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053399046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.4053399046
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.360103581
Short name T742
Test name
Test status
Simulation time 490668649413 ps
CPU time 1200.32 seconds
Started May 05 02:52:03 PM PDT 24
Finished May 05 03:12:04 PM PDT 24
Peak memory 202272 kb
Host smart-9f62a525-6bab-4804-87f5-a656948e6977
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=360103581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.360103581
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3487842493
Short name T175
Test name
Test status
Simulation time 162358364668 ps
CPU time 345.9 seconds
Started May 05 02:51:56 PM PDT 24
Finished May 05 02:57:43 PM PDT 24
Peak memory 202356 kb
Host smart-09e7819e-e60a-4864-85cd-e53701941015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487842493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3487842493
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2038591325
Short name T691
Test name
Test status
Simulation time 329678864753 ps
CPU time 196.68 seconds
Started May 05 02:51:56 PM PDT 24
Finished May 05 02:55:13 PM PDT 24
Peak memory 202272 kb
Host smart-290f1420-86df-4427-8d02-4e3b7638fa67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038591325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2038591325
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1823586672
Short name T667
Test name
Test status
Simulation time 387017645509 ps
CPU time 487.46 seconds
Started May 05 02:52:00 PM PDT 24
Finished May 05 03:00:08 PM PDT 24
Peak memory 202316 kb
Host smart-4c0ed33a-3173-4894-9e28-c164360857b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823586672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1823586672
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.4140389649
Short name T797
Test name
Test status
Simulation time 615186057057 ps
CPU time 1460.14 seconds
Started May 05 02:52:00 PM PDT 24
Finished May 05 03:16:21 PM PDT 24
Peak memory 202280 kb
Host smart-6e9a12a2-b64b-4383-8674-a2a0ba24c8fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140389649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.4140389649
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2896475166
Short name T524
Test name
Test status
Simulation time 111820262654 ps
CPU time 336.38 seconds
Started May 05 02:52:01 PM PDT 24
Finished May 05 02:57:38 PM PDT 24
Peak memory 202720 kb
Host smart-1efc821f-18c2-41ab-a1b5-33607de1bfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896475166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2896475166
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1654034936
Short name T401
Test name
Test status
Simulation time 25455678765 ps
CPU time 31.36 seconds
Started May 05 02:52:01 PM PDT 24
Finished May 05 02:52:33 PM PDT 24
Peak memory 202104 kb
Host smart-469b7a9a-938f-4a57-8704-d5c9061e3f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654034936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1654034936
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.956402592
Short name T219
Test name
Test status
Simulation time 3065315331 ps
CPU time 2.28 seconds
Started May 05 02:51:59 PM PDT 24
Finished May 05 02:52:02 PM PDT 24
Peak memory 202132 kb
Host smart-89f5e3bb-f0a8-4124-b88d-5d08e012ea0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956402592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.956402592
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2365882133
Short name T463
Test name
Test status
Simulation time 5651936197 ps
CPU time 13.87 seconds
Started May 05 02:52:00 PM PDT 24
Finished May 05 02:52:14 PM PDT 24
Peak memory 202120 kb
Host smart-6218970a-0d08-4745-9fa2-56f22b07ee15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365882133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2365882133
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1250957169
Short name T597
Test name
Test status
Simulation time 211126750142 ps
CPU time 242.63 seconds
Started May 05 02:51:59 PM PDT 24
Finished May 05 02:56:02 PM PDT 24
Peak memory 202356 kb
Host smart-9feeb581-b538-484b-a7f1-793a4ef04a90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250957169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1250957169
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.4269700743
Short name T17
Test name
Test status
Simulation time 241202276559 ps
CPU time 167.68 seconds
Started May 05 02:52:00 PM PDT 24
Finished May 05 02:54:48 PM PDT 24
Peak memory 210592 kb
Host smart-fb72d6aa-19d2-4dc9-b1a1-2effe0a8c118
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269700743 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.4269700743
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1192932113
Short name T665
Test name
Test status
Simulation time 366262480 ps
CPU time 1 seconds
Started May 05 02:52:07 PM PDT 24
Finished May 05 02:52:08 PM PDT 24
Peak memory 202052 kb
Host smart-eb051b44-9f83-457c-be83-b49c0bc2ef06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192932113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1192932113
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3046085335
Short name T150
Test name
Test status
Simulation time 328877574726 ps
CPU time 202.35 seconds
Started May 05 02:52:05 PM PDT 24
Finished May 05 02:55:28 PM PDT 24
Peak memory 202296 kb
Host smart-316e45cd-3fdd-44c1-9921-b7b071962a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046085335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3046085335
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1972962489
Short name T200
Test name
Test status
Simulation time 167885049133 ps
CPU time 56.5 seconds
Started May 05 02:52:00 PM PDT 24
Finished May 05 02:52:57 PM PDT 24
Peak memory 202260 kb
Host smart-ba967207-3e33-4520-81ce-8704dc582edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972962489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1972962489
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1491310771
Short name T748
Test name
Test status
Simulation time 164388339589 ps
CPU time 304.27 seconds
Started May 05 02:52:01 PM PDT 24
Finished May 05 02:57:06 PM PDT 24
Peak memory 202260 kb
Host smart-4916bc49-b825-45ec-85dd-11149c5c814b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491310771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1491310771
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1418779632
Short name T501
Test name
Test status
Simulation time 338967499602 ps
CPU time 199.71 seconds
Started May 05 02:52:00 PM PDT 24
Finished May 05 02:55:20 PM PDT 24
Peak memory 202340 kb
Host smart-8588a9b1-e1a7-4fd7-ac4d-c7a1775e846d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418779632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1418779632
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1751902260
Short name T711
Test name
Test status
Simulation time 492611050749 ps
CPU time 198.81 seconds
Started May 05 02:52:01 PM PDT 24
Finished May 05 02:55:21 PM PDT 24
Peak memory 202272 kb
Host smart-caf2d94c-abac-4a18-8108-a937d021e292
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751902260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1751902260
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1694375019
Short name T358
Test name
Test status
Simulation time 201837209024 ps
CPU time 123.1 seconds
Started May 05 02:52:00 PM PDT 24
Finished May 05 02:54:04 PM PDT 24
Peak memory 202360 kb
Host smart-30b55f01-3c5e-449b-bb9d-e8d359f3356f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694375019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1694375019
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1674259072
Short name T660
Test name
Test status
Simulation time 207243734121 ps
CPU time 151.01 seconds
Started May 05 02:51:59 PM PDT 24
Finished May 05 02:54:30 PM PDT 24
Peak memory 202292 kb
Host smart-d7a35f89-c8e7-4770-8b2f-cb594926b44c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674259072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1674259072
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1599203129
Short name T642
Test name
Test status
Simulation time 122399508367 ps
CPU time 500.12 seconds
Started May 05 02:52:06 PM PDT 24
Finished May 05 03:00:26 PM PDT 24
Peak memory 202712 kb
Host smart-9d5e7950-ec20-4d58-bdaf-c60432c5b6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599203129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1599203129
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2578621001
Short name T643
Test name
Test status
Simulation time 46505609932 ps
CPU time 42.55 seconds
Started May 05 02:52:03 PM PDT 24
Finished May 05 02:52:46 PM PDT 24
Peak memory 202112 kb
Host smart-8164e85e-c012-4b06-a956-30a10091615c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578621001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2578621001
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2729526055
Short name T395
Test name
Test status
Simulation time 2655604699 ps
CPU time 6.68 seconds
Started May 05 02:52:05 PM PDT 24
Finished May 05 02:52:12 PM PDT 24
Peak memory 202112 kb
Host smart-92ad2d5d-0e18-49b5-8270-fb91dcacd4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729526055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2729526055
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2060856838
Short name T671
Test name
Test status
Simulation time 5891489181 ps
CPU time 8.16 seconds
Started May 05 02:52:01 PM PDT 24
Finished May 05 02:52:09 PM PDT 24
Peak memory 202096 kb
Host smart-adfac48b-acd0-4e99-abeb-12129722f741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060856838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2060856838
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3895135178
Short name T101
Test name
Test status
Simulation time 190633239071 ps
CPU time 326.24 seconds
Started May 05 02:52:05 PM PDT 24
Finished May 05 02:57:31 PM PDT 24
Peak memory 202300 kb
Host smart-e9c466f6-a220-467b-aa9b-dc697d4bbe28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895135178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3895135178
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1070489035
Short name T469
Test name
Test status
Simulation time 491657302 ps
CPU time 0.9 seconds
Started May 05 02:52:15 PM PDT 24
Finished May 05 02:52:16 PM PDT 24
Peak memory 202016 kb
Host smart-1455555c-2d7b-4aaf-ade4-b81188d27847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070489035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1070489035
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1876935148
Short name T732
Test name
Test status
Simulation time 326427758047 ps
CPU time 207.6 seconds
Started May 05 02:52:07 PM PDT 24
Finished May 05 02:55:35 PM PDT 24
Peak memory 202304 kb
Host smart-0a20eea6-94c6-4f2b-ae88-546e9c3fd91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876935148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1876935148
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2377943605
Short name T609
Test name
Test status
Simulation time 493240137793 ps
CPU time 1220.4 seconds
Started May 05 02:52:08 PM PDT 24
Finished May 05 03:12:28 PM PDT 24
Peak memory 202304 kb
Host smart-7861da8f-3f60-4abb-aa35-a49a7dd2ef90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377943605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2377943605
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3431979992
Short name T180
Test name
Test status
Simulation time 492193308020 ps
CPU time 318.62 seconds
Started May 05 02:52:08 PM PDT 24
Finished May 05 02:57:27 PM PDT 24
Peak memory 202476 kb
Host smart-c8587f75-6c62-448c-ac85-55c4e9092a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431979992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3431979992
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2287590097
Short name T477
Test name
Test status
Simulation time 330279969471 ps
CPU time 365.81 seconds
Started May 05 02:52:09 PM PDT 24
Finished May 05 02:58:15 PM PDT 24
Peak memory 202292 kb
Host smart-8035279b-af4f-4238-a67a-2732a1c5f1b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287590097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2287590097
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1460130291
Short name T166
Test name
Test status
Simulation time 658080134782 ps
CPU time 410.13 seconds
Started May 05 02:52:08 PM PDT 24
Finished May 05 02:58:59 PM PDT 24
Peak memory 202296 kb
Host smart-e39b7cf2-7828-402d-8a25-b5b27e7c9034
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460130291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1460130291
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.4239278495
Short name T220
Test name
Test status
Simulation time 586487789688 ps
CPU time 1287.05 seconds
Started May 05 02:52:09 PM PDT 24
Finished May 05 03:13:36 PM PDT 24
Peak memory 202260 kb
Host smart-32a7d76b-12aa-48cd-9617-954b481d715c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239278495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.4239278495
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3428523078
Short name T766
Test name
Test status
Simulation time 65251999479 ps
CPU time 331.81 seconds
Started May 05 02:52:12 PM PDT 24
Finished May 05 02:57:44 PM PDT 24
Peak memory 202664 kb
Host smart-3647546b-3d0a-464c-af2c-bfc19582f551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428523078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3428523078
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3360170915
Short name T647
Test name
Test status
Simulation time 42491667722 ps
CPU time 26.66 seconds
Started May 05 02:52:13 PM PDT 24
Finished May 05 02:52:40 PM PDT 24
Peak memory 202100 kb
Host smart-e0867f6b-72c7-4f75-ac3c-dd078dc334b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360170915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3360170915
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.885395619
Short name T397
Test name
Test status
Simulation time 3452764630 ps
CPU time 4.88 seconds
Started May 05 02:52:13 PM PDT 24
Finished May 05 02:52:18 PM PDT 24
Peak memory 202112 kb
Host smart-691db29a-133c-498b-bf61-dcfcef43af20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885395619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.885395619
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.97453811
Short name T568
Test name
Test status
Simulation time 6015177057 ps
CPU time 7.26 seconds
Started May 05 02:52:08 PM PDT 24
Finished May 05 02:52:16 PM PDT 24
Peak memory 202144 kb
Host smart-ab514358-8301-4163-91ac-4578c1228120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97453811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.97453811
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2459399734
Short name T37
Test name
Test status
Simulation time 344977379732 ps
CPU time 217.73 seconds
Started May 05 02:52:13 PM PDT 24
Finished May 05 02:55:52 PM PDT 24
Peak memory 202284 kb
Host smart-a9dea65f-5cf3-48a3-bb05-ff63c5a690eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459399734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2459399734
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3622827000
Short name T127
Test name
Test status
Simulation time 94078231625 ps
CPU time 125.5 seconds
Started May 05 02:52:14 PM PDT 24
Finished May 05 02:54:20 PM PDT 24
Peak memory 210988 kb
Host smart-c343c51d-8e55-4b77-a604-bb894a3bdfb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622827000 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3622827000
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2107158774
Short name T562
Test name
Test status
Simulation time 419184032 ps
CPU time 0.69 seconds
Started May 05 02:52:23 PM PDT 24
Finished May 05 02:52:24 PM PDT 24
Peak memory 201924 kb
Host smart-596ce039-7aa5-4b6b-95bf-05efbe0c1f92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107158774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2107158774
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3947490732
Short name T203
Test name
Test status
Simulation time 332315554850 ps
CPU time 715.33 seconds
Started May 05 02:52:16 PM PDT 24
Finished May 05 03:04:12 PM PDT 24
Peak memory 202292 kb
Host smart-a49c4d71-d0de-48f9-affa-0d3e74af4eec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947490732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3947490732
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1225344474
Short name T570
Test name
Test status
Simulation time 324758649158 ps
CPU time 741.82 seconds
Started May 05 02:52:16 PM PDT 24
Finished May 05 03:04:39 PM PDT 24
Peak memory 202384 kb
Host smart-d93969aa-dd36-41f4-bc8f-ea74c6b43349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225344474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1225344474
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3546425169
Short name T708
Test name
Test status
Simulation time 321487752728 ps
CPU time 383.37 seconds
Started May 05 02:52:15 PM PDT 24
Finished May 05 02:58:39 PM PDT 24
Peak memory 202312 kb
Host smart-fcea770e-f072-4a01-ab5e-7baa03de31d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546425169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3546425169
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2147666107
Short name T278
Test name
Test status
Simulation time 168606313773 ps
CPU time 398.25 seconds
Started May 05 02:52:14 PM PDT 24
Finished May 05 02:58:53 PM PDT 24
Peak memory 202356 kb
Host smart-4b20a7a8-c149-4042-a90e-eeb1019e4821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147666107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2147666107
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2305224642
Short name T493
Test name
Test status
Simulation time 164760477235 ps
CPU time 403 seconds
Started May 05 02:52:16 PM PDT 24
Finished May 05 02:58:59 PM PDT 24
Peak memory 202364 kb
Host smart-79ecb161-c404-45e8-9111-bde53546af65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305224642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2305224642
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.259009747
Short name T367
Test name
Test status
Simulation time 616527497780 ps
CPU time 351.07 seconds
Started May 05 02:52:16 PM PDT 24
Finished May 05 02:58:07 PM PDT 24
Peak memory 202348 kb
Host smart-dc2e4e78-39bb-4147-bded-d71727c9ffe8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259009747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.259009747
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.824775666
Short name T590
Test name
Test status
Simulation time 401421938782 ps
CPU time 101.91 seconds
Started May 05 02:52:17 PM PDT 24
Finished May 05 02:53:59 PM PDT 24
Peak memory 202380 kb
Host smart-aafa52c6-0a6c-478c-bd49-22234fd85adf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824775666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.824775666
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3821307863
Short name T729
Test name
Test status
Simulation time 94579637942 ps
CPU time 286.43 seconds
Started May 05 02:52:21 PM PDT 24
Finished May 05 02:57:07 PM PDT 24
Peak memory 202584 kb
Host smart-0c8fda77-5ef9-4910-9e69-ac4002f2198e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821307863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3821307863
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2236338347
Short name T683
Test name
Test status
Simulation time 38503265769 ps
CPU time 87.26 seconds
Started May 05 02:52:22 PM PDT 24
Finished May 05 02:53:50 PM PDT 24
Peak memory 202128 kb
Host smart-a692ba4d-9fb7-407c-b667-c8bdbb19384c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236338347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2236338347
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.292801032
Short name T385
Test name
Test status
Simulation time 5133442764 ps
CPU time 4.2 seconds
Started May 05 02:52:23 PM PDT 24
Finished May 05 02:52:27 PM PDT 24
Peak memory 202136 kb
Host smart-6f96390a-7587-46be-ad7b-beddeea249cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292801032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.292801032
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4110888319
Short name T507
Test name
Test status
Simulation time 5827358878 ps
CPU time 3.56 seconds
Started May 05 02:52:12 PM PDT 24
Finished May 05 02:52:16 PM PDT 24
Peak memory 202048 kb
Host smart-f0c09ff3-f06a-4d0b-a0c2-0a795c86951e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110888319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4110888319
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1522699305
Short name T31
Test name
Test status
Simulation time 175425848169 ps
CPU time 375.1 seconds
Started May 05 02:52:23 PM PDT 24
Finished May 05 02:58:39 PM PDT 24
Peak memory 202296 kb
Host smart-8c92ba2f-c083-483c-be55-8f9a84148c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522699305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1522699305
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3658803631
Short name T48
Test name
Test status
Simulation time 50608999508 ps
CPU time 48.22 seconds
Started May 05 02:52:21 PM PDT 24
Finished May 05 02:53:10 PM PDT 24
Peak memory 202348 kb
Host smart-8559a4d9-5b69-40ed-a3e5-d067f69d5754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658803631 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3658803631
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2413314830
Short name T713
Test name
Test status
Simulation time 442572454 ps
CPU time 1.31 seconds
Started May 05 02:52:33 PM PDT 24
Finished May 05 02:52:35 PM PDT 24
Peak memory 202008 kb
Host smart-2e66f711-24f6-4191-8a0b-f534cc20d0e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413314830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2413314830
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.450227804
Short name T116
Test name
Test status
Simulation time 321301665866 ps
CPU time 56.77 seconds
Started May 05 02:52:25 PM PDT 24
Finished May 05 02:53:22 PM PDT 24
Peak memory 202328 kb
Host smart-e0fecd34-667c-44c8-b111-a104b574b456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450227804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.450227804
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3718265945
Short name T522
Test name
Test status
Simulation time 492494214907 ps
CPU time 704.73 seconds
Started May 05 02:52:28 PM PDT 24
Finished May 05 03:04:13 PM PDT 24
Peak memory 202292 kb
Host smart-05db361a-44fc-4281-90c5-098e1221f307
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718265945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3718265945
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1305562680
Short name T245
Test name
Test status
Simulation time 328940299756 ps
CPU time 810.12 seconds
Started May 05 02:52:24 PM PDT 24
Finished May 05 03:05:55 PM PDT 24
Peak memory 202276 kb
Host smart-a667deb9-02c8-4d96-b44c-4362eae3ad1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305562680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1305562680
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.4093798325
Short name T617
Test name
Test status
Simulation time 326623788477 ps
CPU time 204.4 seconds
Started May 05 02:52:29 PM PDT 24
Finished May 05 02:55:54 PM PDT 24
Peak memory 202284 kb
Host smart-a3a2ce3b-8c80-4cfd-bf7f-d5bb529f2e8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093798325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.4093798325
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3973673242
Short name T212
Test name
Test status
Simulation time 614507130231 ps
CPU time 352.01 seconds
Started May 05 02:52:27 PM PDT 24
Finished May 05 02:58:19 PM PDT 24
Peak memory 202332 kb
Host smart-6845d1be-53f2-452c-b7a4-74121c18aa80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973673242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3973673242
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2039349434
Short name T682
Test name
Test status
Simulation time 592041047506 ps
CPU time 1359.19 seconds
Started May 05 02:52:26 PM PDT 24
Finished May 05 03:15:06 PM PDT 24
Peak memory 202304 kb
Host smart-ca5c6fa0-27c6-405b-af60-9580ff7770d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039349434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2039349434
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3953992534
Short name T205
Test name
Test status
Simulation time 128409577914 ps
CPU time 434.19 seconds
Started May 05 02:52:31 PM PDT 24
Finished May 05 02:59:45 PM PDT 24
Peak memory 202700 kb
Host smart-601c44d4-2ff1-415b-8679-35ea1c584427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953992534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3953992534
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2776418515
Short name T627
Test name
Test status
Simulation time 22922471671 ps
CPU time 54.12 seconds
Started May 05 02:52:30 PM PDT 24
Finished May 05 02:53:24 PM PDT 24
Peak memory 202124 kb
Host smart-66b37fb7-39fe-4336-a20a-9e8bdba3c77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776418515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2776418515
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3773208591
Short name T786
Test name
Test status
Simulation time 3271582940 ps
CPU time 2.79 seconds
Started May 05 02:52:25 PM PDT 24
Finished May 05 02:52:28 PM PDT 24
Peak memory 202100 kb
Host smart-07d31864-5c14-4d89-8e0b-c29a626061d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773208591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3773208591
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2772617414
Short name T9
Test name
Test status
Simulation time 6036269845 ps
CPU time 4.75 seconds
Started May 05 02:52:20 PM PDT 24
Finished May 05 02:52:25 PM PDT 24
Peak memory 202140 kb
Host smart-4cae9ab2-a167-4f97-9e83-fd7ffa29ab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772617414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2772617414
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4294792947
Short name T334
Test name
Test status
Simulation time 330430573207 ps
CPU time 276.7 seconds
Started May 05 02:52:30 PM PDT 24
Finished May 05 02:57:07 PM PDT 24
Peak memory 219084 kb
Host smart-c93e78c4-c8e7-4093-965e-897960865990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294792947 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.4294792947
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1221543837
Short name T434
Test name
Test status
Simulation time 319196903 ps
CPU time 1.02 seconds
Started May 05 02:52:42 PM PDT 24
Finished May 05 02:52:44 PM PDT 24
Peak memory 201988 kb
Host smart-f97c95e5-a965-4370-a275-e100b0f01790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221543837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1221543837
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.68514398
Short name T320
Test name
Test status
Simulation time 329040324869 ps
CPU time 171.03 seconds
Started May 05 02:52:42 PM PDT 24
Finished May 05 02:55:33 PM PDT 24
Peak memory 202388 kb
Host smart-e1c64533-1401-4d43-b847-695673e5b655
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68514398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gatin
g.68514398
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.649652610
Short name T258
Test name
Test status
Simulation time 486920894799 ps
CPU time 1161.16 seconds
Started May 05 02:52:40 PM PDT 24
Finished May 05 03:12:02 PM PDT 24
Peak memory 202376 kb
Host smart-0ec34fdc-cfb4-4b49-b946-716861e6e75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649652610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.649652610
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2773780560
Short name T429
Test name
Test status
Simulation time 167214107963 ps
CPU time 102.24 seconds
Started May 05 02:52:38 PM PDT 24
Finished May 05 02:54:21 PM PDT 24
Peak memory 202288 kb
Host smart-38a803fd-be64-4172-81aa-9ffb9e6c0271
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773780560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2773780560
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3193819304
Short name T673
Test name
Test status
Simulation time 490518816694 ps
CPU time 275.15 seconds
Started May 05 02:52:36 PM PDT 24
Finished May 05 02:57:11 PM PDT 24
Peak memory 202368 kb
Host smart-283f90ab-5eb8-4634-82cb-4a9be1feab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193819304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3193819304
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1292397245
Short name T553
Test name
Test status
Simulation time 332868511925 ps
CPU time 804.52 seconds
Started May 05 02:52:39 PM PDT 24
Finished May 05 03:06:04 PM PDT 24
Peak memory 202344 kb
Host smart-b983cdd4-a60f-42b8-a45b-a308942e7b5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292397245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1292397245
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3112769026
Short name T271
Test name
Test status
Simulation time 186150883517 ps
CPU time 448.68 seconds
Started May 05 02:52:38 PM PDT 24
Finished May 05 03:00:07 PM PDT 24
Peak memory 202300 kb
Host smart-e3d3a3a6-25c2-46a8-a551-3d466f361d79
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112769026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3112769026
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.578459482
Short name T13
Test name
Test status
Simulation time 584465913502 ps
CPU time 702.39 seconds
Started May 05 02:52:44 PM PDT 24
Finished May 05 03:04:27 PM PDT 24
Peak memory 202244 kb
Host smart-88b5b5ef-1f9b-4fa4-b8b0-d1af665894ec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578459482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.578459482
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1379066269
Short name T482
Test name
Test status
Simulation time 74783554496 ps
CPU time 400.83 seconds
Started May 05 02:52:41 PM PDT 24
Finished May 05 02:59:22 PM PDT 24
Peak memory 202648 kb
Host smart-924fac51-0d76-4f2e-ac6f-1f8d4207882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379066269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1379066269
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.256329660
Short name T681
Test name
Test status
Simulation time 39178419288 ps
CPU time 45.59 seconds
Started May 05 02:52:46 PM PDT 24
Finished May 05 02:53:32 PM PDT 24
Peak memory 202140 kb
Host smart-772f6ba9-5c9f-40fe-9456-8083fc7568d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256329660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.256329660
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2393603233
Short name T763
Test name
Test status
Simulation time 5501621965 ps
CPU time 12.24 seconds
Started May 05 02:52:45 PM PDT 24
Finished May 05 02:52:58 PM PDT 24
Peak memory 202052 kb
Host smart-28492b5c-009c-4ea8-9a50-6631dbe9d722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393603233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2393603233
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1832596717
Short name T423
Test name
Test status
Simulation time 5746637393 ps
CPU time 3.67 seconds
Started May 05 02:52:36 PM PDT 24
Finished May 05 02:52:40 PM PDT 24
Peak memory 202140 kb
Host smart-7767056e-3bed-45f7-bf98-e2a878e24827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832596717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1832596717
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2967048286
Short name T735
Test name
Test status
Simulation time 423678424913 ps
CPU time 907.91 seconds
Started May 05 02:52:44 PM PDT 24
Finished May 05 03:07:52 PM PDT 24
Peak memory 202256 kb
Host smart-787f5ca7-53ee-48fe-a4d4-2fdaa4932d71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967048286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2967048286
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1980721020
Short name T319
Test name
Test status
Simulation time 25896184056 ps
CPU time 53.16 seconds
Started May 05 02:52:45 PM PDT 24
Finished May 05 02:53:39 PM PDT 24
Peak memory 202380 kb
Host smart-8feb8817-97a0-4bd0-b220-92517f306493
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980721020 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1980721020
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.851337438
Short name T427
Test name
Test status
Simulation time 529191816 ps
CPU time 0.92 seconds
Started May 05 02:52:51 PM PDT 24
Finished May 05 02:52:52 PM PDT 24
Peak memory 201996 kb
Host smart-e5bc0bef-1beb-401e-a501-3c3c61afc77c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851337438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.851337438
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2848468665
Short name T346
Test name
Test status
Simulation time 533404328070 ps
CPU time 535.15 seconds
Started May 05 02:52:46 PM PDT 24
Finished May 05 03:01:42 PM PDT 24
Peak memory 202336 kb
Host smart-4ceac35e-e459-4c7f-b517-1e6cd1cb5605
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848468665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2848468665
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3301772692
Short name T365
Test name
Test status
Simulation time 161521104798 ps
CPU time 400.91 seconds
Started May 05 02:52:48 PM PDT 24
Finished May 05 02:59:29 PM PDT 24
Peak memory 202288 kb
Host smart-f06cf404-7607-4d55-ad19-56e4d37c465c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301772692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3301772692
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1205134708
Short name T464
Test name
Test status
Simulation time 323708927411 ps
CPU time 798.56 seconds
Started May 05 02:52:49 PM PDT 24
Finished May 05 03:06:08 PM PDT 24
Peak memory 202296 kb
Host smart-4aac8ba3-175e-4655-8c90-3a05a2fe59b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205134708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1205134708
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2769871031
Short name T601
Test name
Test status
Simulation time 320458040825 ps
CPU time 672.14 seconds
Started May 05 02:52:47 PM PDT 24
Finished May 05 03:03:59 PM PDT 24
Peak memory 202428 kb
Host smart-9c96fe25-2831-4f98-9e41-f74d2e059cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769871031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2769871031
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.529930168
Short name T645
Test name
Test status
Simulation time 482959449112 ps
CPU time 275.24 seconds
Started May 05 02:52:48 PM PDT 24
Finished May 05 02:57:24 PM PDT 24
Peak memory 202264 kb
Host smart-5174abe6-140a-40f3-9fe9-3e277c43f533
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=529930168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.529930168
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.539048267
Short name T350
Test name
Test status
Simulation time 536009445245 ps
CPU time 1269.81 seconds
Started May 05 02:52:47 PM PDT 24
Finished May 05 03:13:57 PM PDT 24
Peak memory 202336 kb
Host smart-c0cae811-206d-4bc3-bd3c-7616457671a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539048267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.539048267
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3234178692
Short name T677
Test name
Test status
Simulation time 616216390905 ps
CPU time 441.74 seconds
Started May 05 02:52:46 PM PDT 24
Finished May 05 03:00:08 PM PDT 24
Peak memory 202300 kb
Host smart-ade3640b-b321-43e1-b362-b0ef2cc827bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234178692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3234178692
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.4029575056
Short name T554
Test name
Test status
Simulation time 79670960229 ps
CPU time 398.81 seconds
Started May 05 02:52:51 PM PDT 24
Finished May 05 02:59:30 PM PDT 24
Peak memory 202664 kb
Host smart-c63f55e4-ba7a-48ca-b429-50bfe0b22ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029575056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.4029575056
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.10603577
Short name T486
Test name
Test status
Simulation time 43935670880 ps
CPU time 89.69 seconds
Started May 05 02:52:46 PM PDT 24
Finished May 05 02:54:16 PM PDT 24
Peak memory 202108 kb
Host smart-963945fd-af69-4e5c-87db-45f3c4446bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10603577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.10603577
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3874142189
Short name T592
Test name
Test status
Simulation time 5024859694 ps
CPU time 2.67 seconds
Started May 05 02:52:48 PM PDT 24
Finished May 05 02:52:51 PM PDT 24
Peak memory 202088 kb
Host smart-12e1a0ba-213b-45c1-835b-05f49b00ece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874142189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3874142189
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1381504501
Short name T608
Test name
Test status
Simulation time 5675170485 ps
CPU time 3.97 seconds
Started May 05 02:52:46 PM PDT 24
Finished May 05 02:52:51 PM PDT 24
Peak memory 202140 kb
Host smart-cd4381e7-ffa7-4052-a016-648d96651404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381504501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1381504501
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2847655824
Short name T448
Test name
Test status
Simulation time 6835882565 ps
CPU time 14.57 seconds
Started May 05 02:52:51 PM PDT 24
Finished May 05 02:53:06 PM PDT 24
Peak memory 202088 kb
Host smart-8abc08c6-fb36-44fe-b88e-668c0c5f3c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847655824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2847655824
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3454082152
Short name T39
Test name
Test status
Simulation time 118194751228 ps
CPU time 259.54 seconds
Started May 05 02:52:51 PM PDT 24
Finished May 05 02:57:11 PM PDT 24
Peak memory 211040 kb
Host smart-5b8ce870-ef35-40ae-9027-199cace7c941
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454082152 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3454082152
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4092413913
Short name T208
Test name
Test status
Simulation time 401626927 ps
CPU time 1.15 seconds
Started May 05 02:53:00 PM PDT 24
Finished May 05 02:53:02 PM PDT 24
Peak memory 201964 kb
Host smart-900fcc23-b2e7-4398-b3ed-4f7f6eb469e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092413913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4092413913
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2325454668
Short name T202
Test name
Test status
Simulation time 494215851193 ps
CPU time 1139.14 seconds
Started May 05 02:52:57 PM PDT 24
Finished May 05 03:11:56 PM PDT 24
Peak memory 202304 kb
Host smart-3d1e72bf-4d70-4f12-ac2f-5ca148bce652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325454668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2325454668
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3855813287
Short name T599
Test name
Test status
Simulation time 485492701771 ps
CPU time 1143.45 seconds
Started May 05 02:52:58 PM PDT 24
Finished May 05 03:12:02 PM PDT 24
Peak memory 202292 kb
Host smart-c03c8c3f-0bfd-4906-a96c-d483e12269c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855813287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3855813287
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1741640338
Short name T715
Test name
Test status
Simulation time 341150946653 ps
CPU time 117.92 seconds
Started May 05 02:52:57 PM PDT 24
Finished May 05 02:54:55 PM PDT 24
Peak memory 202268 kb
Host smart-9a626fcd-16e9-4080-b6b0-ade9a60acce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741640338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1741640338
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1483771969
Short name T788
Test name
Test status
Simulation time 496100413997 ps
CPU time 280.1 seconds
Started May 05 02:52:57 PM PDT 24
Finished May 05 02:57:37 PM PDT 24
Peak memory 202276 kb
Host smart-bcd679f3-c687-431d-9ef3-b0ed8affc72b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483771969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1483771969
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2243282843
Short name T267
Test name
Test status
Simulation time 387616464496 ps
CPU time 811.18 seconds
Started May 05 02:53:04 PM PDT 24
Finished May 05 03:06:36 PM PDT 24
Peak memory 202368 kb
Host smart-91af466f-d8f3-4db0-afbf-c4e90c946485
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243282843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2243282843
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2146264003
Short name T634
Test name
Test status
Simulation time 610837384715 ps
CPU time 1389.33 seconds
Started May 05 02:53:04 PM PDT 24
Finished May 05 03:16:14 PM PDT 24
Peak memory 202280 kb
Host smart-7043433a-1be2-4fb3-96de-53ac343f252b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146264003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2146264003
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2914085365
Short name T446
Test name
Test status
Simulation time 121116693222 ps
CPU time 671.84 seconds
Started May 05 02:53:00 PM PDT 24
Finished May 05 03:04:13 PM PDT 24
Peak memory 202736 kb
Host smart-82712f52-4b28-426b-bbc0-71d194d102f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914085365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2914085365
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4114669793
Short name T701
Test name
Test status
Simulation time 42266197970 ps
CPU time 90.91 seconds
Started May 05 02:53:00 PM PDT 24
Finished May 05 02:54:31 PM PDT 24
Peak memory 202140 kb
Host smart-e2472d35-a9ae-488b-8031-32c76e4f4d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114669793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4114669793
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3613418631
Short name T680
Test name
Test status
Simulation time 5318692421 ps
CPU time 12 seconds
Started May 05 02:52:59 PM PDT 24
Finished May 05 02:53:11 PM PDT 24
Peak memory 202140 kb
Host smart-b591b864-23c9-473e-be96-f004a77b4232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613418631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3613418631
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.415053649
Short name T436
Test name
Test status
Simulation time 5814725303 ps
CPU time 14.97 seconds
Started May 05 02:52:52 PM PDT 24
Finished May 05 02:53:08 PM PDT 24
Peak memory 202116 kb
Host smart-c2261128-4819-4c8d-81fa-a342e28d4dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415053649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.415053649
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.4237990152
Short name T91
Test name
Test status
Simulation time 67439908238 ps
CPU time 89.25 seconds
Started May 05 02:53:04 PM PDT 24
Finished May 05 02:54:33 PM PDT 24
Peak memory 211028 kb
Host smart-f72a6a6b-aa36-497e-b43e-ba3d74baa94b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237990152 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.4237990152
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.667732099
Short name T244
Test name
Test status
Simulation time 343726832549 ps
CPU time 749.05 seconds
Started May 05 02:53:04 PM PDT 24
Finished May 05 03:05:34 PM PDT 24
Peak memory 202328 kb
Host smart-2cc1ad96-97cd-4444-846a-1e13a4a15b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667732099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.667732099
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2206476356
Short name T324
Test name
Test status
Simulation time 325511381603 ps
CPU time 396.35 seconds
Started May 05 02:53:05 PM PDT 24
Finished May 05 02:59:42 PM PDT 24
Peak memory 202352 kb
Host smart-ec080868-6a04-450d-93f0-6905a5867f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206476356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2206476356
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2361232737
Short name T537
Test name
Test status
Simulation time 161788580002 ps
CPU time 349.4 seconds
Started May 05 02:53:06 PM PDT 24
Finished May 05 02:58:56 PM PDT 24
Peak memory 202292 kb
Host smart-aa9e1146-3242-460e-a855-a1f71220870c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361232737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2361232737
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.466583483
Short name T298
Test name
Test status
Simulation time 327335280730 ps
CPU time 362.59 seconds
Started May 05 02:53:04 PM PDT 24
Finished May 05 02:59:07 PM PDT 24
Peak memory 202380 kb
Host smart-0c42257c-f83d-4617-9fff-48a3a797a057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466583483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.466583483
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.4125038622
Short name T741
Test name
Test status
Simulation time 325129437997 ps
CPU time 94.4 seconds
Started May 05 02:53:01 PM PDT 24
Finished May 05 02:54:36 PM PDT 24
Peak memory 202256 kb
Host smart-8d31f628-0fe9-480c-8b9c-b423e26a4de0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125038622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.4125038622
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1104742770
Short name T183
Test name
Test status
Simulation time 603721762098 ps
CPU time 166.19 seconds
Started May 05 02:53:03 PM PDT 24
Finished May 05 02:55:49 PM PDT 24
Peak memory 202380 kb
Host smart-9dbf120b-c49a-4228-800b-38f0fff6d2e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104742770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1104742770
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2036181811
Short name T686
Test name
Test status
Simulation time 110476231100 ps
CPU time 422.08 seconds
Started May 05 02:53:10 PM PDT 24
Finished May 05 03:00:12 PM PDT 24
Peak memory 202736 kb
Host smart-9f254c44-63a5-4ed5-a5a7-268735a70810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036181811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2036181811
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1708419731
Short name T222
Test name
Test status
Simulation time 22805007298 ps
CPU time 26.12 seconds
Started May 05 02:53:10 PM PDT 24
Finished May 05 02:53:37 PM PDT 24
Peak memory 202100 kb
Host smart-08d64adf-4dde-4ead-a8f2-4da183fc7d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708419731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1708419731
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1102325764
Short name T780
Test name
Test status
Simulation time 3210140302 ps
CPU time 7.77 seconds
Started May 05 02:53:08 PM PDT 24
Finished May 05 02:53:16 PM PDT 24
Peak memory 202080 kb
Host smart-e8054b0c-48d6-4a72-a2f1-fbd8a6bf5d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102325764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1102325764
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3909954591
Short name T462
Test name
Test status
Simulation time 5799008144 ps
CPU time 14.49 seconds
Started May 05 02:53:00 PM PDT 24
Finished May 05 02:53:15 PM PDT 24
Peak memory 202048 kb
Host smart-9b32fa6b-87c5-4483-92db-9d7d4f9b0283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909954591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3909954591
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3246993147
Short name T109
Test name
Test status
Simulation time 213024373598 ps
CPU time 363.11 seconds
Started May 05 02:53:10 PM PDT 24
Finished May 05 02:59:13 PM PDT 24
Peak memory 210912 kb
Host smart-2f25059f-64e5-4dd7-a7c2-aca2383d5343
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246993147 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3246993147
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1441557507
Short name T120
Test name
Test status
Simulation time 473312565 ps
CPU time 1.18 seconds
Started May 05 02:51:17 PM PDT 24
Finished May 05 02:51:19 PM PDT 24
Peak memory 201988 kb
Host smart-42393051-b6c8-4cdb-88a5-8c802a7306a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441557507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1441557507
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1930302406
Short name T765
Test name
Test status
Simulation time 166899724022 ps
CPU time 95.11 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 02:52:54 PM PDT 24
Peak memory 202284 kb
Host smart-d82967db-8f3a-4338-8b9a-c716882e5442
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930302406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1930302406
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.684425222
Short name T213
Test name
Test status
Simulation time 163062530771 ps
CPU time 365.01 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 02:57:23 PM PDT 24
Peak memory 202344 kb
Host smart-f0d7850c-2ddd-4a2e-9103-2416bba9218b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684425222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.684425222
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3112597611
Short name T299
Test name
Test status
Simulation time 163834106081 ps
CPU time 393.08 seconds
Started May 05 02:51:19 PM PDT 24
Finished May 05 02:57:53 PM PDT 24
Peak memory 202248 kb
Host smart-eb7b7faa-1283-4363-8f3e-2bc5e42098fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112597611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3112597611
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.292083269
Short name T445
Test name
Test status
Simulation time 161807696025 ps
CPU time 170.39 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 02:54:09 PM PDT 24
Peak memory 202284 kb
Host smart-4ff3153a-7296-4c90-9199-4e5132bf8138
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=292083269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.292083269
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3290361780
Short name T442
Test name
Test status
Simulation time 487058038459 ps
CPU time 1034.11 seconds
Started May 05 02:51:19 PM PDT 24
Finished May 05 03:08:34 PM PDT 24
Peak memory 202308 kb
Host smart-6979f37d-32bf-4766-89e2-a091c52c7c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290361780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3290361780
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2037294455
Short name T221
Test name
Test status
Simulation time 329561954239 ps
CPU time 200.19 seconds
Started May 05 02:51:16 PM PDT 24
Finished May 05 02:54:37 PM PDT 24
Peak memory 202304 kb
Host smart-a329bb54-6e75-4070-97b8-ae243c9fbb01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037294455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2037294455
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2980214426
Short name T709
Test name
Test status
Simulation time 356115432575 ps
CPU time 371.47 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 02:57:30 PM PDT 24
Peak memory 202268 kb
Host smart-8c02fc6d-9554-480a-a23a-fb2892ba01db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980214426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2980214426
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.787056288
Short name T444
Test name
Test status
Simulation time 611198420306 ps
CPU time 769.13 seconds
Started May 05 02:51:19 PM PDT 24
Finished May 05 03:04:08 PM PDT 24
Peak memory 202284 kb
Host smart-570ef962-2040-46fd-9ce7-5568626e83d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787056288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.787056288
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2592520539
Short name T27
Test name
Test status
Simulation time 71009260456 ps
CPU time 347.05 seconds
Started May 05 02:51:17 PM PDT 24
Finished May 05 02:57:04 PM PDT 24
Peak memory 202724 kb
Host smart-8db01614-c487-4cc3-9cb4-b664c076e929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592520539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2592520539
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.532320501
Short name T90
Test name
Test status
Simulation time 33136273309 ps
CPU time 80.68 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 02:52:39 PM PDT 24
Peak memory 202112 kb
Host smart-8d110064-81ea-4cb3-866b-325582b02ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532320501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.532320501
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2154489178
Short name T460
Test name
Test status
Simulation time 2853821496 ps
CPU time 1.51 seconds
Started May 05 02:51:19 PM PDT 24
Finished May 05 02:51:21 PM PDT 24
Peak memory 202072 kb
Host smart-b50fbd2b-b0e8-4796-a734-eb1bed0182c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154489178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2154489178
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2570863127
Short name T86
Test name
Test status
Simulation time 7469330884 ps
CPU time 18.02 seconds
Started May 05 02:51:16 PM PDT 24
Finished May 05 02:51:35 PM PDT 24
Peak memory 218912 kb
Host smart-56cb24da-3bef-45c1-aa43-128cff93e7ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570863127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2570863127
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4248932126
Short name T621
Test name
Test status
Simulation time 6167521031 ps
CPU time 15.51 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 02:51:34 PM PDT 24
Peak memory 202140 kb
Host smart-91cf9e96-8832-4e0a-80c4-3db56f7b2991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248932126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4248932126
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.153908026
Short name T314
Test name
Test status
Simulation time 450168462605 ps
CPU time 575.82 seconds
Started May 05 02:51:17 PM PDT 24
Finished May 05 03:00:54 PM PDT 24
Peak memory 210864 kb
Host smart-a260d351-09c4-4a0e-9c52-3e1334110206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153908026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.153908026
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.839082155
Short name T628
Test name
Test status
Simulation time 61227944380 ps
CPU time 148.31 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 02:53:47 PM PDT 24
Peak memory 219212 kb
Host smart-916dd992-3746-4228-9b5a-d1108c1056b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839082155 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.839082155
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2352044481
Short name T675
Test name
Test status
Simulation time 493115690 ps
CPU time 0.91 seconds
Started May 05 02:53:14 PM PDT 24
Finished May 05 02:53:15 PM PDT 24
Peak memory 201964 kb
Host smart-0dd354a1-0160-4355-bfae-1486198fc5ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352044481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2352044481
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.885690686
Short name T331
Test name
Test status
Simulation time 361513780334 ps
CPU time 400.72 seconds
Started May 05 02:53:17 PM PDT 24
Finished May 05 02:59:59 PM PDT 24
Peak memory 202392 kb
Host smart-dacf8d34-68b9-4b70-bfdf-c92a04f27bab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885690686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.885690686
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2030802475
Short name T310
Test name
Test status
Simulation time 163386705354 ps
CPU time 377.84 seconds
Started May 05 02:53:12 PM PDT 24
Finished May 05 02:59:30 PM PDT 24
Peak memory 202308 kb
Host smart-324a0e4d-74fa-42c0-aefc-bf0ff6483165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030802475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2030802475
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1917117254
Short name T363
Test name
Test status
Simulation time 488043347971 ps
CPU time 1137.92 seconds
Started May 05 02:53:11 PM PDT 24
Finished May 05 03:12:10 PM PDT 24
Peak memory 202384 kb
Host smart-d892c600-1607-4929-b1f0-992dc912649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917117254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1917117254
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2782283323
Short name T710
Test name
Test status
Simulation time 167901849504 ps
CPU time 189.98 seconds
Started May 05 02:53:14 PM PDT 24
Finished May 05 02:56:24 PM PDT 24
Peak memory 202300 kb
Host smart-b7da6de7-0af5-4ee1-a0d2-a596f6ab766c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782283323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2782283323
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3082480367
Short name T726
Test name
Test status
Simulation time 169444987620 ps
CPU time 367.39 seconds
Started May 05 02:53:10 PM PDT 24
Finished May 05 02:59:18 PM PDT 24
Peak memory 202336 kb
Host smart-9ec66c07-b088-424e-833a-70c13e1d1f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082480367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3082480367
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1542381029
Short name T430
Test name
Test status
Simulation time 162213104597 ps
CPU time 268.48 seconds
Started May 05 02:53:10 PM PDT 24
Finished May 05 02:57:39 PM PDT 24
Peak memory 202292 kb
Host smart-54e357b9-200a-448b-83e1-a9b9f1b6bbda
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542381029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1542381029
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2867687690
Short name T349
Test name
Test status
Simulation time 206767581541 ps
CPU time 123.24 seconds
Started May 05 02:53:14 PM PDT 24
Finished May 05 02:55:18 PM PDT 24
Peak memory 202280 kb
Host smart-518f81ab-66b9-4b53-97a6-2ab170047104
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867687690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2867687690
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.4237786527
Short name T509
Test name
Test status
Simulation time 402290071416 ps
CPU time 334.86 seconds
Started May 05 02:53:17 PM PDT 24
Finished May 05 02:58:53 PM PDT 24
Peak memory 202304 kb
Host smart-830e687a-4108-4de1-a5ed-023e6fd9adbd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237786527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.4237786527
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3761603029
Short name T233
Test name
Test status
Simulation time 113543171357 ps
CPU time 576.25 seconds
Started May 05 02:53:12 PM PDT 24
Finished May 05 03:02:49 PM PDT 24
Peak memory 202636 kb
Host smart-16628b91-23fe-4a63-8819-58e89792bd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761603029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3761603029
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3547859099
Short name T468
Test name
Test status
Simulation time 23214085239 ps
CPU time 56.43 seconds
Started May 05 02:53:14 PM PDT 24
Finished May 05 02:54:11 PM PDT 24
Peak memory 202108 kb
Host smart-610cec02-77e7-4ae7-988c-88144e039aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547859099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3547859099
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2842959618
Short name T383
Test name
Test status
Simulation time 4335442678 ps
CPU time 11.98 seconds
Started May 05 02:53:13 PM PDT 24
Finished May 05 02:53:25 PM PDT 24
Peak memory 202108 kb
Host smart-4fd69b55-cf88-434b-8f9b-3fd3e2026855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842959618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2842959618
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3056272121
Short name T578
Test name
Test status
Simulation time 5947431235 ps
CPU time 8.17 seconds
Started May 05 02:53:10 PM PDT 24
Finished May 05 02:53:19 PM PDT 24
Peak memory 202048 kb
Host smart-5e65ceb3-81f2-4bdb-a862-91067528357f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056272121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3056272121
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2162969135
Short name T297
Test name
Test status
Simulation time 51983289890 ps
CPU time 183.11 seconds
Started May 05 02:53:15 PM PDT 24
Finished May 05 02:56:19 PM PDT 24
Peak memory 210956 kb
Host smart-9c3aeff7-51e2-4228-9e93-779d114217d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162969135 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2162969135
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3875266498
Short name T663
Test name
Test status
Simulation time 511830379 ps
CPU time 1.85 seconds
Started May 05 02:53:22 PM PDT 24
Finished May 05 02:53:25 PM PDT 24
Peak memory 202016 kb
Host smart-2c84bd84-e6bc-4027-b39d-cf5ac7e52fdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875266498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3875266498
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.762030314
Short name T272
Test name
Test status
Simulation time 161728197923 ps
CPU time 186.69 seconds
Started May 05 02:53:16 PM PDT 24
Finished May 05 02:56:23 PM PDT 24
Peak memory 202392 kb
Host smart-1d23ddb8-ca2c-48b7-80fd-43d883e07523
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762030314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.762030314
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.750751799
Short name T479
Test name
Test status
Simulation time 164607560455 ps
CPU time 98.82 seconds
Started May 05 02:53:18 PM PDT 24
Finished May 05 02:54:57 PM PDT 24
Peak memory 202208 kb
Host smart-64b8f4c7-11d0-4e06-bf2b-1f1e78256688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750751799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.750751799
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.488461006
Short name T284
Test name
Test status
Simulation time 163059337423 ps
CPU time 62.83 seconds
Started May 05 02:53:16 PM PDT 24
Finished May 05 02:54:19 PM PDT 24
Peak memory 202380 kb
Host smart-33cef694-08c3-4559-ad75-52cd19f20388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488461006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.488461006
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3071895194
Short name T407
Test name
Test status
Simulation time 492513560979 ps
CPU time 1073.32 seconds
Started May 05 02:53:17 PM PDT 24
Finished May 05 03:11:11 PM PDT 24
Peak memory 202304 kb
Host smart-00f1e153-c975-4a2b-af98-f16de1dab4bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071895194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3071895194
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1708170779
Short name T12
Test name
Test status
Simulation time 495559922929 ps
CPU time 302.07 seconds
Started May 05 02:53:16 PM PDT 24
Finished May 05 02:58:18 PM PDT 24
Peak memory 202300 kb
Host smart-0dfb374f-edfa-4130-a315-f9c6a077f44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708170779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1708170779
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3160450518
Short name T391
Test name
Test status
Simulation time 163140016457 ps
CPU time 191.98 seconds
Started May 05 02:53:18 PM PDT 24
Finished May 05 02:56:30 PM PDT 24
Peak memory 202328 kb
Host smart-0d7cf3f1-a4a1-46fe-b161-5995cc26ec58
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160450518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3160450518
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.637861317
Short name T198
Test name
Test status
Simulation time 603079753619 ps
CPU time 76.06 seconds
Started May 05 02:53:18 PM PDT 24
Finished May 05 02:54:34 PM PDT 24
Peak memory 202324 kb
Host smart-a9451a8a-23de-4610-8bae-2e6358622be7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637861317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.637861317
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2998231141
Short name T594
Test name
Test status
Simulation time 607307037225 ps
CPU time 1376.2 seconds
Started May 05 02:53:18 PM PDT 24
Finished May 05 03:16:15 PM PDT 24
Peak memory 202316 kb
Host smart-af3ad2d2-e1fe-456b-9f0f-4b8c4497ec25
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998231141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2998231141
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3974577121
Short name T57
Test name
Test status
Simulation time 116504819884 ps
CPU time 410.7 seconds
Started May 05 02:53:21 PM PDT 24
Finished May 05 03:00:13 PM PDT 24
Peak memory 202732 kb
Host smart-e45e5525-a038-4183-89bb-33495bae046d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974577121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3974577121
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3050001983
Short name T447
Test name
Test status
Simulation time 41103232688 ps
CPU time 88.92 seconds
Started May 05 02:53:21 PM PDT 24
Finished May 05 02:54:50 PM PDT 24
Peak memory 202136 kb
Host smart-e30db24b-a27e-40ae-9886-da8a0ad7dbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050001983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3050001983
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.837278790
Short name T620
Test name
Test status
Simulation time 3705380232 ps
CPU time 2.81 seconds
Started May 05 02:53:20 PM PDT 24
Finished May 05 02:53:23 PM PDT 24
Peak memory 202092 kb
Host smart-3dc8f433-924f-42c8-82f2-fe3b9d70f29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837278790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.837278790
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2953477838
Short name T428
Test name
Test status
Simulation time 5778740039 ps
CPU time 7.76 seconds
Started May 05 02:53:16 PM PDT 24
Finished May 05 02:53:24 PM PDT 24
Peak memory 202080 kb
Host smart-7a76a238-7671-4063-b9e4-4f0fb2a2eb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953477838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2953477838
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.4186947617
Short name T261
Test name
Test status
Simulation time 347289799722 ps
CPU time 223.92 seconds
Started May 05 02:53:22 PM PDT 24
Finished May 05 02:57:07 PM PDT 24
Peak memory 202288 kb
Host smart-9c2fc851-3b19-4f97-9e5b-1db6e5d6f73c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186947617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.4186947617
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3466772553
Short name T26
Test name
Test status
Simulation time 18757366383 ps
CPU time 35.82 seconds
Started May 05 02:53:20 PM PDT 24
Finished May 05 02:53:56 PM PDT 24
Peak memory 202412 kb
Host smart-4f90e2ea-d589-4415-ab75-b37646b858d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466772553 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3466772553
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3000795299
Short name T492
Test name
Test status
Simulation time 471549789 ps
CPU time 1.7 seconds
Started May 05 02:53:31 PM PDT 24
Finished May 05 02:53:34 PM PDT 24
Peak memory 202008 kb
Host smart-6d7b2ad9-85d7-4d0c-9441-1ba93cbcdcaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000795299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3000795299
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.708091260
Short name T268
Test name
Test status
Simulation time 350167593524 ps
CPU time 366.12 seconds
Started May 05 02:53:27 PM PDT 24
Finished May 05 02:59:33 PM PDT 24
Peak memory 202320 kb
Host smart-c2d0c7e0-1361-42bc-b658-42e31c2f7f37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708091260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.708091260
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2031211687
Short name T360
Test name
Test status
Simulation time 577482424611 ps
CPU time 1337.64 seconds
Started May 05 02:53:27 PM PDT 24
Finished May 05 03:15:45 PM PDT 24
Peak memory 202252 kb
Host smart-268fec97-4a0c-48d8-b2b9-a9567e53ed93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031211687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2031211687
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.4035406644
Short name T293
Test name
Test status
Simulation time 493438952959 ps
CPU time 293.84 seconds
Started May 05 02:53:20 PM PDT 24
Finished May 05 02:58:15 PM PDT 24
Peak memory 202348 kb
Host smart-d2435434-b2da-40ad-8ea0-808158876abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035406644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.4035406644
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.527260429
Short name T158
Test name
Test status
Simulation time 166236298901 ps
CPU time 100.34 seconds
Started May 05 02:53:28 PM PDT 24
Finished May 05 02:55:08 PM PDT 24
Peak memory 202268 kb
Host smart-045f1ede-4f41-4d54-9595-08351695c676
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=527260429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.527260429
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3708945407
Short name T419
Test name
Test status
Simulation time 329774188207 ps
CPU time 795.18 seconds
Started May 05 02:53:22 PM PDT 24
Finished May 05 03:06:38 PM PDT 24
Peak memory 202292 kb
Host smart-f4d83600-12b4-4d98-8b98-c53210fb62c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708945407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3708945407
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1591705852
Short name T776
Test name
Test status
Simulation time 609563490563 ps
CPU time 1264.26 seconds
Started May 05 02:53:26 PM PDT 24
Finished May 05 03:14:30 PM PDT 24
Peak memory 202228 kb
Host smart-a81e5a7d-8c48-4db4-aaec-74e1eed31ebe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591705852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1591705852
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1742469543
Short name T700
Test name
Test status
Simulation time 23199344590 ps
CPU time 11.87 seconds
Started May 05 02:53:38 PM PDT 24
Finished May 05 02:53:50 PM PDT 24
Peak memory 202132 kb
Host smart-f7a368bb-cd65-44c0-aac8-477cb8c53f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742469543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1742469543
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.808063691
Short name T403
Test name
Test status
Simulation time 3507290949 ps
CPU time 10.07 seconds
Started May 05 02:53:27 PM PDT 24
Finished May 05 02:53:37 PM PDT 24
Peak memory 202096 kb
Host smart-884f44a6-87c9-4b93-a002-65f71caad11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808063691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.808063691
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2928035854
Short name T517
Test name
Test status
Simulation time 5544249424 ps
CPU time 11.89 seconds
Started May 05 02:53:20 PM PDT 24
Finished May 05 02:53:32 PM PDT 24
Peak memory 202144 kb
Host smart-ab7dfe13-3bf4-41d2-8ef7-788159e4c2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928035854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2928035854
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1978577515
Short name T36
Test name
Test status
Simulation time 191869856384 ps
CPU time 36.33 seconds
Started May 05 02:53:37 PM PDT 24
Finished May 05 02:54:14 PM PDT 24
Peak memory 202296 kb
Host smart-3cc47adc-5128-4851-98dd-b42f7c381c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978577515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1978577515
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3217862081
Short name T49
Test name
Test status
Simulation time 65558812401 ps
CPU time 146.4 seconds
Started May 05 02:53:32 PM PDT 24
Finished May 05 02:55:58 PM PDT 24
Peak memory 210688 kb
Host smart-ed259e1d-be74-4929-98cf-88b9c37b1b2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217862081 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3217862081
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3851330298
Short name T564
Test name
Test status
Simulation time 447503732 ps
CPU time 1.68 seconds
Started May 05 02:53:39 PM PDT 24
Finished May 05 02:53:41 PM PDT 24
Peak memory 201996 kb
Host smart-1b9713f9-07f7-4854-a8b7-0a082195d1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851330298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3851330298
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.23667167
Short name T210
Test name
Test status
Simulation time 367835049351 ps
CPU time 222.23 seconds
Started May 05 02:53:34 PM PDT 24
Finished May 05 02:57:17 PM PDT 24
Peak memory 202260 kb
Host smart-9ca8b7ca-f8c2-49a8-8705-944c99cd6609
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23667167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gatin
g.23667167
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3372000933
Short name T581
Test name
Test status
Simulation time 370388414972 ps
CPU time 841.41 seconds
Started May 05 02:53:36 PM PDT 24
Finished May 05 03:07:38 PM PDT 24
Peak memory 202292 kb
Host smart-9c053d72-1c80-4dff-8b61-1dc0795d620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372000933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3372000933
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2189725215
Short name T794
Test name
Test status
Simulation time 330529255492 ps
CPU time 406.68 seconds
Started May 05 02:53:39 PM PDT 24
Finished May 05 03:00:26 PM PDT 24
Peak memory 202296 kb
Host smart-660149c8-c35d-4a48-b67b-63b08d44d17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189725215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2189725215
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3414321299
Short name T668
Test name
Test status
Simulation time 166084747548 ps
CPU time 372.85 seconds
Started May 05 02:53:35 PM PDT 24
Finished May 05 02:59:48 PM PDT 24
Peak memory 202288 kb
Host smart-d3fc722d-5b3c-488d-a69f-c7401b1eff7d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414321299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3414321299
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3316440534
Short name T619
Test name
Test status
Simulation time 164740430825 ps
CPU time 189.92 seconds
Started May 05 02:53:38 PM PDT 24
Finished May 05 02:56:48 PM PDT 24
Peak memory 202280 kb
Host smart-33ef6003-a34f-459c-a45b-e6589e94fe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316440534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3316440534
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.4021258327
Short name T378
Test name
Test status
Simulation time 486204178101 ps
CPU time 527.92 seconds
Started May 05 02:53:39 PM PDT 24
Finished May 05 03:02:27 PM PDT 24
Peak memory 202264 kb
Host smart-22beff67-489e-457f-9f92-fa91c4ac0372
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021258327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.4021258327
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1957743593
Short name T14
Test name
Test status
Simulation time 197224562101 ps
CPU time 61.62 seconds
Started May 05 02:53:34 PM PDT 24
Finished May 05 02:54:36 PM PDT 24
Peak memory 202236 kb
Host smart-cd2f1e76-8233-48e3-be94-1839a0bee2fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957743593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1957743593
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.453619179
Short name T126
Test name
Test status
Simulation time 111659438309 ps
CPU time 617.92 seconds
Started May 05 02:53:33 PM PDT 24
Finished May 05 03:03:51 PM PDT 24
Peak memory 202712 kb
Host smart-a655b4d1-cf94-4ef6-9310-f43f314c3e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453619179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.453619179
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2667176619
Short name T415
Test name
Test status
Simulation time 27516350237 ps
CPU time 60.47 seconds
Started May 05 02:53:35 PM PDT 24
Finished May 05 02:54:36 PM PDT 24
Peak memory 202152 kb
Host smart-daf6f2ad-79be-4006-ac62-e47612b7ac4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667176619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2667176619
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1236425555
Short name T484
Test name
Test status
Simulation time 5124778074 ps
CPU time 6.98 seconds
Started May 05 02:53:36 PM PDT 24
Finished May 05 02:53:44 PM PDT 24
Peak memory 202088 kb
Host smart-df0c5ca3-2565-4fb2-ae7c-9da71b8a9d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236425555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1236425555
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1932276862
Short name T720
Test name
Test status
Simulation time 5777109935 ps
CPU time 7.1 seconds
Started May 05 02:53:38 PM PDT 24
Finished May 05 02:53:45 PM PDT 24
Peak memory 202136 kb
Host smart-e6dfd8fb-323f-497e-a0b6-16e428916ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932276862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1932276862
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2818836732
Short name T791
Test name
Test status
Simulation time 157695271086 ps
CPU time 401.34 seconds
Started May 05 02:53:38 PM PDT 24
Finished May 05 03:00:20 PM PDT 24
Peak memory 211876 kb
Host smart-62fcbede-ae51-4256-9c9d-31aaf1977cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818836732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2818836732
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1775114686
Short name T176
Test name
Test status
Simulation time 233560443503 ps
CPU time 39.51 seconds
Started May 05 02:53:41 PM PDT 24
Finished May 05 02:54:20 PM PDT 24
Peak memory 211088 kb
Host smart-3827fb61-3a4d-4ed9-bb3f-b2d5d7237edf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775114686 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1775114686
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.491123753
Short name T102
Test name
Test status
Simulation time 560436844 ps
CPU time 0.79 seconds
Started May 05 02:53:56 PM PDT 24
Finished May 05 02:53:57 PM PDT 24
Peak memory 201984 kb
Host smart-73deb6a8-db62-4d4d-a135-f5213bca16cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491123753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.491123753
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2661499806
Short name T318
Test name
Test status
Simulation time 327434127072 ps
CPU time 151.69 seconds
Started May 05 02:53:49 PM PDT 24
Finished May 05 02:56:21 PM PDT 24
Peak memory 202364 kb
Host smart-5d213c90-fd76-48d5-9c85-2f3a6c4530cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661499806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2661499806
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3534929689
Short name T584
Test name
Test status
Simulation time 164674352517 ps
CPU time 373.27 seconds
Started May 05 02:53:44 PM PDT 24
Finished May 05 02:59:58 PM PDT 24
Peak memory 202276 kb
Host smart-a5624507-d9a2-4973-a07c-d639b9b05db6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534929689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3534929689
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3325561884
Short name T746
Test name
Test status
Simulation time 164747736236 ps
CPU time 207 seconds
Started May 05 02:53:43 PM PDT 24
Finished May 05 02:57:11 PM PDT 24
Peak memory 202244 kb
Host smart-855f4269-c0ee-4772-82fd-ef8d9d710db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325561884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3325561884
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.4292952481
Short name T734
Test name
Test status
Simulation time 498758658653 ps
CPU time 278.39 seconds
Started May 05 02:53:43 PM PDT 24
Finished May 05 02:58:22 PM PDT 24
Peak memory 202280 kb
Host smart-c73f7e9d-64e5-41df-8559-84c57e49f7f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292952481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.4292952481
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2310747965
Short name T676
Test name
Test status
Simulation time 690452688928 ps
CPU time 761.69 seconds
Started May 05 02:53:44 PM PDT 24
Finished May 05 03:06:26 PM PDT 24
Peak memory 202296 kb
Host smart-49e2642c-180a-4f05-ac9d-343c4bcb382d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310747965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2310747965
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4089105952
Short name T399
Test name
Test status
Simulation time 199226123793 ps
CPU time 292.68 seconds
Started May 05 02:53:49 PM PDT 24
Finished May 05 02:58:42 PM PDT 24
Peak memory 202380 kb
Host smart-31b8d396-41bd-4816-be1a-1a8f493a57ae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089105952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4089105952
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.358688261
Short name T593
Test name
Test status
Simulation time 118004294404 ps
CPU time 394.02 seconds
Started May 05 02:53:52 PM PDT 24
Finished May 05 03:00:26 PM PDT 24
Peak memory 202688 kb
Host smart-69cd7639-5a6e-4678-b21c-a187e402d0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358688261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.358688261
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3399868424
Short name T575
Test name
Test status
Simulation time 24487881977 ps
CPU time 7.73 seconds
Started May 05 02:53:51 PM PDT 24
Finished May 05 02:53:59 PM PDT 24
Peak memory 202100 kb
Host smart-47179dbf-88c4-492f-8c73-9dce0026c1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399868424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3399868424
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3750621943
Short name T105
Test name
Test status
Simulation time 2964464430 ps
CPU time 2.53 seconds
Started May 05 02:53:48 PM PDT 24
Finished May 05 02:53:51 PM PDT 24
Peak memory 202136 kb
Host smart-f89cde54-6c0e-4680-91a4-5758617e5c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750621943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3750621943
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3824401067
Short name T658
Test name
Test status
Simulation time 5922031934 ps
CPU time 14.75 seconds
Started May 05 02:53:40 PM PDT 24
Finished May 05 02:53:55 PM PDT 24
Peak memory 202132 kb
Host smart-e087b730-f254-4fb3-8193-8229e2b05073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824401067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3824401067
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3104555147
Short name T487
Test name
Test status
Simulation time 475511235 ps
CPU time 0.67 seconds
Started May 05 02:54:00 PM PDT 24
Finished May 05 02:54:01 PM PDT 24
Peak memory 202020 kb
Host smart-e3baf1c9-f36e-40e3-a20c-f40ba575ec98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104555147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3104555147
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2839405772
Short name T122
Test name
Test status
Simulation time 356064608717 ps
CPU time 135.81 seconds
Started May 05 02:53:56 PM PDT 24
Finished May 05 02:56:13 PM PDT 24
Peak memory 202216 kb
Host smart-cb5c73b0-583d-4e0d-a2e1-32b4e459e564
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839405772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2839405772
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2977697045
Short name T301
Test name
Test status
Simulation time 496421798162 ps
CPU time 1201.75 seconds
Started May 05 02:53:57 PM PDT 24
Finished May 05 03:14:00 PM PDT 24
Peak memory 202224 kb
Host smart-c108d067-bb7f-4b1a-9a83-dc14e6b6bc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977697045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2977697045
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.481170480
Short name T757
Test name
Test status
Simulation time 162400972985 ps
CPU time 406.9 seconds
Started May 05 02:53:57 PM PDT 24
Finished May 05 03:00:45 PM PDT 24
Peak memory 202252 kb
Host smart-84102c23-bcdc-484b-908e-345f699435cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=481170480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.481170480
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3228329456
Short name T561
Test name
Test status
Simulation time 165413193251 ps
CPU time 388.63 seconds
Started May 05 02:53:57 PM PDT 24
Finished May 05 03:00:26 PM PDT 24
Peak memory 202252 kb
Host smart-c7cb2c9b-4e52-44ce-a3db-a7aeced80a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228329456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3228329456
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2125763891
Short name T186
Test name
Test status
Simulation time 488754819271 ps
CPU time 219.98 seconds
Started May 05 02:53:56 PM PDT 24
Finished May 05 02:57:37 PM PDT 24
Peak memory 202256 kb
Host smart-24922ea4-9141-41dc-822f-6b4a1337817b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125763891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2125763891
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1418939148
Short name T453
Test name
Test status
Simulation time 198993806080 ps
CPU time 488.33 seconds
Started May 05 02:53:54 PM PDT 24
Finished May 05 03:02:03 PM PDT 24
Peak memory 202236 kb
Host smart-0d4c94ff-e471-4389-a9cf-e63ec396ecf2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418939148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1418939148
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.930365581
Short name T376
Test name
Test status
Simulation time 126888750256 ps
CPU time 510.27 seconds
Started May 05 02:54:00 PM PDT 24
Finished May 05 03:02:30 PM PDT 24
Peak memory 202664 kb
Host smart-da95b04c-269a-4a5b-a4da-117c73178b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930365581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.930365581
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1842791236
Short name T520
Test name
Test status
Simulation time 41467433152 ps
CPU time 102.39 seconds
Started May 05 02:54:00 PM PDT 24
Finished May 05 02:55:43 PM PDT 24
Peak memory 202104 kb
Host smart-98d4cb9e-f008-42b9-8cd2-1d206ca348fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842791236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1842791236
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.976551308
Short name T626
Test name
Test status
Simulation time 4093564251 ps
CPU time 9.97 seconds
Started May 05 02:54:00 PM PDT 24
Finished May 05 02:54:10 PM PDT 24
Peak memory 202132 kb
Host smart-5693c7ac-b07c-43fa-a97f-a649ff0a87f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976551308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.976551308
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1808384008
Short name T624
Test name
Test status
Simulation time 5719317337 ps
CPU time 7.77 seconds
Started May 05 02:53:55 PM PDT 24
Finished May 05 02:54:03 PM PDT 24
Peak memory 202124 kb
Host smart-5787927e-9bbf-441b-9565-180a29ffda31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808384008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1808384008
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3243075303
Short name T113
Test name
Test status
Simulation time 172017303625 ps
CPU time 87.46 seconds
Started May 05 02:54:01 PM PDT 24
Finished May 05 02:55:28 PM PDT 24
Peak memory 202336 kb
Host smart-e6ae1044-7913-40c4-bb17-f74577630788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243075303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3243075303
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3319533971
Short name T94
Test name
Test status
Simulation time 312443800 ps
CPU time 0.96 seconds
Started May 05 02:54:12 PM PDT 24
Finished May 05 02:54:14 PM PDT 24
Peak memory 201980 kb
Host smart-fecfc643-75c6-431b-8747-ff0ff5c766cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319533971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3319533971
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2413089577
Short name T106
Test name
Test status
Simulation time 530229209595 ps
CPU time 525.35 seconds
Started May 05 02:54:08 PM PDT 24
Finished May 05 03:02:54 PM PDT 24
Peak memory 202276 kb
Host smart-56952b07-d439-47ef-96cf-43b2e7f242d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413089577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2413089577
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.467281149
Short name T185
Test name
Test status
Simulation time 344501612377 ps
CPU time 741.46 seconds
Started May 05 02:54:08 PM PDT 24
Finished May 05 03:06:29 PM PDT 24
Peak memory 202304 kb
Host smart-e8a2760b-235b-414b-88cf-023f6791589a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467281149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.467281149
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3741872037
Short name T498
Test name
Test status
Simulation time 164180047285 ps
CPU time 103.51 seconds
Started May 05 02:54:05 PM PDT 24
Finished May 05 02:55:49 PM PDT 24
Peak memory 202272 kb
Host smart-a4f80d03-b68c-4168-8713-cbc9db7fb779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741872037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3741872037
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2861607704
Short name T495
Test name
Test status
Simulation time 168324840260 ps
CPU time 59.15 seconds
Started May 05 02:54:05 PM PDT 24
Finished May 05 02:55:04 PM PDT 24
Peak memory 202292 kb
Host smart-583d8c1e-28d3-4fd1-8fa4-4e9b7c5f6815
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861607704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2861607704
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.662922662
Short name T662
Test name
Test status
Simulation time 491423384437 ps
CPU time 307.36 seconds
Started May 05 02:54:05 PM PDT 24
Finished May 05 02:59:13 PM PDT 24
Peak memory 202324 kb
Host smart-290568cb-3a83-44f3-88f4-fb45e79777b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662922662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.662922662
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2008240615
Short name T773
Test name
Test status
Simulation time 166733533109 ps
CPU time 99.83 seconds
Started May 05 02:54:05 PM PDT 24
Finished May 05 02:55:45 PM PDT 24
Peak memory 202288 kb
Host smart-52379cd2-2773-48a3-b235-0ad512f58fb1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008240615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2008240615
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3029122436
Short name T149
Test name
Test status
Simulation time 568326080211 ps
CPU time 689.01 seconds
Started May 05 02:54:05 PM PDT 24
Finished May 05 03:05:34 PM PDT 24
Peak memory 202400 kb
Host smart-8d635111-9275-4f73-a4b6-2bf9d1bebe75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029122436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3029122436
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2539111403
Short name T42
Test name
Test status
Simulation time 194708946007 ps
CPU time 239.43 seconds
Started May 05 02:54:05 PM PDT 24
Finished May 05 02:58:05 PM PDT 24
Peak memory 202364 kb
Host smart-33c3d037-b5ba-4140-ab4b-8e87efdebf4c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539111403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2539111403
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2762832560
Short name T692
Test name
Test status
Simulation time 113639609764 ps
CPU time 401.47 seconds
Started May 05 02:54:08 PM PDT 24
Finished May 05 03:00:50 PM PDT 24
Peak memory 202724 kb
Host smart-ace4e024-e4ca-43bc-9855-95e6a037639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762832560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2762832560
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3810404444
Short name T750
Test name
Test status
Simulation time 31875168425 ps
CPU time 17.16 seconds
Started May 05 02:54:09 PM PDT 24
Finished May 05 02:54:27 PM PDT 24
Peak memory 202144 kb
Host smart-d93170e3-fa97-4b3e-8bcd-f6da53d0dbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810404444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3810404444
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2728853793
Short name T218
Test name
Test status
Simulation time 5091553909 ps
CPU time 3.57 seconds
Started May 05 02:54:09 PM PDT 24
Finished May 05 02:54:13 PM PDT 24
Peak memory 202136 kb
Host smart-aacda9ab-5038-4bfb-8ad1-6115ac4e1671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728853793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2728853793
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3129129489
Short name T510
Test name
Test status
Simulation time 5667664088 ps
CPU time 3.91 seconds
Started May 05 02:53:59 PM PDT 24
Finished May 05 02:54:03 PM PDT 24
Peak memory 202088 kb
Host smart-4997f40a-4000-400b-8b65-b177fba01762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129129489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3129129489
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1998603613
Short name T457
Test name
Test status
Simulation time 300389742396 ps
CPU time 1091.46 seconds
Started May 05 02:54:15 PM PDT 24
Finished May 05 03:12:27 PM PDT 24
Peak memory 202616 kb
Host smart-79263827-1401-491d-ba07-e3e63daecfc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998603613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1998603613
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2523554604
Short name T387
Test name
Test status
Simulation time 473716952 ps
CPU time 0.83 seconds
Started May 05 02:54:27 PM PDT 24
Finished May 05 02:54:28 PM PDT 24
Peak memory 201996 kb
Host smart-ab454a31-42c0-4aac-9da7-e7f7d18cbd05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523554604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2523554604
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2751619841
Short name T93
Test name
Test status
Simulation time 333139662420 ps
CPU time 407.44 seconds
Started May 05 02:54:19 PM PDT 24
Finished May 05 03:01:07 PM PDT 24
Peak memory 202296 kb
Host smart-24791ab7-a9c5-470c-8338-703d7c916dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751619841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2751619841
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.4211422881
Short name T574
Test name
Test status
Simulation time 494657063699 ps
CPU time 296.95 seconds
Started May 05 02:54:19 PM PDT 24
Finished May 05 02:59:17 PM PDT 24
Peak memory 202244 kb
Host smart-5a3ce5a1-2b33-4441-8376-24a8d6fe8f2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211422881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.4211422881
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1307329464
Short name T121
Test name
Test status
Simulation time 161809743271 ps
CPU time 365.66 seconds
Started May 05 02:54:18 PM PDT 24
Finished May 05 03:00:24 PM PDT 24
Peak memory 202308 kb
Host smart-cd87943a-12d2-4427-8aeb-33c6d5d39d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307329464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1307329464
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.688748710
Short name T635
Test name
Test status
Simulation time 321720857713 ps
CPU time 746.55 seconds
Started May 05 02:54:17 PM PDT 24
Finished May 05 03:06:44 PM PDT 24
Peak memory 202288 kb
Host smart-35b6797b-1494-40fc-aad8-cdc6a47a3f3d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=688748710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.688748710
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.4020468298
Short name T45
Test name
Test status
Simulation time 174161116134 ps
CPU time 416.48 seconds
Started May 05 02:54:17 PM PDT 24
Finished May 05 03:01:14 PM PDT 24
Peak memory 202296 kb
Host smart-33962fad-59ae-4e99-93fd-efa373d6f828
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020468298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.4020468298
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2035510691
Short name T417
Test name
Test status
Simulation time 602776456786 ps
CPU time 365.55 seconds
Started May 05 02:54:17 PM PDT 24
Finished May 05 03:00:23 PM PDT 24
Peak memory 202300 kb
Host smart-5f5dc961-35da-4da4-9f93-c734889a96e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035510691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2035510691
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3618401278
Short name T88
Test name
Test status
Simulation time 94316393160 ps
CPU time 347.32 seconds
Started May 05 02:54:22 PM PDT 24
Finished May 05 03:00:10 PM PDT 24
Peak memory 202608 kb
Host smart-358ba588-8120-4c9f-b962-1fade08e0856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618401278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3618401278
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3158742354
Short name T480
Test name
Test status
Simulation time 41928175776 ps
CPU time 25.29 seconds
Started May 05 02:54:21 PM PDT 24
Finished May 05 02:54:47 PM PDT 24
Peak memory 202120 kb
Host smart-71f7f948-24f8-4bbc-85b6-cdf7c219b963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158742354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3158742354
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.675345290
Short name T440
Test name
Test status
Simulation time 5526975276 ps
CPU time 4.32 seconds
Started May 05 02:54:20 PM PDT 24
Finished May 05 02:54:25 PM PDT 24
Peak memory 202068 kb
Host smart-b71d954c-7943-43a9-8277-109c77831f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675345290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.675345290
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.4210620502
Short name T188
Test name
Test status
Simulation time 5821031582 ps
CPU time 3.69 seconds
Started May 05 02:54:12 PM PDT 24
Finished May 05 02:54:16 PM PDT 24
Peak memory 202064 kb
Host smart-0b26ef61-3e19-4d3e-9ce1-fd7e599bdc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210620502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.4210620502
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3816766208
Short name T775
Test name
Test status
Simulation time 224219910629 ps
CPU time 140.18 seconds
Started May 05 02:54:21 PM PDT 24
Finished May 05 02:56:42 PM PDT 24
Peak memory 202376 kb
Host smart-cd0f502d-1c9b-48ca-8beb-3c45d7584f92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816766208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3816766208
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3713564864
Short name T704
Test name
Test status
Simulation time 389168471 ps
CPU time 1.08 seconds
Started May 05 02:54:44 PM PDT 24
Finished May 05 02:54:46 PM PDT 24
Peak memory 201984 kb
Host smart-3781760f-d86a-45aa-945d-0a484a16476b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713564864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3713564864
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1970412060
Short name T283
Test name
Test status
Simulation time 560152667523 ps
CPU time 759.13 seconds
Started May 05 02:54:35 PM PDT 24
Finished May 05 03:07:14 PM PDT 24
Peak memory 202360 kb
Host smart-2a6e3b16-d2d2-4fa1-8af3-d882f772c44b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970412060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1970412060
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.285263942
Short name T348
Test name
Test status
Simulation time 331786140431 ps
CPU time 416.61 seconds
Started May 05 02:54:34 PM PDT 24
Finished May 05 03:01:31 PM PDT 24
Peak memory 202304 kb
Host smart-80f499a9-2cc3-41a6-a1c3-1c9b4790a8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285263942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.285263942
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3352261643
Short name T209
Test name
Test status
Simulation time 325161456242 ps
CPU time 812.33 seconds
Started May 05 02:54:30 PM PDT 24
Finished May 05 03:08:02 PM PDT 24
Peak memory 202360 kb
Host smart-2d052663-a268-4d77-ba90-2908c31ea6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352261643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3352261643
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1075934646
Short name T728
Test name
Test status
Simulation time 498899477356 ps
CPU time 112.89 seconds
Started May 05 02:54:37 PM PDT 24
Finished May 05 02:56:30 PM PDT 24
Peak memory 202228 kb
Host smart-5b1700ad-a6b5-4a3d-8b0d-982aa0b29db8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075934646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1075934646
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3032674542
Short name T29
Test name
Test status
Simulation time 330863403550 ps
CPU time 716.92 seconds
Started May 05 02:54:29 PM PDT 24
Finished May 05 03:06:27 PM PDT 24
Peak memory 202364 kb
Host smart-252f59e6-ce72-4ca4-b793-e1ba26faf808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032674542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3032674542
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.55594376
Short name T461
Test name
Test status
Simulation time 495409075037 ps
CPU time 1117.12 seconds
Started May 05 02:54:30 PM PDT 24
Finished May 05 03:13:08 PM PDT 24
Peak memory 202316 kb
Host smart-856b3aa5-dfd5-40d3-9f6d-77a947ded8a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=55594376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed
.55594376
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.150067111
Short name T529
Test name
Test status
Simulation time 192757135926 ps
CPU time 487.68 seconds
Started May 05 02:54:34 PM PDT 24
Finished May 05 03:02:42 PM PDT 24
Peak memory 202308 kb
Host smart-83163d4d-c184-4377-a3a6-4adc917595a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150067111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.150067111
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3957538491
Short name T566
Test name
Test status
Simulation time 594930618972 ps
CPU time 311.17 seconds
Started May 05 02:54:35 PM PDT 24
Finished May 05 02:59:46 PM PDT 24
Peak memory 202308 kb
Host smart-3fa7d65a-3d80-4f68-88f6-409067cea041
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957538491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3957538491
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1876495321
Short name T725
Test name
Test status
Simulation time 120296787137 ps
CPU time 676.17 seconds
Started May 05 02:54:38 PM PDT 24
Finished May 05 03:05:54 PM PDT 24
Peak memory 202656 kb
Host smart-8a95951a-246b-4633-ab6e-216dc77a301c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876495321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1876495321
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3169886745
Short name T552
Test name
Test status
Simulation time 31134354460 ps
CPU time 7.41 seconds
Started May 05 02:54:36 PM PDT 24
Finished May 05 02:54:44 PM PDT 24
Peak memory 202132 kb
Host smart-432d61ad-0fcf-442b-a046-d84efde9559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169886745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3169886745
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.819685244
Short name T596
Test name
Test status
Simulation time 4865885799 ps
CPU time 6.93 seconds
Started May 05 02:54:36 PM PDT 24
Finished May 05 02:54:43 PM PDT 24
Peak memory 202116 kb
Host smart-6e5d648f-56db-4827-9953-e54f1a995ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819685244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.819685244
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.949278342
Short name T622
Test name
Test status
Simulation time 6082238295 ps
CPU time 15.12 seconds
Started May 05 02:54:25 PM PDT 24
Finished May 05 02:54:41 PM PDT 24
Peak memory 202148 kb
Host smart-f7c9a688-4016-4592-9735-2e19ec02c2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949278342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.949278342
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3294043303
Short name T345
Test name
Test status
Simulation time 500770625728 ps
CPU time 1521.71 seconds
Started May 05 02:54:44 PM PDT 24
Finished May 05 03:20:06 PM PDT 24
Peak memory 202708 kb
Host smart-10937355-687f-4146-8800-ca84fed45497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294043303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3294043303
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.4294845233
Short name T19
Test name
Test status
Simulation time 16611996890 ps
CPU time 46.45 seconds
Started May 05 02:54:44 PM PDT 24
Finished May 05 02:55:31 PM PDT 24
Peak memory 210920 kb
Host smart-a01fa3ac-4a21-4ed8-a037-055e2cdf6e38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294845233 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.4294845233
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4113062721
Short name T541
Test name
Test status
Simulation time 329106979 ps
CPU time 0.76 seconds
Started May 05 02:55:01 PM PDT 24
Finished May 05 02:55:02 PM PDT 24
Peak memory 202012 kb
Host smart-778398b4-7a2f-4f31-ad79-b45a3b1210b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113062721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4113062721
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3576864510
Short name T328
Test name
Test status
Simulation time 505132508824 ps
CPU time 588.44 seconds
Started May 05 02:54:52 PM PDT 24
Finished May 05 03:04:41 PM PDT 24
Peak memory 202324 kb
Host smart-b3d7b65c-d610-48a3-a8af-5343f468be49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576864510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3576864510
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.4147781709
Short name T549
Test name
Test status
Simulation time 166951807549 ps
CPU time 381.75 seconds
Started May 05 02:54:49 PM PDT 24
Finished May 05 03:01:11 PM PDT 24
Peak memory 202280 kb
Host smart-1fe8a862-b639-4245-a5ea-cc96908a57e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147781709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4147781709
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1703600822
Short name T204
Test name
Test status
Simulation time 159869582028 ps
CPU time 367.8 seconds
Started May 05 02:54:54 PM PDT 24
Finished May 05 03:01:02 PM PDT 24
Peak memory 202252 kb
Host smart-a6f8fbdf-1147-490a-b930-2b28d85aa9f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703600822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1703600822
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2756394842
Short name T530
Test name
Test status
Simulation time 490435086917 ps
CPU time 1057.74 seconds
Started May 05 02:54:47 PM PDT 24
Finished May 05 03:12:25 PM PDT 24
Peak memory 202304 kb
Host smart-e304bc57-cc6a-4c0e-9cd7-3735662603cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756394842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2756394842
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3074620026
Short name T413
Test name
Test status
Simulation time 493390727484 ps
CPU time 314.45 seconds
Started May 05 02:54:47 PM PDT 24
Finished May 05 03:00:02 PM PDT 24
Peak memory 202244 kb
Host smart-7be64ba0-0790-436d-bc92-99bd0b58c011
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074620026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3074620026
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2514659604
Short name T755
Test name
Test status
Simulation time 181270913139 ps
CPU time 441.1 seconds
Started May 05 02:54:53 PM PDT 24
Finished May 05 03:02:15 PM PDT 24
Peak memory 202304 kb
Host smart-029f08bd-7536-4f26-b972-366af027883a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514659604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2514659604
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.4286427314
Short name T525
Test name
Test status
Simulation time 589289634973 ps
CPU time 1287.53 seconds
Started May 05 02:54:53 PM PDT 24
Finished May 05 03:16:21 PM PDT 24
Peak memory 202304 kb
Host smart-bea0725e-e5a4-4ee4-8818-6db8f74cbdb7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286427314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.4286427314
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2077800307
Short name T232
Test name
Test status
Simulation time 82094101818 ps
CPU time 242.78 seconds
Started May 05 02:54:57 PM PDT 24
Finished May 05 02:59:00 PM PDT 24
Peak memory 202720 kb
Host smart-8c5fc464-f8c2-4591-bf7c-429df2548a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077800307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2077800307
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.824112572
Short name T652
Test name
Test status
Simulation time 24264145035 ps
CPU time 15.02 seconds
Started May 05 02:54:52 PM PDT 24
Finished May 05 02:55:08 PM PDT 24
Peak memory 202108 kb
Host smart-205eb878-29ee-41f9-9bb5-d0029f6a8db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824112572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.824112572
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2281285705
Short name T148
Test name
Test status
Simulation time 5432888816 ps
CPU time 3.57 seconds
Started May 05 02:54:52 PM PDT 24
Finished May 05 02:54:56 PM PDT 24
Peak memory 202060 kb
Host smart-52df54fa-ffbc-443a-ab26-883aef379656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281285705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2281285705
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2913988855
Short name T689
Test name
Test status
Simulation time 5901555773 ps
CPU time 7.82 seconds
Started May 05 02:54:47 PM PDT 24
Finished May 05 02:54:55 PM PDT 24
Peak memory 202124 kb
Host smart-08913cb1-078b-417a-b2b1-9f60a8f05127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913988855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2913988855
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1240306837
Short name T296
Test name
Test status
Simulation time 562115180945 ps
CPU time 1335.07 seconds
Started May 05 02:55:02 PM PDT 24
Finished May 05 03:17:18 PM PDT 24
Peak memory 210780 kb
Host smart-daefa587-978c-4726-8e4d-e3fa6dd7fcfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240306837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1240306837
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1862090712
Short name T194
Test name
Test status
Simulation time 206074907008 ps
CPU time 201.85 seconds
Started May 05 02:54:56 PM PDT 24
Finished May 05 02:58:18 PM PDT 24
Peak memory 211048 kb
Host smart-5526af4f-c5af-4b60-b2bf-a1d01615cd80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862090712 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1862090712
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1101771915
Short name T112
Test name
Test status
Simulation time 357358135 ps
CPU time 0.71 seconds
Started May 05 02:51:23 PM PDT 24
Finished May 05 02:51:24 PM PDT 24
Peak memory 201988 kb
Host smart-2dc5cf0f-2abf-4c14-8719-5491cfd0480b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101771915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1101771915
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3007257692
Short name T286
Test name
Test status
Simulation time 164552136140 ps
CPU time 89.57 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 02:52:48 PM PDT 24
Peak memory 202388 kb
Host smart-4f2f07c6-c277-4cbb-a5d9-7b2aa9c6f0e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007257692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3007257692
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.4264673170
Short name T754
Test name
Test status
Simulation time 339460846435 ps
CPU time 778.3 seconds
Started May 05 02:51:16 PM PDT 24
Finished May 05 03:04:16 PM PDT 24
Peak memory 202268 kb
Host smart-b0d3dbf8-506a-4925-a68c-0e14bfb426d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264673170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.4264673170
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1437826612
Short name T311
Test name
Test status
Simulation time 327581181423 ps
CPU time 191.03 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 02:54:30 PM PDT 24
Peak memory 202300 kb
Host smart-875ade90-ba91-47ed-a113-95a51c7121b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437826612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1437826612
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.153550268
Short name T518
Test name
Test status
Simulation time 495320232374 ps
CPU time 264.85 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 02:55:43 PM PDT 24
Peak memory 202236 kb
Host smart-59f0aea8-563d-486d-9b64-b62d9dae1323
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=153550268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.153550268
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2907759673
Short name T5
Test name
Test status
Simulation time 164575650404 ps
CPU time 80.37 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 02:52:39 PM PDT 24
Peak memory 202236 kb
Host smart-c37a0030-5ad7-4980-829a-92983ed022be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907759673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2907759673
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3849520387
Short name T747
Test name
Test status
Simulation time 161636878952 ps
CPU time 106.36 seconds
Started May 05 02:51:17 PM PDT 24
Finished May 05 02:53:04 PM PDT 24
Peak memory 202308 kb
Host smart-2002906c-8c40-4e41-845b-944e2d16b636
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849520387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3849520387
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3656550112
Short name T287
Test name
Test status
Simulation time 361081731425 ps
CPU time 817.25 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 03:04:56 PM PDT 24
Peak memory 202276 kb
Host smart-ac502048-10bd-409e-99ba-796d8eef2d71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656550112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3656550112
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2947405755
Short name T216
Test name
Test status
Simulation time 194519404802 ps
CPU time 407.73 seconds
Started May 05 02:51:17 PM PDT 24
Finished May 05 02:58:06 PM PDT 24
Peak memory 202344 kb
Host smart-8dcbd858-cd7a-4019-a7db-28aea187c302
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947405755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2947405755
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1390939833
Short name T405
Test name
Test status
Simulation time 107868581715 ps
CPU time 396.28 seconds
Started May 05 02:51:17 PM PDT 24
Finished May 05 02:57:54 PM PDT 24
Peak memory 202608 kb
Host smart-6bf5dda9-2a5f-4f2f-acfd-6a7b8b5eb551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390939833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1390939833
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2919207315
Short name T119
Test name
Test status
Simulation time 28553776934 ps
CPU time 17.54 seconds
Started May 05 02:51:16 PM PDT 24
Finished May 05 02:51:35 PM PDT 24
Peak memory 202128 kb
Host smart-5d54f0a3-450e-4bec-b49c-193b229b36bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919207315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2919207315
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2305217687
Short name T722
Test name
Test status
Simulation time 4259016465 ps
CPU time 3.07 seconds
Started May 05 02:51:17 PM PDT 24
Finished May 05 02:51:21 PM PDT 24
Peak memory 202136 kb
Host smart-d4146e30-3585-4473-b797-94cd604477fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305217687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2305217687
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.251118430
Short name T500
Test name
Test status
Simulation time 5652350887 ps
CPU time 9.82 seconds
Started May 05 02:51:18 PM PDT 24
Finished May 05 02:51:28 PM PDT 24
Peak memory 202144 kb
Host smart-e859b286-24b7-4463-983b-486fcf475d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251118430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.251118430
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3469444702
Short name T326
Test name
Test status
Simulation time 331069197262 ps
CPU time 766.41 seconds
Started May 05 02:51:21 PM PDT 24
Finished May 05 03:04:08 PM PDT 24
Peak memory 202328 kb
Host smart-1252a024-56c1-4524-9b5d-969e91ab7dca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469444702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3469444702
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2511752895
Short name T108
Test name
Test status
Simulation time 8974463651 ps
CPU time 20.37 seconds
Started May 05 02:51:23 PM PDT 24
Finished May 05 02:51:43 PM PDT 24
Peak memory 202424 kb
Host smart-db28934a-cd0b-4af7-b64d-5271791e3df5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511752895 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2511752895
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1609826958
Short name T606
Test name
Test status
Simulation time 340775172 ps
CPU time 1.45 seconds
Started May 05 02:55:10 PM PDT 24
Finished May 05 02:55:12 PM PDT 24
Peak memory 202048 kb
Host smart-87049f99-88d2-4786-8307-f5bbfffc6b47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609826958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1609826958
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1734284776
Short name T260
Test name
Test status
Simulation time 366942910847 ps
CPU time 770.09 seconds
Started May 05 02:55:06 PM PDT 24
Finished May 05 03:07:57 PM PDT 24
Peak memory 202360 kb
Host smart-99b8e229-98ad-41b7-ae13-a381307f179d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734284776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1734284776
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1744382968
Short name T696
Test name
Test status
Simulation time 329803752713 ps
CPU time 780.69 seconds
Started May 05 02:55:00 PM PDT 24
Finished May 05 03:08:01 PM PDT 24
Peak memory 202304 kb
Host smart-e97731af-f892-4af4-9ae0-c398614287ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744382968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1744382968
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1944936236
Short name T653
Test name
Test status
Simulation time 156423621004 ps
CPU time 195.51 seconds
Started May 05 02:55:07 PM PDT 24
Finished May 05 02:58:23 PM PDT 24
Peak memory 202308 kb
Host smart-b07d8655-1c53-46be-98d0-f1f818c709b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944936236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1944936236
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2446029420
Short name T625
Test name
Test status
Simulation time 163226729214 ps
CPU time 183.99 seconds
Started May 05 02:55:01 PM PDT 24
Finished May 05 02:58:05 PM PDT 24
Peak memory 202232 kb
Host smart-ea73fdc8-2872-49c7-8d7d-7ad7e95bbc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446029420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2446029420
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2249784833
Short name T432
Test name
Test status
Simulation time 329742504262 ps
CPU time 810.03 seconds
Started May 05 02:55:00 PM PDT 24
Finished May 05 03:08:30 PM PDT 24
Peak memory 202252 kb
Host smart-88367296-ed4d-4f77-9427-57e11c3846fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249784833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2249784833
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.32111535
Short name T162
Test name
Test status
Simulation time 188787806188 ps
CPU time 58.36 seconds
Started May 05 02:55:04 PM PDT 24
Finished May 05 02:56:03 PM PDT 24
Peak memory 202364 kb
Host smart-36e45fae-bf23-432c-afc3-07096fc4265b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32111535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.a
dc_ctrl_filters_wakeup_fixed.32111535
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2917617652
Short name T784
Test name
Test status
Simulation time 95700437333 ps
CPU time 516.04 seconds
Started May 05 02:55:10 PM PDT 24
Finished May 05 03:03:47 PM PDT 24
Peak memory 202720 kb
Host smart-5a77734e-e63a-41e4-8f0b-38b02da8c666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917617652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2917617652
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.645615043
Short name T587
Test name
Test status
Simulation time 27486667454 ps
CPU time 66.42 seconds
Started May 05 02:55:09 PM PDT 24
Finished May 05 02:56:16 PM PDT 24
Peak memory 202116 kb
Host smart-cc712f88-629f-4e7e-9f36-6bd6528f7043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645615043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.645615043
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.4008307183
Short name T478
Test name
Test status
Simulation time 4292348092 ps
CPU time 3.22 seconds
Started May 05 02:55:10 PM PDT 24
Finished May 05 02:55:13 PM PDT 24
Peak memory 202148 kb
Host smart-84ac29e5-bb0b-4310-bb7b-5860685aa00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008307183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.4008307183
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2895652434
Short name T182
Test name
Test status
Simulation time 5832963211 ps
CPU time 13.61 seconds
Started May 05 02:55:03 PM PDT 24
Finished May 05 02:55:17 PM PDT 24
Peak memory 202064 kb
Host smart-0abedd71-bfaa-4e5f-9855-15d55fa3148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895652434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2895652434
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.4194366899
Short name T719
Test name
Test status
Simulation time 215857517940 ps
CPU time 132.37 seconds
Started May 05 02:55:10 PM PDT 24
Finished May 05 02:57:23 PM PDT 24
Peak memory 202380 kb
Host smart-86ce8521-5da5-4785-85cd-3aa34b6138b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194366899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.4194366899
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2543392999
Short name T24
Test name
Test status
Simulation time 52721503062 ps
CPU time 63.44 seconds
Started May 05 02:55:09 PM PDT 24
Finished May 05 02:56:13 PM PDT 24
Peak memory 210656 kb
Host smart-0967ef41-f8fe-4b84-93f0-6d0038ccb149
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543392999 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2543392999
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.290396894
Short name T672
Test name
Test status
Simulation time 298991826 ps
CPU time 0.95 seconds
Started May 05 02:55:29 PM PDT 24
Finished May 05 02:55:30 PM PDT 24
Peak memory 202016 kb
Host smart-aa2e7250-102f-4cf3-892d-a33d277a6834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290396894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.290396894
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1081190620
Short name T565
Test name
Test status
Simulation time 172156943578 ps
CPU time 36.34 seconds
Started May 05 02:55:19 PM PDT 24
Finished May 05 02:55:56 PM PDT 24
Peak memory 202280 kb
Host smart-7715605f-df4a-4dd3-b2d6-f7836d04075c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081190620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1081190620
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3393298337
Short name T767
Test name
Test status
Simulation time 503170475033 ps
CPU time 325.61 seconds
Started May 05 02:55:18 PM PDT 24
Finished May 05 03:00:44 PM PDT 24
Peak memory 202368 kb
Host smart-e0f5b9a6-b608-467c-82d0-d0bbb6dc3435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393298337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3393298337
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3264087980
Short name T503
Test name
Test status
Simulation time 168069471965 ps
CPU time 88.52 seconds
Started May 05 02:55:16 PM PDT 24
Finished May 05 02:56:45 PM PDT 24
Peak memory 202400 kb
Host smart-f13bd769-619d-435b-a64c-7abbed2b831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264087980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3264087980
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2291487294
Short name T459
Test name
Test status
Simulation time 163277874898 ps
CPU time 95.3 seconds
Started May 05 02:55:14 PM PDT 24
Finished May 05 02:56:50 PM PDT 24
Peak memory 202312 kb
Host smart-74f3fdfa-ce64-4b14-bd98-884a23ad9468
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291487294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2291487294
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1246008397
Short name T573
Test name
Test status
Simulation time 326512886221 ps
CPU time 800.07 seconds
Started May 05 02:55:09 PM PDT 24
Finished May 05 03:08:30 PM PDT 24
Peak memory 202212 kb
Host smart-c74554f2-e868-4efa-9af6-384eb7f6a881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246008397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1246008397
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.4209858549
Short name T189
Test name
Test status
Simulation time 486332497573 ps
CPU time 801.29 seconds
Started May 05 02:55:15 PM PDT 24
Finished May 05 03:08:37 PM PDT 24
Peak memory 202276 kb
Host smart-29849d59-e126-4e52-8606-a83cda46ab45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209858549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.4209858549
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1619722692
Short name T292
Test name
Test status
Simulation time 171026078410 ps
CPU time 95.31 seconds
Started May 05 02:55:15 PM PDT 24
Finished May 05 02:56:51 PM PDT 24
Peak memory 202312 kb
Host smart-50ee2e61-0074-4d2a-afbc-df440a50fca7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619722692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1619722692
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.144630864
Short name T545
Test name
Test status
Simulation time 201615627785 ps
CPU time 227.45 seconds
Started May 05 02:55:19 PM PDT 24
Finished May 05 02:59:07 PM PDT 24
Peak memory 202324 kb
Host smart-05a3238e-edcd-42f3-9d0f-6e1bf0316095
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144630864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.144630864
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.670112224
Short name T718
Test name
Test status
Simulation time 72074891577 ps
CPU time 421.88 seconds
Started May 05 02:55:24 PM PDT 24
Finished May 05 03:02:26 PM PDT 24
Peak memory 202640 kb
Host smart-002e41a5-e5fd-475f-a4b3-5fc62dc36444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670112224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.670112224
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1248526510
Short name T774
Test name
Test status
Simulation time 31740648856 ps
CPU time 19.25 seconds
Started May 05 02:55:23 PM PDT 24
Finished May 05 02:55:43 PM PDT 24
Peak memory 202120 kb
Host smart-d6fc54f3-1e2f-4fbe-a8ba-93611195042b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248526510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1248526510
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2415674071
Short name T727
Test name
Test status
Simulation time 3820151611 ps
CPU time 5.96 seconds
Started May 05 02:55:23 PM PDT 24
Finished May 05 02:55:29 PM PDT 24
Peak memory 202104 kb
Host smart-16bdc136-d065-4933-ae2a-c3300259d709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415674071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2415674071
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3492209226
Short name T466
Test name
Test status
Simulation time 5694380557 ps
CPU time 2.81 seconds
Started May 05 02:55:11 PM PDT 24
Finished May 05 02:55:14 PM PDT 24
Peak memory 202144 kb
Host smart-4160281d-b189-401f-bf19-964126797db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492209226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3492209226
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3489394352
Short name T721
Test name
Test status
Simulation time 22569440905 ps
CPU time 53.43 seconds
Started May 05 02:55:22 PM PDT 24
Finished May 05 02:56:16 PM PDT 24
Peak memory 210976 kb
Host smart-acf4dc16-5454-42b0-b81a-b681f6871017
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489394352 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3489394352
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1857138981
Short name T85
Test name
Test status
Simulation time 354466134 ps
CPU time 0.85 seconds
Started May 05 02:55:45 PM PDT 24
Finished May 05 02:55:46 PM PDT 24
Peak memory 201992 kb
Host smart-c363cb52-7cf1-4db0-8eb3-b6b8c34148e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857138981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1857138981
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.381363004
Short name T473
Test name
Test status
Simulation time 172765680671 ps
CPU time 14.13 seconds
Started May 05 02:55:32 PM PDT 24
Finished May 05 02:55:46 PM PDT 24
Peak memory 202224 kb
Host smart-1714f078-1d0e-4209-8a90-b129c6449cd5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381363004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.381363004
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2471247472
Short name T53
Test name
Test status
Simulation time 191601802708 ps
CPU time 197.42 seconds
Started May 05 02:55:38 PM PDT 24
Finished May 05 02:58:56 PM PDT 24
Peak memory 202296 kb
Host smart-c25c154a-1888-477f-934b-2179270c605d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471247472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2471247472
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.4042941205
Short name T323
Test name
Test status
Simulation time 169994526072 ps
CPU time 225.14 seconds
Started May 05 02:55:27 PM PDT 24
Finished May 05 02:59:13 PM PDT 24
Peak memory 202308 kb
Host smart-c42615a6-b1cf-4ba6-ac8f-7f480d5755de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042941205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.4042941205
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3566075692
Short name T223
Test name
Test status
Simulation time 325704408103 ps
CPU time 192.89 seconds
Started May 05 02:55:29 PM PDT 24
Finished May 05 02:58:42 PM PDT 24
Peak memory 202300 kb
Host smart-10730917-72bf-458c-a509-edff6cfc3e6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566075692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3566075692
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1821498783
Short name T241
Test name
Test status
Simulation time 321840715383 ps
CPU time 374.42 seconds
Started May 05 02:55:26 PM PDT 24
Finished May 05 03:01:41 PM PDT 24
Peak memory 202344 kb
Host smart-85f16c9a-e970-40ff-b68f-3045438559a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821498783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1821498783
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3779723803
Short name T197
Test name
Test status
Simulation time 498770333777 ps
CPU time 268.73 seconds
Started May 05 02:55:28 PM PDT 24
Finished May 05 02:59:57 PM PDT 24
Peak memory 202276 kb
Host smart-57fd0344-07b3-4041-b59a-0b080ce692f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779723803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3779723803
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.722358392
Short name T714
Test name
Test status
Simulation time 281372458726 ps
CPU time 167.45 seconds
Started May 05 02:55:28 PM PDT 24
Finished May 05 02:58:16 PM PDT 24
Peak memory 202332 kb
Host smart-66289dca-0db5-43d9-8248-45872d7b407c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722358392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.722358392
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1496824382
Short name T506
Test name
Test status
Simulation time 188848425331 ps
CPU time 462.45 seconds
Started May 05 02:55:32 PM PDT 24
Finished May 05 03:03:15 PM PDT 24
Peak memory 202288 kb
Host smart-664566af-ac09-400a-aae1-d188a4b7fa23
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496824382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1496824382
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3338712248
Short name T237
Test name
Test status
Simulation time 77470668787 ps
CPU time 271.56 seconds
Started May 05 02:55:35 PM PDT 24
Finished May 05 03:00:07 PM PDT 24
Peak memory 202700 kb
Host smart-3b277508-8116-4352-9741-b3640924f44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338712248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3338712248
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.908993185
Short name T160
Test name
Test status
Simulation time 24427377132 ps
CPU time 32.48 seconds
Started May 05 02:55:36 PM PDT 24
Finished May 05 02:56:09 PM PDT 24
Peak memory 202108 kb
Host smart-62f791e7-0cc1-429f-ba20-c309dd676bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908993185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.908993185
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.385316866
Short name T485
Test name
Test status
Simulation time 4391886377 ps
CPU time 1.99 seconds
Started May 05 02:55:36 PM PDT 24
Finished May 05 02:55:38 PM PDT 24
Peak memory 202044 kb
Host smart-690e3540-8435-4a91-81df-f2176e1f7769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385316866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.385316866
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2939782509
Short name T114
Test name
Test status
Simulation time 5665915554 ps
CPU time 6.62 seconds
Started May 05 02:55:27 PM PDT 24
Finished May 05 02:55:34 PM PDT 24
Peak memory 202120 kb
Host smart-6426727c-bd89-4d0c-82da-01de4901ad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939782509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2939782509
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1257348954
Short name T20
Test name
Test status
Simulation time 95281308096 ps
CPU time 22.14 seconds
Started May 05 02:55:41 PM PDT 24
Finished May 05 02:56:04 PM PDT 24
Peak memory 210652 kb
Host smart-0a2ed136-18b0-4359-a1a6-2b501235fb5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257348954 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1257348954
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.340885514
Short name T103
Test name
Test status
Simulation time 570723871 ps
CPU time 0.74 seconds
Started May 05 02:55:53 PM PDT 24
Finished May 05 02:55:54 PM PDT 24
Peak memory 201920 kb
Host smart-3711ed18-4164-4b8d-8aa4-f44d84929e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340885514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.340885514
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3838871839
Short name T295
Test name
Test status
Simulation time 249449217947 ps
CPU time 482.91 seconds
Started May 05 02:55:50 PM PDT 24
Finished May 05 03:03:53 PM PDT 24
Peak memory 202424 kb
Host smart-09760f40-cb00-4f8d-a801-4a20c3369523
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838871839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3838871839
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2613714241
Short name T740
Test name
Test status
Simulation time 286698975545 ps
CPU time 332.42 seconds
Started May 05 02:55:48 PM PDT 24
Finished May 05 03:01:21 PM PDT 24
Peak memory 202216 kb
Host smart-15ef87e1-4c02-4921-83ce-fc9fcecf6a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613714241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2613714241
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3666210935
Short name T359
Test name
Test status
Simulation time 492219864684 ps
CPU time 1130.37 seconds
Started May 05 02:55:44 PM PDT 24
Finished May 05 03:14:34 PM PDT 24
Peak memory 202360 kb
Host smart-fd974d60-84b9-41d9-987d-5125bf84f66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666210935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3666210935
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.749363022
Short name T585
Test name
Test status
Simulation time 169982275415 ps
CPU time 110.43 seconds
Started May 05 02:55:47 PM PDT 24
Finished May 05 02:57:38 PM PDT 24
Peak memory 202336 kb
Host smart-2f03c349-d166-4ac9-a25a-bf91bab78ae9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=749363022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.749363022
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3805592477
Short name T641
Test name
Test status
Simulation time 321889431602 ps
CPU time 100.98 seconds
Started May 05 02:55:45 PM PDT 24
Finished May 05 02:57:26 PM PDT 24
Peak memory 202280 kb
Host smart-751111c6-bbec-449b-9b3a-0d9ad5d149c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805592477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3805592477
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.630350700
Short name T458
Test name
Test status
Simulation time 167665518117 ps
CPU time 356.4 seconds
Started May 05 02:55:46 PM PDT 24
Finished May 05 03:01:43 PM PDT 24
Peak memory 202360 kb
Host smart-a325342b-7a68-4294-92e9-40757e355fbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=630350700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.630350700
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3964127436
Short name T513
Test name
Test status
Simulation time 179037731744 ps
CPU time 108.66 seconds
Started May 05 02:55:49 PM PDT 24
Finished May 05 02:57:38 PM PDT 24
Peak memory 202316 kb
Host smart-1db2f769-c916-4405-8bf1-763fac2d8198
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964127436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3964127436
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2848008806
Short name T409
Test name
Test status
Simulation time 391788889889 ps
CPU time 229.9 seconds
Started May 05 02:55:51 PM PDT 24
Finished May 05 02:59:41 PM PDT 24
Peak memory 202312 kb
Host smart-d2cf7db4-2954-40d7-b048-9af5003d1306
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848008806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2848008806
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3570161949
Short name T441
Test name
Test status
Simulation time 30269278687 ps
CPU time 18.54 seconds
Started May 05 02:55:53 PM PDT 24
Finished May 05 02:56:12 PM PDT 24
Peak memory 202104 kb
Host smart-dc13ddcc-8957-4ae0-815c-c2c37259ed14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570161949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3570161949
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1379190531
Short name T600
Test name
Test status
Simulation time 2847386017 ps
CPU time 4.76 seconds
Started May 05 02:55:48 PM PDT 24
Finished May 05 02:55:53 PM PDT 24
Peak memory 202132 kb
Host smart-7b7dd504-358c-43b0-bdee-6185a5b4cd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379190531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1379190531
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.106355412
Short name T443
Test name
Test status
Simulation time 6078437225 ps
CPU time 15.74 seconds
Started May 05 02:55:44 PM PDT 24
Finished May 05 02:56:00 PM PDT 24
Peak memory 202144 kb
Host smart-2cef6efb-f1de-4828-a741-ff545a12f258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106355412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.106355412
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.163534060
Short name T515
Test name
Test status
Simulation time 198671885458 ps
CPU time 127.3 seconds
Started May 05 02:55:53 PM PDT 24
Finished May 05 02:58:01 PM PDT 24
Peak memory 202292 kb
Host smart-dd4b18d6-783f-4842-a204-cb541a1c336f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163534060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
163534060
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3146023694
Short name T124
Test name
Test status
Simulation time 122849109464 ps
CPU time 123.88 seconds
Started May 05 02:55:53 PM PDT 24
Finished May 05 02:57:57 PM PDT 24
Peak memory 210980 kb
Host smart-af69ddce-c5bf-44c8-b443-e4f7aa59b4c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146023694 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3146023694
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2535914084
Short name T420
Test name
Test status
Simulation time 299621770 ps
CPU time 1.25 seconds
Started May 05 02:56:08 PM PDT 24
Finished May 05 02:56:10 PM PDT 24
Peak memory 202012 kb
Host smart-d046b2ff-7c4c-46a4-97f9-60e61d8f5eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535914084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2535914084
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2358145640
Short name T229
Test name
Test status
Simulation time 341744657057 ps
CPU time 165.7 seconds
Started May 05 02:56:03 PM PDT 24
Finished May 05 02:58:49 PM PDT 24
Peak memory 202268 kb
Host smart-26854934-21c2-4dc8-aa4d-a7e47161a697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358145640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2358145640
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.755357383
Short name T589
Test name
Test status
Simulation time 160980790738 ps
CPU time 363.76 seconds
Started May 05 02:55:59 PM PDT 24
Finished May 05 03:02:03 PM PDT 24
Peak memory 202312 kb
Host smart-66e78505-690b-4868-860b-bfb4e35bc3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755357383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.755357383
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3462313059
Short name T382
Test name
Test status
Simulation time 489480679255 ps
CPU time 596.35 seconds
Started May 05 02:56:00 PM PDT 24
Finished May 05 03:05:56 PM PDT 24
Peak memory 202308 kb
Host smart-e99e72f8-3f29-441b-8bed-351dffd8593c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462313059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3462313059
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1723103745
Short name T248
Test name
Test status
Simulation time 321404338351 ps
CPU time 774.04 seconds
Started May 05 02:56:00 PM PDT 24
Finished May 05 03:08:54 PM PDT 24
Peak memory 202352 kb
Host smart-9926cd15-7de8-4502-9e6a-f2eb46509b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723103745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1723103745
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.873685318
Short name T424
Test name
Test status
Simulation time 164954993684 ps
CPU time 377.95 seconds
Started May 05 02:55:59 PM PDT 24
Finished May 05 03:02:18 PM PDT 24
Peak memory 202260 kb
Host smart-9e3bd895-f3fe-4364-8978-33da37f31421
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=873685318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.873685318
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2224851435
Short name T362
Test name
Test status
Simulation time 192923674797 ps
CPU time 26.39 seconds
Started May 05 02:55:57 PM PDT 24
Finished May 05 02:56:24 PM PDT 24
Peak memory 202320 kb
Host smart-821e32cd-a3c4-4e6e-93f0-d50a5f128fe3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224851435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2224851435
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3710327135
Short name T523
Test name
Test status
Simulation time 194722271021 ps
CPU time 455.76 seconds
Started May 05 02:55:57 PM PDT 24
Finished May 05 03:03:33 PM PDT 24
Peak memory 202260 kb
Host smart-71d28444-ce45-458c-9fab-119810b565da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710327135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3710327135
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.321807496
Short name T793
Test name
Test status
Simulation time 97337320285 ps
CPU time 373.08 seconds
Started May 05 02:56:02 PM PDT 24
Finished May 05 03:02:15 PM PDT 24
Peak memory 202644 kb
Host smart-63d9e087-bf27-4e83-8c75-69ecd2ca47a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321807496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.321807496
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.566388644
Short name T379
Test name
Test status
Simulation time 22020905121 ps
CPU time 27.07 seconds
Started May 05 02:56:02 PM PDT 24
Finished May 05 02:56:30 PM PDT 24
Peak memory 202044 kb
Host smart-517aae3d-118b-4fb4-866c-3028a4aecb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566388644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.566388644
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3581608242
Short name T389
Test name
Test status
Simulation time 3036752503 ps
CPU time 7.63 seconds
Started May 05 02:56:05 PM PDT 24
Finished May 05 02:56:13 PM PDT 24
Peak memory 202128 kb
Host smart-a7165cb1-6d1a-4c3e-9d40-477f7628953a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581608242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3581608242
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.642263140
Short name T785
Test name
Test status
Simulation time 5966335672 ps
CPU time 8.29 seconds
Started May 05 02:55:54 PM PDT 24
Finished May 05 02:56:03 PM PDT 24
Peak memory 202136 kb
Host smart-34f6b01f-7d23-432f-ac77-211dd1e7d3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642263140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.642263140
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1688813667
Short name T250
Test name
Test status
Simulation time 4575988781532 ps
CPU time 513.99 seconds
Started May 05 02:56:05 PM PDT 24
Finished May 05 03:04:39 PM PDT 24
Peak memory 217908 kb
Host smart-f5441359-bd7a-446d-9067-4efcdbdd6928
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688813667 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1688813667
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.761165976
Short name T659
Test name
Test status
Simulation time 512905782 ps
CPU time 0.9 seconds
Started May 05 02:56:16 PM PDT 24
Finished May 05 02:56:18 PM PDT 24
Peak memory 202032 kb
Host smart-682f0e1a-fe14-49e1-8ee8-db61f97fcbc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761165976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.761165976
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2452056345
Short name T361
Test name
Test status
Simulation time 326342409330 ps
CPU time 202.03 seconds
Started May 05 02:56:08 PM PDT 24
Finished May 05 02:59:30 PM PDT 24
Peak memory 202292 kb
Host smart-4f4b82b2-a42e-4c75-96b6-d6956869ddde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452056345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2452056345
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3782302462
Short name T648
Test name
Test status
Simulation time 328506373756 ps
CPU time 181.74 seconds
Started May 05 02:56:08 PM PDT 24
Finished May 05 02:59:10 PM PDT 24
Peak memory 202296 kb
Host smart-fa81fd55-1b97-4fd1-9480-6fc193ae3a84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782302462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3782302462
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.699188950
Short name T153
Test name
Test status
Simulation time 324109405387 ps
CPU time 767.63 seconds
Started May 05 02:56:08 PM PDT 24
Finished May 05 03:08:56 PM PDT 24
Peak memory 202260 kb
Host smart-5abf5432-78f5-4476-a91e-9931b8cb9750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699188950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.699188950
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2602418379
Short name T657
Test name
Test status
Simulation time 491852818647 ps
CPU time 556.73 seconds
Started May 05 02:56:08 PM PDT 24
Finished May 05 03:05:25 PM PDT 24
Peak memory 202264 kb
Host smart-9656612a-2892-4962-947b-17298deaf4b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602418379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2602418379
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2398100775
Short name T591
Test name
Test status
Simulation time 574698114643 ps
CPU time 1216.16 seconds
Started May 05 02:56:07 PM PDT 24
Finished May 05 03:16:23 PM PDT 24
Peak memory 202332 kb
Host smart-15d9cae1-3855-4a34-850f-6e81378f8d0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398100775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2398100775
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.596263483
Short name T694
Test name
Test status
Simulation time 609134960303 ps
CPU time 595.01 seconds
Started May 05 02:56:07 PM PDT 24
Finished May 05 03:06:03 PM PDT 24
Peak memory 202264 kb
Host smart-673d45ba-7185-4e20-9955-0e84bc59b520
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596263483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.596263483
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.33195179
Short name T2
Test name
Test status
Simulation time 104882923607 ps
CPU time 531.43 seconds
Started May 05 02:56:15 PM PDT 24
Finished May 05 03:05:07 PM PDT 24
Peak memory 202568 kb
Host smart-f8e79c39-8eec-436f-8ab1-f7258b162ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33195179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.33195179
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2321344182
Short name T693
Test name
Test status
Simulation time 40055226837 ps
CPU time 21.58 seconds
Started May 05 02:56:11 PM PDT 24
Finished May 05 02:56:33 PM PDT 24
Peak memory 202140 kb
Host smart-40c31ec1-0aa8-4b59-8050-974b327e4dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321344182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2321344182
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3172433139
Short name T472
Test name
Test status
Simulation time 4079050637 ps
CPU time 2.97 seconds
Started May 05 02:56:11 PM PDT 24
Finished May 05 02:56:14 PM PDT 24
Peak memory 202128 kb
Host smart-36487405-0292-4baa-a641-86419199df00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172433139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3172433139
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3492084329
Short name T557
Test name
Test status
Simulation time 6059799262 ps
CPU time 12.7 seconds
Started May 05 02:56:08 PM PDT 24
Finished May 05 02:56:21 PM PDT 24
Peak memory 202144 kb
Host smart-7659ffb6-fb94-460e-83d2-dee1a4d9fb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492084329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3492084329
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2193106769
Short name T736
Test name
Test status
Simulation time 751890223082 ps
CPU time 1878.25 seconds
Started May 05 02:56:17 PM PDT 24
Finished May 05 03:27:35 PM PDT 24
Peak memory 202656 kb
Host smart-e596aa08-8583-474a-8337-58fd5bf77194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193106769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2193106769
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3144749491
Short name T34
Test name
Test status
Simulation time 40759122190 ps
CPU time 150.16 seconds
Started May 05 02:56:14 PM PDT 24
Finished May 05 02:58:45 PM PDT 24
Peak memory 210984 kb
Host smart-2e856354-95e2-441b-8017-30cc59824495
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144749491 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3144749491
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1058520221
Short name T497
Test name
Test status
Simulation time 484217558 ps
CPU time 0.89 seconds
Started May 05 02:56:19 PM PDT 24
Finished May 05 02:56:20 PM PDT 24
Peak memory 201984 kb
Host smart-56a59dd1-e250-4326-919e-2f4d9dcee919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058520221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1058520221
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.404276816
Short name T329
Test name
Test status
Simulation time 330912203810 ps
CPU time 207.5 seconds
Started May 05 02:56:16 PM PDT 24
Finished May 05 02:59:44 PM PDT 24
Peak memory 202372 kb
Host smart-d24bbd90-e52a-442a-bb54-fd756887bc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404276816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.404276816
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3940402467
Short name T514
Test name
Test status
Simulation time 491093369481 ps
CPU time 121.41 seconds
Started May 05 02:56:17 PM PDT 24
Finished May 05 02:58:19 PM PDT 24
Peak memory 202268 kb
Host smart-52199918-8f89-4946-a280-27ee14194530
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940402467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3940402467
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.961811056
Short name T111
Test name
Test status
Simulation time 485030481805 ps
CPU time 315.65 seconds
Started May 05 02:56:15 PM PDT 24
Finished May 05 03:01:31 PM PDT 24
Peak memory 202304 kb
Host smart-889ee748-1383-4bc7-bb69-d6b03fb4c60c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=961811056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.961811056
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3919015337
Short name T651
Test name
Test status
Simulation time 379986449140 ps
CPU time 144.41 seconds
Started May 05 02:56:16 PM PDT 24
Finished May 05 02:58:41 PM PDT 24
Peak memory 202316 kb
Host smart-59bcce25-4ab3-43fb-863c-088173947730
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919015337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3919015337
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2809530035
Short name T781
Test name
Test status
Simulation time 194703788622 ps
CPU time 470.17 seconds
Started May 05 02:56:17 PM PDT 24
Finished May 05 03:04:07 PM PDT 24
Peak memory 202296 kb
Host smart-c3d2945e-f328-4f5e-ace5-5a72ea3a28cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809530035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2809530035
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.629984342
Short name T705
Test name
Test status
Simulation time 39287811234 ps
CPU time 89.33 seconds
Started May 05 02:56:19 PM PDT 24
Finished May 05 02:57:49 PM PDT 24
Peak memory 202156 kb
Host smart-cec26f4a-f4d0-4e62-9366-6be4195b6755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629984342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.629984342
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2484678215
Short name T496
Test name
Test status
Simulation time 5194675170 ps
CPU time 3.71 seconds
Started May 05 02:56:22 PM PDT 24
Finished May 05 02:56:26 PM PDT 24
Peak memory 202124 kb
Host smart-18e642aa-7073-4885-8fac-87f8f3e0058c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484678215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2484678215
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.4078703175
Short name T437
Test name
Test status
Simulation time 5500531662 ps
CPU time 14.1 seconds
Started May 05 02:56:17 PM PDT 24
Finished May 05 02:56:32 PM PDT 24
Peak memory 202144 kb
Host smart-1e467731-5cde-4e3c-b942-7aa2d7574ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078703175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.4078703175
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2334041470
Short name T117
Test name
Test status
Simulation time 327359718123 ps
CPU time 403.92 seconds
Started May 05 02:56:19 PM PDT 24
Finished May 05 03:03:03 PM PDT 24
Peak memory 202280 kb
Host smart-2c3cfc00-3a55-4164-8902-b52cbc5d1000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334041470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2334041470
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1072742032
Short name T47
Test name
Test status
Simulation time 400337008 ps
CPU time 0.83 seconds
Started May 05 02:56:25 PM PDT 24
Finished May 05 02:56:26 PM PDT 24
Peak memory 201956 kb
Host smart-dc485453-a15a-496f-ba3b-aec58affd001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072742032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1072742032
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3095419895
Short name T632
Test name
Test status
Simulation time 171474855780 ps
CPU time 131.43 seconds
Started May 05 02:56:25 PM PDT 24
Finished May 05 02:58:37 PM PDT 24
Peak memory 202364 kb
Host smart-512e3050-5d50-420b-b5fe-c586d0aacf4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095419895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3095419895
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.4179645929
Short name T211
Test name
Test status
Simulation time 359477463162 ps
CPU time 197.54 seconds
Started May 05 02:56:24 PM PDT 24
Finished May 05 02:59:42 PM PDT 24
Peak memory 202260 kb
Host smart-78b055c6-1589-4a5e-a092-07c5c43760a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179645929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.4179645929
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1430761452
Short name T100
Test name
Test status
Simulation time 167812222650 ps
CPU time 47.17 seconds
Started May 05 02:56:23 PM PDT 24
Finished May 05 02:57:10 PM PDT 24
Peak memory 202372 kb
Host smart-a4d8b8ee-1a0b-4384-89fd-ebf6b2c8cdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430761452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1430761452
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1493481894
Short name T490
Test name
Test status
Simulation time 161660226489 ps
CPU time 193 seconds
Started May 05 02:56:18 PM PDT 24
Finished May 05 02:59:32 PM PDT 24
Peak memory 202284 kb
Host smart-000e9e4e-ede6-45ae-b7c7-453af78defd6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493481894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1493481894
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1317872108
Short name T179
Test name
Test status
Simulation time 326736349280 ps
CPU time 146.43 seconds
Started May 05 02:56:23 PM PDT 24
Finished May 05 02:58:50 PM PDT 24
Peak memory 202280 kb
Host smart-5ddc8c0e-29a5-4cb4-b1ec-27e870f1ee08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317872108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1317872108
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2379082446
Short name T733
Test name
Test status
Simulation time 490536425938 ps
CPU time 300.57 seconds
Started May 05 02:56:19 PM PDT 24
Finished May 05 03:01:20 PM PDT 24
Peak memory 202272 kb
Host smart-231dc93b-3f8e-440c-8cdd-df580d5b3806
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379082446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2379082446
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3189366701
Short name T357
Test name
Test status
Simulation time 173351997188 ps
CPU time 357.76 seconds
Started May 05 02:56:23 PM PDT 24
Finished May 05 03:02:21 PM PDT 24
Peak memory 202308 kb
Host smart-f72cb741-4efc-4e10-a2d6-7eae03579056
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189366701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3189366701
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2464666840
Short name T633
Test name
Test status
Simulation time 203177223969 ps
CPU time 216.81 seconds
Started May 05 02:56:24 PM PDT 24
Finished May 05 03:00:01 PM PDT 24
Peak memory 202288 kb
Host smart-c6379377-6365-4076-b243-1260405de838
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464666840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2464666840
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1332378420
Short name T373
Test name
Test status
Simulation time 109249647364 ps
CPU time 604.34 seconds
Started May 05 02:56:24 PM PDT 24
Finished May 05 03:06:29 PM PDT 24
Peak memory 202588 kb
Host smart-2645f379-59bd-4b99-ab84-639b534f9d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332378420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1332378420
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2530763046
Short name T181
Test name
Test status
Simulation time 25945886911 ps
CPU time 27.43 seconds
Started May 05 02:56:24 PM PDT 24
Finished May 05 02:56:51 PM PDT 24
Peak memory 202132 kb
Host smart-9319f6c4-8f46-4c0c-b3bc-377598853ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530763046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2530763046
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3155428519
Short name T400
Test name
Test status
Simulation time 3355869046 ps
CPU time 6.93 seconds
Started May 05 02:56:26 PM PDT 24
Finished May 05 02:56:33 PM PDT 24
Peak memory 202140 kb
Host smart-61f10360-00d7-4c85-a37f-1abf9b212657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155428519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3155428519
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3491868017
Short name T787
Test name
Test status
Simulation time 5954111094 ps
CPU time 4.44 seconds
Started May 05 02:56:20 PM PDT 24
Finished May 05 02:56:25 PM PDT 24
Peak memory 202044 kb
Host smart-8aa60bdb-bbe8-4638-9aa9-d18a1ca36b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491868017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3491868017
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2412484643
Short name T769
Test name
Test status
Simulation time 194455777018 ps
CPU time 440.23 seconds
Started May 05 02:56:26 PM PDT 24
Finished May 05 03:03:46 PM PDT 24
Peak memory 202328 kb
Host smart-a5f2eefb-36ba-4bcf-8097-fc61469d2329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412484643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2412484643
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.4282352645
Short name T21
Test name
Test status
Simulation time 154613715428 ps
CPU time 330.5 seconds
Started May 05 02:56:26 PM PDT 24
Finished May 05 03:01:57 PM PDT 24
Peak memory 210968 kb
Host smart-3649ae00-5f73-4e48-8a8d-f81872a9c0fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282352645 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.4282352645
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3063987989
Short name T491
Test name
Test status
Simulation time 523553335 ps
CPU time 1.21 seconds
Started May 05 02:56:34 PM PDT 24
Finished May 05 02:56:35 PM PDT 24
Peak memory 202016 kb
Host smart-1be76dae-5a7a-4602-b0b1-fe73574ad947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063987989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3063987989
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2235861490
Short name T303
Test name
Test status
Simulation time 171911077464 ps
CPU time 50.65 seconds
Started May 05 02:56:30 PM PDT 24
Finished May 05 02:57:21 PM PDT 24
Peak memory 202372 kb
Host smart-c3913d19-2d5d-405b-8065-74026d94b9c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235861490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2235861490
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3594145025
Short name T336
Test name
Test status
Simulation time 515026742442 ps
CPU time 1163.23 seconds
Started May 05 02:56:28 PM PDT 24
Finished May 05 03:15:52 PM PDT 24
Peak memory 202272 kb
Host smart-aafc8aef-ec87-4338-871b-a1019dd59376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594145025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3594145025
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2334581619
Short name T598
Test name
Test status
Simulation time 166884159949 ps
CPU time 366.3 seconds
Started May 05 02:56:26 PM PDT 24
Finished May 05 03:02:33 PM PDT 24
Peak memory 202288 kb
Host smart-c06ebdeb-6f5a-46bc-ba24-30a0c4711f5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334581619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2334581619
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1126252333
Short name T356
Test name
Test status
Simulation time 493364220852 ps
CPU time 1184.6 seconds
Started May 05 02:56:27 PM PDT 24
Finished May 05 03:16:12 PM PDT 24
Peak memory 202296 kb
Host smart-4cbe2a78-bd32-4bdc-b057-4d9e3111b569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126252333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1126252333
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2132097223
Short name T569
Test name
Test status
Simulation time 328333281548 ps
CPU time 180.78 seconds
Started May 05 02:56:25 PM PDT 24
Finished May 05 02:59:26 PM PDT 24
Peak memory 202252 kb
Host smart-c0ae690c-68b0-4079-b5bd-0d51752ad233
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132097223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2132097223
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2325540257
Short name T104
Test name
Test status
Simulation time 507146364359 ps
CPU time 323.12 seconds
Started May 05 02:56:26 PM PDT 24
Finished May 05 03:01:49 PM PDT 24
Peak memory 202388 kb
Host smart-0196b7de-9614-44ef-adb1-cd710974c0dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325540257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2325540257
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.689351270
Short name T499
Test name
Test status
Simulation time 398315893569 ps
CPU time 235.64 seconds
Started May 05 02:56:31 PM PDT 24
Finished May 05 03:00:27 PM PDT 24
Peak memory 202264 kb
Host smart-f7b13d76-f001-458c-b376-76d8c8566d9a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689351270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.689351270
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2872060482
Short name T54
Test name
Test status
Simulation time 90087134061 ps
CPU time 361.87 seconds
Started May 05 02:56:30 PM PDT 24
Finished May 05 03:02:32 PM PDT 24
Peak memory 202732 kb
Host smart-211a9933-349c-4fb9-9327-33ad65875b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872060482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2872060482
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1871997441
Short name T16
Test name
Test status
Simulation time 41985795295 ps
CPU time 25.16 seconds
Started May 05 02:56:29 PM PDT 24
Finished May 05 02:56:55 PM PDT 24
Peak memory 202144 kb
Host smart-c3e3a46c-b115-4680-ac4a-177cc99393c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871997441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1871997441
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3890686905
Short name T749
Test name
Test status
Simulation time 2780680146 ps
CPU time 2.53 seconds
Started May 05 02:56:29 PM PDT 24
Finished May 05 02:56:32 PM PDT 24
Peak memory 202128 kb
Host smart-9f33f752-4dc1-411a-b868-d39992a18427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890686905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3890686905
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1872020992
Short name T612
Test name
Test status
Simulation time 6047109335 ps
CPU time 4.82 seconds
Started May 05 02:56:25 PM PDT 24
Finished May 05 02:56:30 PM PDT 24
Peak memory 202104 kb
Host smart-8d9a0a06-5e35-45f1-b353-fa5245c67914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872020992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1872020992
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.669469881
Short name T543
Test name
Test status
Simulation time 32862795568 ps
CPU time 76.98 seconds
Started May 05 02:56:29 PM PDT 24
Finished May 05 02:57:46 PM PDT 24
Peak memory 210592 kb
Host smart-4319446b-3982-48f1-90be-8879f7cf4330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669469881 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.669469881
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.4027465456
Short name T454
Test name
Test status
Simulation time 383154806 ps
CPU time 0.68 seconds
Started May 05 02:56:41 PM PDT 24
Finished May 05 02:56:42 PM PDT 24
Peak memory 201992 kb
Host smart-12961e64-b5a3-49b7-b66a-41af9fe59cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027465456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.4027465456
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1375864044
Short name T251
Test name
Test status
Simulation time 489840968640 ps
CPU time 564.53 seconds
Started May 05 02:56:32 PM PDT 24
Finished May 05 03:05:57 PM PDT 24
Peak memory 202344 kb
Host smart-1b543146-9de0-4741-a92e-67a5b450834c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375864044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1375864044
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.751000057
Short name T527
Test name
Test status
Simulation time 165586722545 ps
CPU time 385.06 seconds
Started May 05 02:56:33 PM PDT 24
Finished May 05 03:02:58 PM PDT 24
Peak memory 202400 kb
Host smart-f8dfca35-ee93-440f-a66a-d4177392d784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751000057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.751000057
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2659978635
Short name T640
Test name
Test status
Simulation time 333694715342 ps
CPU time 408.33 seconds
Started May 05 02:56:31 PM PDT 24
Finished May 05 03:03:20 PM PDT 24
Peak memory 202228 kb
Host smart-75866d70-4ff4-4aee-a14f-6fce023ba80f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659978635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2659978635
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3756542828
Short name T327
Test name
Test status
Simulation time 323608376051 ps
CPU time 683.49 seconds
Started May 05 02:56:31 PM PDT 24
Finished May 05 03:07:55 PM PDT 24
Peak memory 202288 kb
Host smart-dfa2397e-dc21-4ccd-aca2-b61d5f128c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756542828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3756542828
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1971388595
Short name T533
Test name
Test status
Simulation time 173502618494 ps
CPU time 366.39 seconds
Started May 05 02:56:34 PM PDT 24
Finished May 05 03:02:41 PM PDT 24
Peak memory 202312 kb
Host smart-99961bc2-0f2f-425c-b670-366650035420
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971388595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1971388595
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1020118188
Short name T559
Test name
Test status
Simulation time 170766761285 ps
CPU time 105.32 seconds
Started May 05 02:56:31 PM PDT 24
Finished May 05 02:58:17 PM PDT 24
Peak memory 202304 kb
Host smart-34eea2d4-e396-4439-90c8-dd50da5de278
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020118188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1020118188
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2224230825
Short name T452
Test name
Test status
Simulation time 209386310719 ps
CPU time 29.22 seconds
Started May 05 02:56:34 PM PDT 24
Finished May 05 02:57:03 PM PDT 24
Peak memory 202280 kb
Host smart-b8632a7c-1c8e-4f76-9912-54ac5c1c5026
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224230825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2224230825
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.4105146752
Short name T707
Test name
Test status
Simulation time 24516138634 ps
CPU time 16.39 seconds
Started May 05 02:56:38 PM PDT 24
Finished May 05 02:56:55 PM PDT 24
Peak memory 202172 kb
Host smart-9a8c0fe9-d4b0-49f3-a573-360e4b59af8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105146752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.4105146752
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.503830212
Short name T1
Test name
Test status
Simulation time 3667574123 ps
CPU time 5.23 seconds
Started May 05 02:56:41 PM PDT 24
Finished May 05 02:56:47 PM PDT 24
Peak memory 202068 kb
Host smart-2963deab-447e-475f-b9ad-d9ce4e1021f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503830212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.503830212
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.778460436
Short name T107
Test name
Test status
Simulation time 6065425974 ps
CPU time 1.46 seconds
Started May 05 02:56:33 PM PDT 24
Finished May 05 02:56:34 PM PDT 24
Peak memory 202108 kb
Host smart-98198957-5539-48d4-ab04-a1c1d0a07ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778460436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.778460436
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.893466750
Short name T739
Test name
Test status
Simulation time 303389593151 ps
CPU time 175.32 seconds
Started May 05 02:56:39 PM PDT 24
Finished May 05 02:59:34 PM PDT 24
Peak memory 210584 kb
Host smart-9750bdd6-557b-4324-a750-fd53a3743157
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893466750 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.893466750
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.109001487
Short name T77
Test name
Test status
Simulation time 337869906 ps
CPU time 0.78 seconds
Started May 05 02:51:25 PM PDT 24
Finished May 05 02:51:27 PM PDT 24
Peak memory 201960 kb
Host smart-ef5d0bd5-a3b5-4170-9124-55f488016a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109001487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.109001487
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.65212387
Short name T262
Test name
Test status
Simulation time 515157257094 ps
CPU time 1207.22 seconds
Started May 05 02:51:20 PM PDT 24
Finished May 05 03:11:28 PM PDT 24
Peak memory 202264 kb
Host smart-bba462a3-143b-41ac-96da-05339502445c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65212387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating
.65212387
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2391480317
Short name T304
Test name
Test status
Simulation time 540635829722 ps
CPU time 346.97 seconds
Started May 05 02:51:21 PM PDT 24
Finished May 05 02:57:09 PM PDT 24
Peak memory 202356 kb
Host smart-7bf6f129-9e38-4708-959b-0130cafe65a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391480317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2391480317
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.4291526888
Short name T164
Test name
Test status
Simulation time 330930072337 ps
CPU time 686.85 seconds
Started May 05 02:51:21 PM PDT 24
Finished May 05 03:02:48 PM PDT 24
Peak memory 202316 kb
Host smart-f590336c-858e-4403-a36b-390b9c757557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291526888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.4291526888
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2114239891
Short name T52
Test name
Test status
Simulation time 323037678251 ps
CPU time 709.43 seconds
Started May 05 02:51:23 PM PDT 24
Finished May 05 03:03:13 PM PDT 24
Peak memory 202280 kb
Host smart-a5734db8-7214-4004-ae6a-682a16276468
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114239891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2114239891
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.4060276881
Short name T614
Test name
Test status
Simulation time 161309357687 ps
CPU time 66.51 seconds
Started May 05 02:51:20 PM PDT 24
Finished May 05 02:52:27 PM PDT 24
Peak memory 202276 kb
Host smart-cb30da45-78d8-40d0-b9a7-465cda209083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060276881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.4060276881
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2941067159
Short name T33
Test name
Test status
Simulation time 500540952639 ps
CPU time 938.56 seconds
Started May 05 02:51:21 PM PDT 24
Finished May 05 03:07:00 PM PDT 24
Peak memory 202200 kb
Host smart-3bd1a639-9b1e-47d9-a47f-f0ccb95234c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941067159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2941067159
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.4113291987
Short name T227
Test name
Test status
Simulation time 560565391142 ps
CPU time 321.94 seconds
Started May 05 02:51:24 PM PDT 24
Finished May 05 02:56:46 PM PDT 24
Peak memory 202356 kb
Host smart-567c3429-8764-4cd7-b28b-7de708146ca5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113291987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.4113291987
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.233870536
Short name T771
Test name
Test status
Simulation time 591012797270 ps
CPU time 1401.82 seconds
Started May 05 02:51:21 PM PDT 24
Finished May 05 03:14:43 PM PDT 24
Peak memory 202280 kb
Host smart-0f3c6d15-f8a3-489a-8532-d29660b17f80
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233870536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.233870536
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3326018680
Short name T604
Test name
Test status
Simulation time 96036436607 ps
CPU time 283.64 seconds
Started May 05 02:51:21 PM PDT 24
Finished May 05 02:56:05 PM PDT 24
Peak memory 202908 kb
Host smart-e2c8012b-07b2-46ed-b76e-3810912f8d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326018680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3326018680
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1172619138
Short name T123
Test name
Test status
Simulation time 36018511711 ps
CPU time 77.26 seconds
Started May 05 02:51:22 PM PDT 24
Finished May 05 02:52:39 PM PDT 24
Peak memory 202152 kb
Host smart-13931dd3-97a7-44de-8c6d-dea39bea2ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172619138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1172619138
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3762137883
Short name T381
Test name
Test status
Simulation time 2903188829 ps
CPU time 3.38 seconds
Started May 05 02:51:23 PM PDT 24
Finished May 05 02:51:27 PM PDT 24
Peak memory 202120 kb
Host smart-1e7e3dfc-c030-49fb-8f42-77eebb06e184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762137883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3762137883
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3796582952
Short name T87
Test name
Test status
Simulation time 8402645429 ps
CPU time 1.89 seconds
Started May 05 02:51:24 PM PDT 24
Finished May 05 02:51:26 PM PDT 24
Peak memory 218844 kb
Host smart-7f1ff8c7-809e-49d8-a043-a3756c802ee6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796582952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3796582952
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3194972380
Short name T678
Test name
Test status
Simulation time 5930711666 ps
CPU time 4.19 seconds
Started May 05 02:51:21 PM PDT 24
Finished May 05 02:51:26 PM PDT 24
Peak memory 202148 kb
Host smart-030f9e84-c3ca-4056-9f94-38d8510b196d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194972380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3194972380
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4059206214
Short name T542
Test name
Test status
Simulation time 670397793478 ps
CPU time 750.71 seconds
Started May 05 02:51:24 PM PDT 24
Finished May 05 03:03:55 PM PDT 24
Peak memory 202188 kb
Host smart-459706a9-31d2-4017-84db-62fb51cfc7fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059206214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4059206214
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1966081248
Short name T41
Test name
Test status
Simulation time 168248285961 ps
CPU time 127.12 seconds
Started May 05 02:51:20 PM PDT 24
Finished May 05 02:53:27 PM PDT 24
Peak memory 218284 kb
Host smart-342b661b-c282-475b-9bdd-64b36b2548e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966081248 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1966081248
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1674009762
Short name T567
Test name
Test status
Simulation time 430824786 ps
CPU time 0.89 seconds
Started May 05 02:56:40 PM PDT 24
Finished May 05 02:56:42 PM PDT 24
Peak memory 201980 kb
Host smart-f853a68a-7803-4b5d-b8d8-9053ca6b3c08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674009762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1674009762
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3001723286
Short name T504
Test name
Test status
Simulation time 411394951386 ps
CPU time 473.56 seconds
Started May 05 02:56:40 PM PDT 24
Finished May 05 03:04:34 PM PDT 24
Peak memory 202312 kb
Host smart-2aab819b-c875-4e44-875a-c82332182e92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001723286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3001723286
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1913208256
Short name T644
Test name
Test status
Simulation time 318364060729 ps
CPU time 769.83 seconds
Started May 05 02:56:40 PM PDT 24
Finished May 05 03:09:30 PM PDT 24
Peak memory 202356 kb
Host smart-ee86f033-4ac7-420d-bdc5-5e44e03629bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913208256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1913208256
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.339493644
Short name T449
Test name
Test status
Simulation time 168596904615 ps
CPU time 399.83 seconds
Started May 05 02:56:38 PM PDT 24
Finished May 05 03:03:18 PM PDT 24
Peak memory 202284 kb
Host smart-54d1ccdf-4a86-47ac-a349-cc2612b4454d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=339493644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.339493644
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.123702101
Short name T366
Test name
Test status
Simulation time 166809129006 ps
CPU time 390.36 seconds
Started May 05 02:56:44 PM PDT 24
Finished May 05 03:03:14 PM PDT 24
Peak memory 202276 kb
Host smart-4f026b3d-31e8-4f62-a423-a1c16bf10d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123702101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.123702101
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.859715013
Short name T706
Test name
Test status
Simulation time 495560116220 ps
CPU time 1048.16 seconds
Started May 05 02:56:40 PM PDT 24
Finished May 05 03:14:09 PM PDT 24
Peak memory 202292 kb
Host smart-92905976-42c2-4028-b60f-8acad6389b5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=859715013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.859715013
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1475019351
Short name T99
Test name
Test status
Simulation time 174330578842 ps
CPU time 395.38 seconds
Started May 05 02:56:39 PM PDT 24
Finished May 05 03:03:14 PM PDT 24
Peak memory 202252 kb
Host smart-d3426de4-c779-4fd0-ae4b-f1618032d2c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475019351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1475019351
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2245159584
Short name T782
Test name
Test status
Simulation time 611476763671 ps
CPU time 379 seconds
Started May 05 02:56:37 PM PDT 24
Finished May 05 03:02:57 PM PDT 24
Peak memory 202260 kb
Host smart-42f1d0c6-00db-4b30-9d44-a2f795e92b59
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245159584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2245159584
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2107904136
Short name T30
Test name
Test status
Simulation time 94086731648 ps
CPU time 532.71 seconds
Started May 05 02:56:41 PM PDT 24
Finished May 05 03:05:34 PM PDT 24
Peak memory 202608 kb
Host smart-129cdbeb-ef81-4276-be29-8956f6a9d3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107904136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2107904136
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2820113637
Short name T646
Test name
Test status
Simulation time 44580753274 ps
CPU time 91.96 seconds
Started May 05 02:56:43 PM PDT 24
Finished May 05 02:58:16 PM PDT 24
Peak memory 202132 kb
Host smart-0c78a56a-92b0-41b8-8027-db530af9b96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820113637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2820113637
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1590557846
Short name T638
Test name
Test status
Simulation time 4048199076 ps
CPU time 6.94 seconds
Started May 05 02:56:43 PM PDT 24
Finished May 05 02:56:50 PM PDT 24
Peak memory 202072 kb
Host smart-2b2fa08b-59cb-42e6-b7b3-a44f204f649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590557846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1590557846
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2556712847
Short name T698
Test name
Test status
Simulation time 5666437939 ps
CPU time 4.39 seconds
Started May 05 02:56:41 PM PDT 24
Finished May 05 02:56:46 PM PDT 24
Peak memory 202088 kb
Host smart-3500a538-8c99-4baf-b49b-194b97db101f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556712847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2556712847
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3556090312
Short name T313
Test name
Test status
Simulation time 258766323609 ps
CPU time 820.62 seconds
Started May 05 02:56:42 PM PDT 24
Finished May 05 03:10:23 PM PDT 24
Peak memory 210852 kb
Host smart-a97c2ec6-3fb2-422e-a1e6-872f26a8e82a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556090312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3556090312
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.4045761483
Short name T230
Test name
Test status
Simulation time 224962964909 ps
CPU time 79.71 seconds
Started May 05 02:56:40 PM PDT 24
Finished May 05 02:58:00 PM PDT 24
Peak memory 210620 kb
Host smart-e40de69f-1e6e-4893-8be6-b202895f0da1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045761483 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.4045761483
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.203241098
Short name T743
Test name
Test status
Simulation time 516591108 ps
CPU time 1.88 seconds
Started May 05 02:56:51 PM PDT 24
Finished May 05 02:56:53 PM PDT 24
Peak memory 201984 kb
Host smart-f8a059e6-92cf-49c7-a6a8-a99e5cb72600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203241098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.203241098
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1856062741
Short name T768
Test name
Test status
Simulation time 162768400011 ps
CPU time 185.51 seconds
Started May 05 02:56:43 PM PDT 24
Finished May 05 02:59:49 PM PDT 24
Peak memory 202380 kb
Host smart-a40aae06-6ee2-4f9b-bf1f-a48ee04b75f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856062741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1856062741
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.4228117681
Short name T280
Test name
Test status
Simulation time 166911550551 ps
CPU time 80.93 seconds
Started May 05 02:56:44 PM PDT 24
Finished May 05 02:58:06 PM PDT 24
Peak memory 202288 kb
Host smart-53bfc5ca-17f4-469d-b549-dffd6bb55ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228117681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.4228117681
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2858041577
Short name T89
Test name
Test status
Simulation time 334077213238 ps
CPU time 53.21 seconds
Started May 05 02:56:46 PM PDT 24
Finished May 05 02:57:40 PM PDT 24
Peak memory 202324 kb
Host smart-dbf790ff-2853-423b-ba42-ba88df479e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858041577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2858041577
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3661058436
Short name T778
Test name
Test status
Simulation time 487905653040 ps
CPU time 1034.88 seconds
Started May 05 02:56:46 PM PDT 24
Finished May 05 03:14:01 PM PDT 24
Peak memory 202240 kb
Host smart-ec9b0cb6-86f6-47e6-8fc2-e7e28d92bc1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661058436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3661058436
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3611581814
Short name T342
Test name
Test status
Simulation time 165287242756 ps
CPU time 90.74 seconds
Started May 05 02:56:42 PM PDT 24
Finished May 05 02:58:13 PM PDT 24
Peak memory 202388 kb
Host smart-b736be1f-6c7d-4c3d-9090-c702cc344c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611581814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3611581814
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2385185684
Short name T455
Test name
Test status
Simulation time 486389492214 ps
CPU time 302.91 seconds
Started May 05 02:56:45 PM PDT 24
Finished May 05 03:01:48 PM PDT 24
Peak memory 202276 kb
Host smart-77d4bdc6-76b7-45e9-9ab4-5c970d5cb315
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385185684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2385185684
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2195976831
Short name T322
Test name
Test status
Simulation time 365213852163 ps
CPU time 385.06 seconds
Started May 05 02:56:45 PM PDT 24
Finished May 05 03:03:10 PM PDT 24
Peak memory 202280 kb
Host smart-9bd8d4a8-71b0-4bdd-89fa-50c3919f639d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195976831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2195976831
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.4134790853
Short name T751
Test name
Test status
Simulation time 93375741144 ps
CPU time 532.13 seconds
Started May 05 02:56:50 PM PDT 24
Finished May 05 03:05:42 PM PDT 24
Peak memory 202728 kb
Host smart-25e1bae4-dc59-4a8c-947d-5bb2902dc4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134790853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.4134790853
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.77804587
Short name T471
Test name
Test status
Simulation time 32241003493 ps
CPU time 24.49 seconds
Started May 05 02:56:52 PM PDT 24
Finished May 05 02:57:16 PM PDT 24
Peak memory 202152 kb
Host smart-493dcceb-6477-461f-a70a-c1e8cccc6758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77804587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.77804587
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3107188635
Short name T777
Test name
Test status
Simulation time 3735640509 ps
CPU time 8.15 seconds
Started May 05 02:56:44 PM PDT 24
Finished May 05 02:56:53 PM PDT 24
Peak memory 202080 kb
Host smart-5f8aae7c-3c64-4056-9052-6ab5feaef98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107188635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3107188635
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3704905520
Short name T649
Test name
Test status
Simulation time 6024495618 ps
CPU time 1.97 seconds
Started May 05 02:56:41 PM PDT 24
Finished May 05 02:56:43 PM PDT 24
Peak memory 202304 kb
Host smart-eeb3acb9-01ef-47b0-a60a-71715b173d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704905520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3704905520
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1745344560
Short name T275
Test name
Test status
Simulation time 363276110349 ps
CPU time 790.03 seconds
Started May 05 02:56:51 PM PDT 24
Finished May 05 03:10:01 PM PDT 24
Peak memory 202584 kb
Host smart-e5a06fa3-8f4b-40b5-8a6e-a3ab574e81ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745344560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1745344560
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2701388715
Short name T333
Test name
Test status
Simulation time 166229747563 ps
CPU time 360.32 seconds
Started May 05 02:56:53 PM PDT 24
Finished May 05 03:02:54 PM PDT 24
Peak memory 218776 kb
Host smart-24e2f136-b9a4-427e-ac57-a88d5da597aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701388715 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2701388715
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.41095754
Short name T402
Test name
Test status
Simulation time 293381718 ps
CPU time 1.08 seconds
Started May 05 02:57:07 PM PDT 24
Finished May 05 02:57:09 PM PDT 24
Peak memory 201980 kb
Host smart-f67cb35d-c1c8-4ba7-b1db-887a9e34b4c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41095754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.41095754
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1315562062
Short name T300
Test name
Test status
Simulation time 345847443059 ps
CPU time 65.34 seconds
Started May 05 02:56:56 PM PDT 24
Finished May 05 02:58:02 PM PDT 24
Peak memory 202304 kb
Host smart-3e91b351-22b2-40ab-9987-ca3a00ef39dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315562062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1315562062
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1855443376
Short name T325
Test name
Test status
Simulation time 163781640664 ps
CPU time 205.42 seconds
Started May 05 02:57:08 PM PDT 24
Finished May 05 03:00:34 PM PDT 24
Peak memory 202292 kb
Host smart-133b78c8-2f6a-41a0-a337-54befd814e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855443376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1855443376
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.735326117
Short name T571
Test name
Test status
Simulation time 333396636471 ps
CPU time 766.58 seconds
Started May 05 02:56:56 PM PDT 24
Finished May 05 03:09:43 PM PDT 24
Peak memory 202308 kb
Host smart-b286979c-1ac3-4afa-ad02-488e5c7f1b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735326117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.735326117
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.154214773
Short name T532
Test name
Test status
Simulation time 165807460826 ps
CPU time 201.98 seconds
Started May 05 02:56:53 PM PDT 24
Finished May 05 03:00:15 PM PDT 24
Peak memory 202296 kb
Host smart-c007f2b0-59c5-4e97-a61f-138fbcb25a10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=154214773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.154214773
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1794142312
Short name T195
Test name
Test status
Simulation time 490105661838 ps
CPU time 285.93 seconds
Started May 05 02:56:53 PM PDT 24
Finished May 05 03:01:39 PM PDT 24
Peak memory 202280 kb
Host smart-85f94c84-9244-40a0-bfd6-b7363ae66d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794142312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1794142312
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1789542498
Short name T384
Test name
Test status
Simulation time 165547517538 ps
CPU time 383.5 seconds
Started May 05 02:56:51 PM PDT 24
Finished May 05 03:03:15 PM PDT 24
Peak memory 202336 kb
Host smart-08fad5c3-95c5-4eeb-a701-c9a31262ab53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789542498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1789542498
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3093288267
Short name T171
Test name
Test status
Simulation time 603678583504 ps
CPU time 188.75 seconds
Started May 05 02:56:52 PM PDT 24
Finished May 05 03:00:01 PM PDT 24
Peak memory 202296 kb
Host smart-c1758792-e259-4bd7-9f3e-594b8716a7cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093288267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3093288267
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.453260236
Short name T234
Test name
Test status
Simulation time 67761669470 ps
CPU time 370.5 seconds
Started May 05 02:57:08 PM PDT 24
Finished May 05 03:03:19 PM PDT 24
Peak memory 202636 kb
Host smart-c36f00ae-4ce4-4c95-be8b-d10f1a2f7fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453260236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.453260236
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.621659937
Short name T475
Test name
Test status
Simulation time 26933781741 ps
CPU time 15.39 seconds
Started May 05 02:56:58 PM PDT 24
Finished May 05 02:57:14 PM PDT 24
Peak memory 202108 kb
Host smart-0d3c0ef9-e389-4772-a727-6c3619e295b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621659937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.621659937
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3524735855
Short name T404
Test name
Test status
Simulation time 4980055481 ps
CPU time 1.78 seconds
Started May 05 02:57:08 PM PDT 24
Finished May 05 02:57:10 PM PDT 24
Peak memory 202136 kb
Host smart-7b587f9c-3cdb-434a-afcc-3e46efb9ac68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524735855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3524735855
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3116187374
Short name T408
Test name
Test status
Simulation time 5859199929 ps
CPU time 13.03 seconds
Started May 05 02:56:50 PM PDT 24
Finished May 05 02:57:03 PM PDT 24
Peak memory 202108 kb
Host smart-7c71b3a6-d7be-46c0-ae42-e1a954221b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116187374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3116187374
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2579325642
Short name T22
Test name
Test status
Simulation time 241772886757 ps
CPU time 274.38 seconds
Started May 05 02:57:09 PM PDT 24
Finished May 05 03:01:44 PM PDT 24
Peak memory 210920 kb
Host smart-470eacee-bf86-4e34-873d-901ba532fb96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579325642 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2579325642
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2423406807
Short name T433
Test name
Test status
Simulation time 439692769 ps
CPU time 1.6 seconds
Started May 05 02:57:09 PM PDT 24
Finished May 05 02:57:11 PM PDT 24
Peak memory 202012 kb
Host smart-44f7d9ac-f92d-4bee-84c7-4c89b23c0fb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423406807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2423406807
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3110392879
Short name T177
Test name
Test status
Simulation time 328800969748 ps
CPU time 362.57 seconds
Started May 05 02:57:10 PM PDT 24
Finished May 05 03:03:13 PM PDT 24
Peak memory 202272 kb
Host smart-a78d4b38-81bd-4278-966d-a5ca2e1546e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110392879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3110392879
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2456932086
Short name T664
Test name
Test status
Simulation time 333866212665 ps
CPU time 193.48 seconds
Started May 05 02:57:13 PM PDT 24
Finished May 05 03:00:27 PM PDT 24
Peak memory 202376 kb
Host smart-b0b2f4df-098c-4f67-8404-3a6e539e2e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456932086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2456932086
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1936154601
Short name T291
Test name
Test status
Simulation time 489464120439 ps
CPU time 608.13 seconds
Started May 05 02:57:10 PM PDT 24
Finished May 05 03:07:19 PM PDT 24
Peak memory 202364 kb
Host smart-f4d1403b-6682-41ef-a400-a75744c12a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936154601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1936154601
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2556673328
Short name T607
Test name
Test status
Simulation time 493806668299 ps
CPU time 134.34 seconds
Started May 05 02:57:09 PM PDT 24
Finished May 05 02:59:24 PM PDT 24
Peak memory 202248 kb
Host smart-99e3ad12-4618-4fd5-bc5a-9c0e0af71bbb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556673328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2556673328
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3133261265
Short name T115
Test name
Test status
Simulation time 334584662802 ps
CPU time 191.36 seconds
Started May 05 02:57:08 PM PDT 24
Finished May 05 03:00:20 PM PDT 24
Peak memory 202272 kb
Host smart-500d87a0-81d9-42fa-b86e-2ae716702b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133261265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3133261265
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2302520926
Short name T396
Test name
Test status
Simulation time 482791851815 ps
CPU time 1056.26 seconds
Started May 05 02:57:07 PM PDT 24
Finished May 05 03:14:44 PM PDT 24
Peak memory 202288 kb
Host smart-822bc604-71fd-4744-ad1a-defc4aec5df6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302520926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2302520926
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3368470954
Short name T92
Test name
Test status
Simulation time 227716826601 ps
CPU time 99.83 seconds
Started May 05 02:57:10 PM PDT 24
Finished May 05 02:58:50 PM PDT 24
Peak memory 202308 kb
Host smart-5cd982b7-bb48-4a3a-9a0b-7056954d62a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368470954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3368470954
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1852555999
Short name T550
Test name
Test status
Simulation time 202534758790 ps
CPU time 461.38 seconds
Started May 05 02:57:11 PM PDT 24
Finished May 05 03:04:53 PM PDT 24
Peak memory 202284 kb
Host smart-a99416e1-3693-4139-98ea-012350ae35dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852555999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1852555999
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1292865226
Short name T580
Test name
Test status
Simulation time 105915762987 ps
CPU time 445.83 seconds
Started May 05 02:57:06 PM PDT 24
Finished May 05 03:04:32 PM PDT 24
Peak memory 202672 kb
Host smart-56b1d12d-354d-40cb-85a5-8b4363cecfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292865226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1292865226
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2684791786
Short name T476
Test name
Test status
Simulation time 22096721479 ps
CPU time 13.66 seconds
Started May 05 02:57:07 PM PDT 24
Finished May 05 02:57:21 PM PDT 24
Peak memory 202136 kb
Host smart-c8910408-7f82-4774-8f0f-db23edfa9cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684791786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2684791786
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3101318804
Short name T724
Test name
Test status
Simulation time 3688916336 ps
CPU time 2.68 seconds
Started May 05 02:57:10 PM PDT 24
Finished May 05 02:57:13 PM PDT 24
Peak memory 202120 kb
Host smart-c49e38f2-c293-4461-87a0-de588defe5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101318804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3101318804
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2482386475
Short name T438
Test name
Test status
Simulation time 5802696736 ps
CPU time 3.4 seconds
Started May 05 02:57:10 PM PDT 24
Finished May 05 02:57:14 PM PDT 24
Peak memory 202124 kb
Host smart-3b521135-320f-4ee1-be5b-91d0b7e0bcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482386475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2482386475
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2502054127
Short name T282
Test name
Test status
Simulation time 1166459238060 ps
CPU time 2963.39 seconds
Started May 05 02:57:09 PM PDT 24
Finished May 05 03:46:33 PM PDT 24
Peak memory 210924 kb
Host smart-8712b219-757e-4930-8f62-cf78923918eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502054127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2502054127
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3037866279
Short name T50
Test name
Test status
Simulation time 62186718616 ps
CPU time 148.34 seconds
Started May 05 02:57:07 PM PDT 24
Finished May 05 02:59:35 PM PDT 24
Peak memory 211056 kb
Host smart-e46b3ad2-70e6-4aeb-8372-16ebd2060d67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037866279 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3037866279
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2415621528
Short name T586
Test name
Test status
Simulation time 467638966 ps
CPU time 1.11 seconds
Started May 05 02:57:14 PM PDT 24
Finished May 05 02:57:16 PM PDT 24
Peak memory 202016 kb
Host smart-84e0f7e6-b5a2-432d-bf91-7577149d32c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415621528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2415621528
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.720915581
Short name T65
Test name
Test status
Simulation time 354030669438 ps
CPU time 80.6 seconds
Started May 05 02:57:06 PM PDT 24
Finished May 05 02:58:27 PM PDT 24
Peak memory 202320 kb
Host smart-a095e448-bb47-4001-bdc8-d71980ddc1c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720915581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.720915581
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.183687163
Short name T255
Test name
Test status
Simulation time 166134767440 ps
CPU time 107.51 seconds
Started May 05 02:57:07 PM PDT 24
Finished May 05 02:58:55 PM PDT 24
Peak memory 202420 kb
Host smart-71162191-4303-4763-8a3d-8a3911bfc65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183687163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.183687163
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2377324149
Short name T416
Test name
Test status
Simulation time 494704452131 ps
CPU time 1084.6 seconds
Started May 05 02:57:08 PM PDT 24
Finished May 05 03:15:13 PM PDT 24
Peak memory 202324 kb
Host smart-91654129-bfe4-4839-a3a3-eb4fd43a1567
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377324149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2377324149
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1106933362
Short name T539
Test name
Test status
Simulation time 164730332324 ps
CPU time 402.89 seconds
Started May 05 02:57:10 PM PDT 24
Finished May 05 03:03:53 PM PDT 24
Peak memory 202372 kb
Host smart-be719e3b-c4af-4488-ad30-f01776b0275e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106933362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1106933362
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.877108070
Short name T789
Test name
Test status
Simulation time 331683393308 ps
CPU time 360.03 seconds
Started May 05 02:57:10 PM PDT 24
Finished May 05 03:03:11 PM PDT 24
Peak memory 202260 kb
Host smart-e1a7792a-dd89-483b-a63f-1fe1c7ef36f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=877108070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.877108070
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2386423122
Short name T332
Test name
Test status
Simulation time 374255631063 ps
CPU time 906.34 seconds
Started May 05 02:57:11 PM PDT 24
Finished May 05 03:12:18 PM PDT 24
Peak memory 202360 kb
Host smart-a12ea65b-db47-45d3-b878-b1b3470fef1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386423122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2386423122
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3149991476
Short name T615
Test name
Test status
Simulation time 383323313057 ps
CPU time 907.42 seconds
Started May 05 02:57:08 PM PDT 24
Finished May 05 03:12:16 PM PDT 24
Peak memory 202384 kb
Host smart-3f0b3417-fdf1-4fff-b7cf-ef472f3c0d19
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149991476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3149991476
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3111702620
Short name T547
Test name
Test status
Simulation time 109659378826 ps
CPU time 399.48 seconds
Started May 05 02:57:08 PM PDT 24
Finished May 05 03:03:48 PM PDT 24
Peak memory 202648 kb
Host smart-d490ed61-5f64-4232-af0c-aa336a97ce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111702620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3111702620
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1124250224
Short name T512
Test name
Test status
Simulation time 29820743216 ps
CPU time 66.68 seconds
Started May 05 02:57:07 PM PDT 24
Finished May 05 02:58:14 PM PDT 24
Peak memory 202136 kb
Host smart-ff900d11-5f28-434f-a276-a57a8a5bd169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124250224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1124250224
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.441068631
Short name T752
Test name
Test status
Simulation time 2696257331 ps
CPU time 2.24 seconds
Started May 05 02:57:06 PM PDT 24
Finished May 05 02:57:09 PM PDT 24
Peak memory 202108 kb
Host smart-d8bc2403-d565-493b-838a-b89e2d34b10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441068631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.441068631
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2808121032
Short name T758
Test name
Test status
Simulation time 5823099905 ps
CPU time 9.83 seconds
Started May 05 02:57:07 PM PDT 24
Finished May 05 02:57:17 PM PDT 24
Peak memory 202304 kb
Host smart-2aac8d2e-87d0-4ac1-8354-a799bbe3db21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808121032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2808121032
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2361959102
Short name T761
Test name
Test status
Simulation time 666264535410 ps
CPU time 358.15 seconds
Started May 05 02:57:07 PM PDT 24
Finished May 05 03:03:05 PM PDT 24
Peak memory 202340 kb
Host smart-65a68cfa-9747-423e-bb2d-838b3543d882
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361959102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2361959102
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.4197146796
Short name T254
Test name
Test status
Simulation time 37306389182 ps
CPU time 76.89 seconds
Started May 05 02:57:06 PM PDT 24
Finished May 05 02:58:24 PM PDT 24
Peak memory 210972 kb
Host smart-910b78d0-ce26-422a-9370-d6bce461ab81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197146796 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.4197146796
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1889939869
Short name T716
Test name
Test status
Simulation time 483340804 ps
CPU time 1.7 seconds
Started May 05 02:57:16 PM PDT 24
Finished May 05 02:57:18 PM PDT 24
Peak memory 201992 kb
Host smart-6a014b2b-65b7-4fd9-ab05-665ee43b8029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889939869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1889939869
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2239723718
Short name T636
Test name
Test status
Simulation time 161643524394 ps
CPU time 93.51 seconds
Started May 05 02:57:14 PM PDT 24
Finished May 05 02:58:48 PM PDT 24
Peak memory 202384 kb
Host smart-5f20c318-2dc9-4043-8285-d78fa297e7fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239723718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2239723718
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2083797947
Short name T555
Test name
Test status
Simulation time 170952585840 ps
CPU time 91.63 seconds
Started May 05 02:57:13 PM PDT 24
Finished May 05 02:58:45 PM PDT 24
Peak memory 202352 kb
Host smart-909c0c0c-5a38-4303-9948-c05a7a68a60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083797947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2083797947
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.986497444
Short name T7
Test name
Test status
Simulation time 163682117622 ps
CPU time 412.53 seconds
Started May 05 02:57:12 PM PDT 24
Finished May 05 03:04:05 PM PDT 24
Peak memory 202296 kb
Host smart-a6121254-8cd9-406c-89fe-94bda35bc587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986497444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.986497444
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3746627605
Short name T32
Test name
Test status
Simulation time 324134565900 ps
CPU time 156.48 seconds
Started May 05 02:57:12 PM PDT 24
Finished May 05 02:59:48 PM PDT 24
Peak memory 202296 kb
Host smart-d1e324a6-c01d-42ec-a835-8c5062c35583
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746627605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3746627605
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3336937156
Short name T10
Test name
Test status
Simulation time 331024115876 ps
CPU time 391.68 seconds
Started May 05 02:57:08 PM PDT 24
Finished May 05 03:03:40 PM PDT 24
Peak memory 202388 kb
Host smart-4e291074-027b-4f01-a84c-935b147b4923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336937156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3336937156
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.708410383
Short name T393
Test name
Test status
Simulation time 170336529395 ps
CPU time 95.13 seconds
Started May 05 02:57:08 PM PDT 24
Finished May 05 02:58:44 PM PDT 24
Peak memory 202280 kb
Host smart-5ff0ad8b-37d8-48ae-8616-3da84524c871
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=708410383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.708410383
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1497909092
Short name T410
Test name
Test status
Simulation time 216344193064 ps
CPU time 134.55 seconds
Started May 05 02:57:15 PM PDT 24
Finished May 05 02:59:29 PM PDT 24
Peak memory 202304 kb
Host smart-7b750c08-ef0b-4ce2-bc57-83098fad9dc0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497909092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1497909092
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2488729999
Short name T494
Test name
Test status
Simulation time 86624906889 ps
CPU time 306.83 seconds
Started May 05 02:57:10 PM PDT 24
Finished May 05 03:02:17 PM PDT 24
Peak memory 202648 kb
Host smart-53407394-11dc-43bd-a1ae-5b20fa108a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488729999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2488729999
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2666642164
Short name T572
Test name
Test status
Simulation time 29916926324 ps
CPU time 12.82 seconds
Started May 05 02:57:14 PM PDT 24
Finished May 05 02:57:27 PM PDT 24
Peak memory 202140 kb
Host smart-c758ffe4-251f-4b5b-bc09-8494e28a22e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666642164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2666642164
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.740701441
Short name T147
Test name
Test status
Simulation time 2898515666 ps
CPU time 1.41 seconds
Started May 05 02:57:10 PM PDT 24
Finished May 05 02:57:12 PM PDT 24
Peak memory 202112 kb
Host smart-0c7dadfa-d037-4821-ac81-0ccbe31cc8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740701441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.740701441
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.4211149699
Short name T386
Test name
Test status
Simulation time 5804652094 ps
CPU time 3.91 seconds
Started May 05 02:57:09 PM PDT 24
Finished May 05 02:57:14 PM PDT 24
Peak memory 202108 kb
Host smart-fc7cc0e3-37df-4ee9-b689-49d6ad2d9cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211149699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.4211149699
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2811142719
Short name T281
Test name
Test status
Simulation time 171175136735 ps
CPU time 376.5 seconds
Started May 05 02:57:12 PM PDT 24
Finished May 05 03:03:29 PM PDT 24
Peak memory 202236 kb
Host smart-e2eb1a62-64a3-4b94-8c14-0ea23af09747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811142719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2811142719
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2341253806
Short name T535
Test name
Test status
Simulation time 141192204740 ps
CPU time 89.49 seconds
Started May 05 02:57:11 PM PDT 24
Finished May 05 02:58:41 PM PDT 24
Peak memory 202412 kb
Host smart-424d228e-f627-43d5-8412-25da35927df0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341253806 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2341253806
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3684436714
Short name T411
Test name
Test status
Simulation time 500983852 ps
CPU time 1.12 seconds
Started May 05 02:57:21 PM PDT 24
Finished May 05 02:57:23 PM PDT 24
Peak memory 202176 kb
Host smart-ecb105b3-82b4-43fe-be63-1d759450e74d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684436714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3684436714
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2160691229
Short name T266
Test name
Test status
Simulation time 340529672305 ps
CPU time 471.73 seconds
Started May 05 02:57:19 PM PDT 24
Finished May 05 03:05:11 PM PDT 24
Peak memory 202288 kb
Host smart-a89178db-4d3a-410e-84bd-8d06069c04c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160691229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2160691229
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3663036195
Short name T534
Test name
Test status
Simulation time 164020764643 ps
CPU time 387.04 seconds
Started May 05 02:57:14 PM PDT 24
Finished May 05 03:03:42 PM PDT 24
Peak memory 202276 kb
Host smart-28aec78f-64e9-4909-a289-b2714c0520cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663036195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3663036195
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.871375353
Short name T731
Test name
Test status
Simulation time 165640222615 ps
CPU time 94.05 seconds
Started May 05 02:57:15 PM PDT 24
Finished May 05 02:58:50 PM PDT 24
Peak memory 202220 kb
Host smart-9fdc2f31-032a-4cc2-b2f8-a6ce17239b32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=871375353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.871375353
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2276683993
Short name T163
Test name
Test status
Simulation time 329058757753 ps
CPU time 274.32 seconds
Started May 05 02:57:17 PM PDT 24
Finished May 05 03:01:52 PM PDT 24
Peak memory 202220 kb
Host smart-c062dbd1-b4e9-48f4-8941-ec3ef20f856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276683993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2276683993
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2969477535
Short name T670
Test name
Test status
Simulation time 336230173078 ps
CPU time 325.15 seconds
Started May 05 02:57:14 PM PDT 24
Finished May 05 03:02:40 PM PDT 24
Peak memory 202240 kb
Host smart-a3950086-2ef1-454a-b949-5403baf8f1e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969477535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2969477535
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3960400468
Short name T481
Test name
Test status
Simulation time 401865813555 ps
CPU time 435.03 seconds
Started May 05 02:57:14 PM PDT 24
Finished May 05 03:04:29 PM PDT 24
Peak memory 202272 kb
Host smart-6a78cc07-f75b-430b-9ff5-4909408922c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960400468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3960400468
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.489849320
Short name T372
Test name
Test status
Simulation time 85388162213 ps
CPU time 484.47 seconds
Started May 05 02:57:20 PM PDT 24
Finished May 05 03:05:25 PM PDT 24
Peak memory 202652 kb
Host smart-73a381a7-8250-4c56-abc1-4299c6507b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489849320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.489849320
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3255709966
Short name T629
Test name
Test status
Simulation time 43774579241 ps
CPU time 20.02 seconds
Started May 05 02:57:21 PM PDT 24
Finished May 05 02:57:41 PM PDT 24
Peak memory 202152 kb
Host smart-7921ccb4-cb0a-4f97-bf99-f87241d9ddfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255709966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3255709966
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1351077286
Short name T414
Test name
Test status
Simulation time 3291147198 ps
CPU time 2.62 seconds
Started May 05 02:57:21 PM PDT 24
Finished May 05 02:57:24 PM PDT 24
Peak memory 202072 kb
Host smart-09de14ab-f15e-4ed3-a43a-54110c1a04df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351077286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1351077286
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2271878066
Short name T465
Test name
Test status
Simulation time 5740125987 ps
CPU time 4.19 seconds
Started May 05 02:57:15 PM PDT 24
Finished May 05 02:57:20 PM PDT 24
Peak memory 202136 kb
Host smart-b75b91f0-930d-4e98-8737-b5766aa92dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271878066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2271878066
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3619919485
Short name T687
Test name
Test status
Simulation time 517881311147 ps
CPU time 178.81 seconds
Started May 05 02:57:21 PM PDT 24
Finished May 05 03:00:21 PM PDT 24
Peak memory 202372 kb
Host smart-92fbbbc3-2956-4cb0-86f8-de0fe3848c92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619919485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3619919485
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2712830065
Short name T760
Test name
Test status
Simulation time 42650987592 ps
CPU time 102.29 seconds
Started May 05 02:57:21 PM PDT 24
Finished May 05 02:59:03 PM PDT 24
Peak memory 211036 kb
Host smart-eafe7816-0aed-4036-bab0-9b3f1f2e2a7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712830065 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2712830065
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2417099602
Short name T511
Test name
Test status
Simulation time 530790318 ps
CPU time 1.79 seconds
Started May 05 02:57:26 PM PDT 24
Finished May 05 02:57:29 PM PDT 24
Peak memory 202012 kb
Host smart-b74a64b6-049e-4ca0-8db8-c38179de75f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417099602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2417099602
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1711582702
Short name T744
Test name
Test status
Simulation time 332513538537 ps
CPU time 175.06 seconds
Started May 05 02:57:27 PM PDT 24
Finished May 05 03:00:22 PM PDT 24
Peak memory 202280 kb
Host smart-9a84a844-9cf3-4c7b-8c24-50ba633bebdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711582702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1711582702
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3903195352
Short name T191
Test name
Test status
Simulation time 508416973608 ps
CPU time 278.95 seconds
Started May 05 02:57:24 PM PDT 24
Finished May 05 03:02:04 PM PDT 24
Peak memory 202300 kb
Host smart-db2a9a88-34c2-4b5c-a22b-66ecffc2b17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903195352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3903195352
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1485908258
Short name T674
Test name
Test status
Simulation time 484578898819 ps
CPU time 328.58 seconds
Started May 05 02:57:28 PM PDT 24
Finished May 05 03:02:57 PM PDT 24
Peak memory 202296 kb
Host smart-7a06b147-89ec-4d53-938c-919522edd586
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485908258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1485908258
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.380249466
Short name T154
Test name
Test status
Simulation time 490126253967 ps
CPU time 564.2 seconds
Started May 05 02:57:27 PM PDT 24
Finished May 05 03:06:52 PM PDT 24
Peak memory 202200 kb
Host smart-433a369d-f4a2-4ccd-97c5-71043886f8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380249466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.380249466
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3679323923
Short name T656
Test name
Test status
Simulation time 327617502574 ps
CPU time 812.05 seconds
Started May 05 02:57:24 PM PDT 24
Finished May 05 03:10:57 PM PDT 24
Peak memory 202268 kb
Host smart-c06f40e0-be45-4bcf-a470-4c78127a2ebf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679323923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3679323923
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3532066070
Short name T157
Test name
Test status
Simulation time 578876023148 ps
CPU time 998.39 seconds
Started May 05 02:57:24 PM PDT 24
Finished May 05 03:14:03 PM PDT 24
Peak memory 202384 kb
Host smart-5dccd55b-5310-4ddb-8883-476c3eb305c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532066070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3532066070
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3443386529
Short name T623
Test name
Test status
Simulation time 201388202486 ps
CPU time 468.37 seconds
Started May 05 02:57:27 PM PDT 24
Finished May 05 03:05:16 PM PDT 24
Peak memory 202220 kb
Host smart-f79df7c3-e757-4996-8485-44bc1a8794bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443386529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3443386529
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2363961483
Short name T790
Test name
Test status
Simulation time 117724866517 ps
CPU time 585.85 seconds
Started May 05 02:57:27 PM PDT 24
Finished May 05 03:07:13 PM PDT 24
Peak memory 202636 kb
Host smart-f904ca3f-b936-4ec6-a8e5-650da81eacc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363961483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2363961483
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2309648175
Short name T159
Test name
Test status
Simulation time 47641736927 ps
CPU time 31.02 seconds
Started May 05 02:57:28 PM PDT 24
Finished May 05 02:57:59 PM PDT 24
Peak memory 202112 kb
Host smart-ee2acf71-f6f1-4a72-af67-cab814ce6a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309648175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2309648175
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3328969942
Short name T548
Test name
Test status
Simulation time 4004758561 ps
CPU time 9.57 seconds
Started May 05 02:57:23 PM PDT 24
Finished May 05 02:57:33 PM PDT 24
Peak memory 202116 kb
Host smart-1f4c2fcc-1f57-4ea1-b4bc-7e019bf7b732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328969942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3328969942
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2117311125
Short name T3
Test name
Test status
Simulation time 5601006539 ps
CPU time 3.77 seconds
Started May 05 02:57:23 PM PDT 24
Finished May 05 02:57:27 PM PDT 24
Peak memory 202068 kb
Host smart-16147eb7-c339-4c68-be5a-2412e0005227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117311125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2117311125
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1284266365
Short name T783
Test name
Test status
Simulation time 623653121734 ps
CPU time 1726.3 seconds
Started May 05 02:57:28 PM PDT 24
Finished May 05 03:26:14 PM PDT 24
Peak memory 210784 kb
Host smart-e48a4790-81eb-431c-bdc4-c02dbab29b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284266365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1284266365
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2282680725
Short name T252
Test name
Test status
Simulation time 94028702832 ps
CPU time 127.64 seconds
Started May 05 02:57:28 PM PDT 24
Finished May 05 02:59:36 PM PDT 24
Peak memory 202484 kb
Host smart-72ea42c6-2016-4dd4-a2e6-dc40f7911c10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282680725 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2282680725
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1805746564
Short name T737
Test name
Test status
Simulation time 295303233 ps
CPU time 0.94 seconds
Started May 05 02:57:39 PM PDT 24
Finished May 05 02:57:40 PM PDT 24
Peak memory 202016 kb
Host smart-adaa6bcd-693f-46ef-9412-4433125880a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805746564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1805746564
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2108879825
Short name T655
Test name
Test status
Simulation time 197026819383 ps
CPU time 89.57 seconds
Started May 05 02:57:37 PM PDT 24
Finished May 05 02:59:07 PM PDT 24
Peak memory 202280 kb
Host smart-04d7c7aa-3081-4408-8866-20164fe3f12e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108879825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2108879825
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1999199268
Short name T610
Test name
Test status
Simulation time 346002596005 ps
CPU time 790.73 seconds
Started May 05 02:57:35 PM PDT 24
Finished May 05 03:10:47 PM PDT 24
Peak memory 202272 kb
Host smart-635ef945-8971-4641-9dce-666201ae5c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999199268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1999199268
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1378890114
Short name T207
Test name
Test status
Simulation time 490124675030 ps
CPU time 609.65 seconds
Started May 05 02:57:30 PM PDT 24
Finished May 05 03:07:40 PM PDT 24
Peak memory 202384 kb
Host smart-45c81b85-6e7b-4377-82de-1bce48bc0b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378890114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1378890114
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.974558998
Short name T558
Test name
Test status
Simulation time 331442845640 ps
CPU time 197.93 seconds
Started May 05 02:57:27 PM PDT 24
Finished May 05 03:00:45 PM PDT 24
Peak memory 202292 kb
Host smart-8ee8b56c-2a92-4aad-9be9-e135f3505c99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=974558998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.974558998
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2977249039
Short name T738
Test name
Test status
Simulation time 161403037256 ps
CPU time 288.2 seconds
Started May 05 02:57:28 PM PDT 24
Finished May 05 03:02:17 PM PDT 24
Peak memory 202252 kb
Host smart-8412d374-9508-43c6-abdf-8337a7fd58e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977249039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2977249039
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1384097055
Short name T579
Test name
Test status
Simulation time 493780671342 ps
CPU time 529.48 seconds
Started May 05 02:57:27 PM PDT 24
Finished May 05 03:06:17 PM PDT 24
Peak memory 202200 kb
Host smart-ed0f5935-838b-47ba-b18a-e7d23e63507a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384097055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1384097055
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3384136583
Short name T178
Test name
Test status
Simulation time 165541910932 ps
CPU time 68.26 seconds
Started May 05 02:57:27 PM PDT 24
Finished May 05 02:58:36 PM PDT 24
Peak memory 202396 kb
Host smart-dee351dc-2b40-40fb-aac5-e3151645fb65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384136583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3384136583
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3223029892
Short name T28
Test name
Test status
Simulation time 383434599981 ps
CPU time 50.64 seconds
Started May 05 02:57:33 PM PDT 24
Finished May 05 02:58:24 PM PDT 24
Peak memory 202284 kb
Host smart-40d7c8b7-6024-4746-a2de-f96268960802
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223029892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3223029892
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1405302976
Short name T239
Test name
Test status
Simulation time 129059957034 ps
CPU time 461.2 seconds
Started May 05 02:57:36 PM PDT 24
Finished May 05 03:05:18 PM PDT 24
Peak memory 202748 kb
Host smart-222f5d1c-ed06-40ff-9943-d8c3386af734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405302976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1405302976
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1716421794
Short name T394
Test name
Test status
Simulation time 28379088592 ps
CPU time 64.76 seconds
Started May 05 02:57:36 PM PDT 24
Finished May 05 02:58:41 PM PDT 24
Peak memory 202108 kb
Host smart-b65765ff-c1a7-436a-83b5-383c054e61bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716421794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1716421794
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.291301253
Short name T425
Test name
Test status
Simulation time 5501028239 ps
CPU time 13.35 seconds
Started May 05 02:57:31 PM PDT 24
Finished May 05 02:57:45 PM PDT 24
Peak memory 202132 kb
Host smart-adc77048-f0f8-4a90-91e2-6c8842ac46c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291301253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.291301253
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3022662256
Short name T577
Test name
Test status
Simulation time 5779917880 ps
CPU time 2.95 seconds
Started May 05 02:57:30 PM PDT 24
Finished May 05 02:57:33 PM PDT 24
Peak memory 202048 kb
Host smart-790c9a22-b9d9-4e3d-8031-196b3181a2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022662256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3022662256
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2866819660
Short name T505
Test name
Test status
Simulation time 11133210068 ps
CPU time 27.02 seconds
Started May 05 02:57:39 PM PDT 24
Finished May 05 02:58:06 PM PDT 24
Peak memory 202036 kb
Host smart-a6d0e0f5-77ff-4d90-875c-57e93415f4b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866819660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2866819660
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1579436155
Short name T685
Test name
Test status
Simulation time 138749285868 ps
CPU time 50.33 seconds
Started May 05 02:57:38 PM PDT 24
Finished May 05 02:58:29 PM PDT 24
Peak memory 210600 kb
Host smart-1f4b4bd3-3147-4ae0-9646-0dac636e9121
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579436155 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1579436155
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1862099527
Short name T631
Test name
Test status
Simulation time 511510518 ps
CPU time 0.79 seconds
Started May 05 02:57:41 PM PDT 24
Finished May 05 02:57:42 PM PDT 24
Peak memory 201976 kb
Host smart-db2586b3-85d3-4781-891c-d213ca869f4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862099527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1862099527
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.299995553
Short name T246
Test name
Test status
Simulation time 161927145894 ps
CPU time 97.02 seconds
Started May 05 02:57:37 PM PDT 24
Finished May 05 02:59:15 PM PDT 24
Peak memory 202312 kb
Host smart-f08dfac4-ecff-4fdf-8454-361653380de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299995553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.299995553
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1160931366
Short name T764
Test name
Test status
Simulation time 167306740637 ps
CPU time 352.43 seconds
Started May 05 02:57:40 PM PDT 24
Finished May 05 03:03:33 PM PDT 24
Peak memory 202240 kb
Host smart-28df860d-89dc-4ce1-bb44-ebdf2173b56e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160931366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1160931366
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3155161127
Short name T613
Test name
Test status
Simulation time 162163512751 ps
CPU time 108.9 seconds
Started May 05 02:57:36 PM PDT 24
Finished May 05 02:59:26 PM PDT 24
Peak memory 202340 kb
Host smart-39367dce-956a-4377-beba-50664bf2e4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155161127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3155161127
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1186058815
Short name T516
Test name
Test status
Simulation time 166454420689 ps
CPU time 395.73 seconds
Started May 05 02:57:36 PM PDT 24
Finished May 05 03:04:12 PM PDT 24
Peak memory 202260 kb
Host smart-19f4670a-7e50-4a04-b7f5-e7b31948cc60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186058815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1186058815
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3085537937
Short name T723
Test name
Test status
Simulation time 567996623130 ps
CPU time 89.92 seconds
Started May 05 02:57:41 PM PDT 24
Finished May 05 02:59:11 PM PDT 24
Peak memory 202236 kb
Host smart-d8e1205b-fab1-4e97-aa86-075ba129762d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085537937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3085537937
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.681755990
Short name T412
Test name
Test status
Simulation time 400474221897 ps
CPU time 237.18 seconds
Started May 05 02:57:41 PM PDT 24
Finished May 05 03:01:39 PM PDT 24
Peak memory 202276 kb
Host smart-a03f3cd1-857c-4cc9-a98b-237894780129
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681755990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.681755990
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.4285235971
Short name T483
Test name
Test status
Simulation time 84202937324 ps
CPU time 339.37 seconds
Started May 05 02:57:41 PM PDT 24
Finished May 05 03:03:20 PM PDT 24
Peak memory 202684 kb
Host smart-875eb7ec-6357-4d15-9cfc-6c3f8d7da0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285235971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4285235971
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2124965143
Short name T44
Test name
Test status
Simulation time 23254764209 ps
CPU time 14.99 seconds
Started May 05 02:57:41 PM PDT 24
Finished May 05 02:57:56 PM PDT 24
Peak memory 202092 kb
Host smart-534db348-a1b4-4bd7-a8c7-0ced838b5362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124965143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2124965143
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.158400149
Short name T551
Test name
Test status
Simulation time 4422443528 ps
CPU time 11.19 seconds
Started May 05 02:57:40 PM PDT 24
Finished May 05 02:57:52 PM PDT 24
Peak memory 202120 kb
Host smart-3fd6803d-b1f1-46f8-a582-908f707363bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158400149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.158400149
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3664038624
Short name T206
Test name
Test status
Simulation time 5917510572 ps
CPU time 7.53 seconds
Started May 05 02:57:38 PM PDT 24
Finished May 05 02:57:46 PM PDT 24
Peak memory 202144 kb
Host smart-d3390605-0d54-4379-89f7-333b0a7b26f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664038624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3664038624
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2958530514
Short name T375
Test name
Test status
Simulation time 541431860921 ps
CPU time 1005.09 seconds
Started May 05 02:57:42 PM PDT 24
Finished May 05 03:14:27 PM PDT 24
Peak memory 210912 kb
Host smart-0ae279ec-0dfe-4ed6-8cb4-708286ef26d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958530514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2958530514
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2522485528
Short name T762
Test name
Test status
Simulation time 412760992 ps
CPU time 0.84 seconds
Started May 05 02:51:34 PM PDT 24
Finished May 05 02:51:36 PM PDT 24
Peak memory 202008 kb
Host smart-37e60cef-73c8-430d-9157-102de6a1445c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522485528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2522485528
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1297021606
Short name T337
Test name
Test status
Simulation time 597405537788 ps
CPU time 118.28 seconds
Started May 05 02:51:29 PM PDT 24
Finished May 05 02:53:28 PM PDT 24
Peak memory 202328 kb
Host smart-f9d58462-f190-4e24-9723-8e2c7604bace
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297021606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1297021606
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1575758908
Short name T249
Test name
Test status
Simulation time 165987779497 ps
CPU time 383.48 seconds
Started May 05 02:51:29 PM PDT 24
Finished May 05 02:57:53 PM PDT 24
Peak memory 202308 kb
Host smart-734243f8-9778-49d8-8794-4f39b32d395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575758908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1575758908
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3467631113
Short name T341
Test name
Test status
Simulation time 324582499589 ps
CPU time 563.1 seconds
Started May 05 02:51:25 PM PDT 24
Finished May 05 03:00:48 PM PDT 24
Peak memory 202308 kb
Host smart-89b8cfc8-e7bd-4e3a-81e5-d43ad20bc68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467631113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3467631113
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3083833258
Short name T699
Test name
Test status
Simulation time 167225316339 ps
CPU time 230.18 seconds
Started May 05 02:51:24 PM PDT 24
Finished May 05 02:55:15 PM PDT 24
Peak memory 202268 kb
Host smart-ebe743aa-4117-4034-8f69-8371b55e5e73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083833258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3083833258
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3904499554
Short name T174
Test name
Test status
Simulation time 484002898837 ps
CPU time 284.62 seconds
Started May 05 02:51:25 PM PDT 24
Finished May 05 02:56:10 PM PDT 24
Peak memory 202360 kb
Host smart-02784608-6452-4512-9b2c-f0477bca3d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904499554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3904499554
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3627187967
Short name T582
Test name
Test status
Simulation time 170599459196 ps
CPU time 388.45 seconds
Started May 05 02:51:23 PM PDT 24
Finished May 05 02:57:52 PM PDT 24
Peak memory 202308 kb
Host smart-b9c227c0-5b6a-4f06-b0f8-3a34ad984726
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627187967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3627187967
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.447357354
Short name T650
Test name
Test status
Simulation time 351106962012 ps
CPU time 393.85 seconds
Started May 05 02:51:28 PM PDT 24
Finished May 05 02:58:03 PM PDT 24
Peak memory 202292 kb
Host smart-5b96abc0-ea2f-48f7-a6e4-9376cd52a75c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447357354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.447357354
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2988353804
Short name T426
Test name
Test status
Simulation time 199102529806 ps
CPU time 113.6 seconds
Started May 05 02:51:29 PM PDT 24
Finished May 05 02:53:23 PM PDT 24
Peak memory 202300 kb
Host smart-00136299-3210-4c01-97dc-7480afeb46bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988353804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2988353804
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.967843686
Short name T377
Test name
Test status
Simulation time 139469275992 ps
CPU time 440.9 seconds
Started May 05 02:51:31 PM PDT 24
Finished May 05 02:58:52 PM PDT 24
Peak memory 202644 kb
Host smart-3cba8e22-2acf-4d2a-ae7c-1aa46ad8335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967843686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.967843686
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.787119680
Short name T474
Test name
Test status
Simulation time 36885410711 ps
CPU time 46.43 seconds
Started May 05 02:51:29 PM PDT 24
Finished May 05 02:52:16 PM PDT 24
Peak memory 202112 kb
Host smart-34009e0a-23fe-4d9e-84a0-74708e794d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787119680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.787119680
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.333333811
Short name T745
Test name
Test status
Simulation time 2953849051 ps
CPU time 7.65 seconds
Started May 05 02:51:29 PM PDT 24
Finished May 05 02:51:37 PM PDT 24
Peak memory 202128 kb
Host smart-6f5a77b9-9320-4499-a136-f4deb58a50d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333333811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.333333811
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2038615763
Short name T439
Test name
Test status
Simulation time 5838886234 ps
CPU time 4.42 seconds
Started May 05 02:51:27 PM PDT 24
Finished May 05 02:51:32 PM PDT 24
Peak memory 202148 kb
Host smart-2a891936-f4eb-45cf-adee-94aaca06a965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038615763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2038615763
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1122428533
Short name T321
Test name
Test status
Simulation time 215875548312 ps
CPU time 491.92 seconds
Started May 05 02:51:34 PM PDT 24
Finished May 05 02:59:47 PM PDT 24
Peak memory 202336 kb
Host smart-abcb5dea-7bdf-463b-9e13-a4012f743732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122428533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1122428533
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2816001289
Short name T618
Test name
Test status
Simulation time 67008933663 ps
CPU time 121.4 seconds
Started May 05 02:51:30 PM PDT 24
Finished May 05 02:53:32 PM PDT 24
Peak memory 210612 kb
Host smart-043abe86-84fe-46de-bafc-3b5e6c40ba70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816001289 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2816001289
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.674185314
Short name T215
Test name
Test status
Simulation time 547914263 ps
CPU time 0.78 seconds
Started May 05 02:51:39 PM PDT 24
Finished May 05 02:51:41 PM PDT 24
Peak memory 202016 kb
Host smart-99331265-720d-4703-8174-bafff8da767d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674185314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.674185314
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2360212913
Short name T508
Test name
Test status
Simulation time 325180590721 ps
CPU time 463.42 seconds
Started May 05 02:51:36 PM PDT 24
Finished May 05 02:59:20 PM PDT 24
Peak memory 202300 kb
Host smart-8e91396e-1852-45a8-98d5-bacbe83ce379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360212913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2360212913
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3274287595
Short name T576
Test name
Test status
Simulation time 490065025661 ps
CPU time 294.81 seconds
Started May 05 02:51:34 PM PDT 24
Finished May 05 02:56:29 PM PDT 24
Peak memory 202276 kb
Host smart-8db0f79c-c827-4289-abe1-19b8ba61ef10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274287595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3274287595
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2333207459
Short name T355
Test name
Test status
Simulation time 504235186679 ps
CPU time 1190.68 seconds
Started May 05 02:51:35 PM PDT 24
Finished May 05 03:11:27 PM PDT 24
Peak memory 202368 kb
Host smart-769729e0-5b0b-466b-bd03-5b7142461011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333207459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2333207459
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1630469819
Short name T450
Test name
Test status
Simulation time 495765413511 ps
CPU time 1008.34 seconds
Started May 05 02:51:35 PM PDT 24
Finished May 05 03:08:25 PM PDT 24
Peak memory 202296 kb
Host smart-ee063125-8277-482b-ae4b-e87dc6dc8958
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630469819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1630469819
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3565887019
Short name T488
Test name
Test status
Simulation time 172448277181 ps
CPU time 361.95 seconds
Started May 05 02:51:35 PM PDT 24
Finished May 05 02:57:37 PM PDT 24
Peak memory 202400 kb
Host smart-a48c8996-38d3-4fdc-98e8-d6857246a33f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565887019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3565887019
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3160795011
Short name T779
Test name
Test status
Simulation time 609351559304 ps
CPU time 735.73 seconds
Started May 05 02:51:34 PM PDT 24
Finished May 05 03:03:50 PM PDT 24
Peak memory 202288 kb
Host smart-8369eca0-81e9-4591-b006-c607e3b38552
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160795011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3160795011
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2123893716
Short name T695
Test name
Test status
Simulation time 66690624855 ps
CPU time 244.74 seconds
Started May 05 02:51:39 PM PDT 24
Finished May 05 02:55:44 PM PDT 24
Peak memory 202640 kb
Host smart-0171e6f0-10a2-4d53-8c76-b84030bcd662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123893716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2123893716
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2636111173
Short name T418
Test name
Test status
Simulation time 25490235862 ps
CPU time 54.4 seconds
Started May 05 02:51:42 PM PDT 24
Finished May 05 02:52:36 PM PDT 24
Peak memory 202124 kb
Host smart-f5f8c341-02ff-4e9d-b220-31bf8236f4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636111173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2636111173
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2318633928
Short name T456
Test name
Test status
Simulation time 4483760602 ps
CPU time 3.31 seconds
Started May 05 02:51:39 PM PDT 24
Finished May 05 02:51:43 PM PDT 24
Peak memory 202092 kb
Host smart-1f8368eb-d3a8-4bf5-b748-651a84b784b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318633928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2318633928
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.80455768
Short name T392
Test name
Test status
Simulation time 5795748970 ps
CPU time 4.29 seconds
Started May 05 02:51:35 PM PDT 24
Finished May 05 02:51:40 PM PDT 24
Peak memory 202140 kb
Host smart-dad245a3-2881-4cc1-90cb-9d2250a98465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80455768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.80455768
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1679484965
Short name T374
Test name
Test status
Simulation time 118231892265 ps
CPU time 372.75 seconds
Started May 05 02:51:39 PM PDT 24
Finished May 05 02:57:53 PM PDT 24
Peak memory 202728 kb
Host smart-1a30f82a-5919-476e-98c8-51e0467ddc14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679484965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1679484965
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.763748097
Short name T364
Test name
Test status
Simulation time 307955210255 ps
CPU time 52.8 seconds
Started May 05 02:51:37 PM PDT 24
Finished May 05 02:52:31 PM PDT 24
Peak memory 210632 kb
Host smart-9a6c4395-002f-4639-aff5-2fc8ca1ddeab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763748097 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.763748097
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2123005762
Short name T78
Test name
Test status
Simulation time 367969539 ps
CPU time 1.02 seconds
Started May 05 02:51:43 PM PDT 24
Finished May 05 02:51:44 PM PDT 24
Peak memory 202004 kb
Host smart-9ceb3df3-6459-4f4c-9b83-4b24c0e08903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123005762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2123005762
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1463825363
Short name T309
Test name
Test status
Simulation time 355637359929 ps
CPU time 736.47 seconds
Started May 05 02:51:44 PM PDT 24
Finished May 05 03:04:01 PM PDT 24
Peak memory 202108 kb
Host smart-e512da76-e87c-47b0-8c6c-73ae11400bb3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463825363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1463825363
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2940785459
Short name T556
Test name
Test status
Simulation time 359751283022 ps
CPU time 221.69 seconds
Started May 05 02:51:37 PM PDT 24
Finished May 05 02:55:20 PM PDT 24
Peak memory 202304 kb
Host smart-f459fdc0-1747-4a15-9f54-c1b4d5a080ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940785459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2940785459
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1978181301
Short name T602
Test name
Test status
Simulation time 162451882580 ps
CPU time 380.67 seconds
Started May 05 02:51:38 PM PDT 24
Finished May 05 02:57:59 PM PDT 24
Peak memory 202356 kb
Host smart-16b4577b-c93a-467b-ac56-b0868bf9208a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978181301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1978181301
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2115168325
Short name T666
Test name
Test status
Simulation time 330107214346 ps
CPU time 829.99 seconds
Started May 05 02:51:39 PM PDT 24
Finished May 05 03:05:30 PM PDT 24
Peak memory 202336 kb
Host smart-6753f7da-fba1-4ed2-afc4-37e782fc81b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115168325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2115168325
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3101873151
Short name T770
Test name
Test status
Simulation time 497851228281 ps
CPU time 270.46 seconds
Started May 05 02:51:40 PM PDT 24
Finished May 05 02:56:11 PM PDT 24
Peak memory 202276 kb
Host smart-c953edd9-697d-49df-a56d-5d6aad7cd279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101873151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3101873151
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2252478744
Short name T536
Test name
Test status
Simulation time 487237375801 ps
CPU time 576.58 seconds
Started May 05 02:51:40 PM PDT 24
Finished May 05 03:01:17 PM PDT 24
Peak memory 202416 kb
Host smart-1d252e8e-f66e-4409-885b-2c7de2cc1cd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252478744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2252478744
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3053053205
Short name T792
Test name
Test status
Simulation time 203245753755 ps
CPU time 450.88 seconds
Started May 05 02:51:41 PM PDT 24
Finished May 05 02:59:12 PM PDT 24
Peak memory 202232 kb
Host smart-b44eb9ad-41a6-40f4-beb5-99e5ac58fabe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053053205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3053053205
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.187031218
Short name T528
Test name
Test status
Simulation time 127797296510 ps
CPU time 482.21 seconds
Started May 05 02:51:44 PM PDT 24
Finished May 05 02:59:47 PM PDT 24
Peak memory 202624 kb
Host smart-9b6642c9-693b-418d-bbc8-d05c21470689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187031218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.187031218
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.671459663
Short name T540
Test name
Test status
Simulation time 44062748752 ps
CPU time 28.38 seconds
Started May 05 02:51:42 PM PDT 24
Finished May 05 02:52:11 PM PDT 24
Peak memory 202132 kb
Host smart-711159aa-6f0d-48ed-9ef1-1f10c25a97ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671459663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.671459663
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1051744255
Short name T639
Test name
Test status
Simulation time 4703799995 ps
CPU time 1.91 seconds
Started May 05 02:51:41 PM PDT 24
Finished May 05 02:51:43 PM PDT 24
Peak memory 202128 kb
Host smart-8798bdfd-cec3-4c45-bb50-a76812c85862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051744255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1051744255
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2764496520
Short name T4
Test name
Test status
Simulation time 5788842464 ps
CPU time 13.83 seconds
Started May 05 02:51:38 PM PDT 24
Finished May 05 02:51:52 PM PDT 24
Peak memory 202116 kb
Host smart-bee16de1-a90c-4123-b6da-c5b0a1a3c467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764496520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2764496520
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.388492391
Short name T302
Test name
Test status
Simulation time 346864423741 ps
CPU time 785.19 seconds
Started May 05 02:51:43 PM PDT 24
Finished May 05 03:04:48 PM PDT 24
Peak memory 202312 kb
Host smart-8e821ae0-a874-4574-8c89-c8e2b132f0ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388492391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.388492391
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.588091339
Short name T753
Test name
Test status
Simulation time 353050977 ps
CPU time 0.88 seconds
Started May 05 02:51:42 PM PDT 24
Finished May 05 02:51:44 PM PDT 24
Peak memory 201936 kb
Host smart-80e60919-cff1-40af-b248-274f20a9a50f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588091339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.588091339
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.4279299360
Short name T225
Test name
Test status
Simulation time 540123247703 ps
CPU time 309.92 seconds
Started May 05 02:51:47 PM PDT 24
Finished May 05 02:56:58 PM PDT 24
Peak memory 202224 kb
Host smart-769b3999-8847-4d77-9124-4a14a08a860b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279299360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.4279299360
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.31785944
Short name T661
Test name
Test status
Simulation time 495753274259 ps
CPU time 1033.63 seconds
Started May 05 02:51:49 PM PDT 24
Finished May 05 03:09:03 PM PDT 24
Peak memory 202272 kb
Host smart-40122905-dfc9-4d33-a230-190f752afcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31785944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.31785944
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.707693038
Short name T339
Test name
Test status
Simulation time 493685659700 ps
CPU time 229.04 seconds
Started May 05 02:51:42 PM PDT 24
Finished May 05 02:55:31 PM PDT 24
Peak memory 202264 kb
Host smart-de3a67bf-38d9-4252-81a4-3f00950bb52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707693038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.707693038
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2067283307
Short name T630
Test name
Test status
Simulation time 326814176752 ps
CPU time 386.84 seconds
Started May 05 02:51:45 PM PDT 24
Finished May 05 02:58:12 PM PDT 24
Peak memory 202296 kb
Host smart-b80503f0-b4c5-49db-8e02-683b7b03ace8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067283307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2067283307
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2227155424
Short name T390
Test name
Test status
Simulation time 484355434841 ps
CPU time 92.32 seconds
Started May 05 02:51:42 PM PDT 24
Finished May 05 02:53:15 PM PDT 24
Peak memory 202304 kb
Host smart-4698e2ce-d13b-445b-9e6c-e7890724de4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227155424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2227155424
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2115931351
Short name T168
Test name
Test status
Simulation time 193073286834 ps
CPU time 120.94 seconds
Started May 05 02:51:45 PM PDT 24
Finished May 05 02:53:46 PM PDT 24
Peak memory 202392 kb
Host smart-63d48ba1-f72b-453c-b42a-c9837c3e2c7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115931351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2115931351
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.246429068
Short name T538
Test name
Test status
Simulation time 204563626200 ps
CPU time 239.97 seconds
Started May 05 02:51:47 PM PDT 24
Finished May 05 02:55:47 PM PDT 24
Peak memory 202256 kb
Host smart-42d6a9bf-00a3-4646-8389-e156962eaf3c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246429068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.246429068
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2790788520
Short name T690
Test name
Test status
Simulation time 71443822752 ps
CPU time 255.03 seconds
Started May 05 02:51:47 PM PDT 24
Finished May 05 02:56:02 PM PDT 24
Peak memory 202648 kb
Host smart-fba2ba6e-39b5-4ead-9395-2c9453f8ce0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790788520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2790788520
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3563760614
Short name T380
Test name
Test status
Simulation time 40737449908 ps
CPU time 24.77 seconds
Started May 05 02:51:46 PM PDT 24
Finished May 05 02:52:11 PM PDT 24
Peak memory 202104 kb
Host smart-73d27ff4-ec67-4aa8-b0a3-eb2f96d70773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563760614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3563760614
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3637787139
Short name T563
Test name
Test status
Simulation time 4023860147 ps
CPU time 9.68 seconds
Started May 05 02:51:41 PM PDT 24
Finished May 05 02:51:51 PM PDT 24
Peak memory 202128 kb
Host smart-4301d792-efaa-4269-b22e-01efcc9ba58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637787139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3637787139
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1603944880
Short name T526
Test name
Test status
Simulation time 5970637663 ps
CPU time 3.98 seconds
Started May 05 02:51:42 PM PDT 24
Finished May 05 02:51:46 PM PDT 24
Peak memory 202068 kb
Host smart-33b4c0b0-3594-4797-bf6a-a02cff5f18e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603944880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1603944880
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2690593891
Short name T95
Test name
Test status
Simulation time 308641940057 ps
CPU time 436.81 seconds
Started May 05 02:51:42 PM PDT 24
Finished May 05 02:59:00 PM PDT 24
Peak memory 210900 kb
Host smart-f413d159-019d-4917-8624-bb234ad56b89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690593891 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2690593891
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1364835026
Short name T795
Test name
Test status
Simulation time 422261513 ps
CPU time 0.83 seconds
Started May 05 02:51:52 PM PDT 24
Finished May 05 02:51:53 PM PDT 24
Peak memory 201956 kb
Host smart-04ff9665-de9d-467c-a3cc-651218d2578d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364835026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1364835026
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1429195369
Short name T274
Test name
Test status
Simulation time 166875253467 ps
CPU time 26.52 seconds
Started May 05 02:51:48 PM PDT 24
Finished May 05 02:52:15 PM PDT 24
Peak memory 202260 kb
Host smart-79a68b09-c46e-461c-8eb4-1b5fd8ab79c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429195369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1429195369
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.723289584
Short name T343
Test name
Test status
Simulation time 383060484360 ps
CPU time 215.54 seconds
Started May 05 02:51:48 PM PDT 24
Finished May 05 02:55:24 PM PDT 24
Peak memory 202368 kb
Host smart-1521ef58-3ee5-4b48-8e6e-f4b49aa3cab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723289584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.723289584
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1172061292
Short name T703
Test name
Test status
Simulation time 162643559758 ps
CPU time 100.05 seconds
Started May 05 02:51:48 PM PDT 24
Finished May 05 02:53:28 PM PDT 24
Peak memory 202388 kb
Host smart-2f338a51-6bef-4ab3-aef1-6bf839a62a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172061292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1172061292
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2923591132
Short name T285
Test name
Test status
Simulation time 338717554429 ps
CPU time 806.1 seconds
Started May 05 02:51:45 PM PDT 24
Finished May 05 03:05:12 PM PDT 24
Peak memory 202236 kb
Host smart-e6b7caa8-4d9a-49c5-8f01-63f7ecd2341d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923591132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2923591132
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3731473032
Short name T669
Test name
Test status
Simulation time 331934255985 ps
CPU time 844.54 seconds
Started May 05 02:51:48 PM PDT 24
Finished May 05 03:05:53 PM PDT 24
Peak memory 202296 kb
Host smart-dfc81ca3-5409-451c-9620-11a78b308278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731473032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3731473032
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.172117974
Short name T605
Test name
Test status
Simulation time 493612445399 ps
CPU time 281.66 seconds
Started May 05 02:51:48 PM PDT 24
Finished May 05 02:56:30 PM PDT 24
Peak memory 202264 kb
Host smart-f9b14905-b8e0-4309-8703-e77bba7732cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=172117974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.172117974
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.4256285600
Short name T637
Test name
Test status
Simulation time 392432563504 ps
CPU time 802.46 seconds
Started May 05 02:51:46 PM PDT 24
Finished May 05 03:05:09 PM PDT 24
Peak memory 202324 kb
Host smart-4f0afceb-20bc-4bce-ba24-278de8fb51c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256285600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.4256285600
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3407008323
Short name T730
Test name
Test status
Simulation time 206112521151 ps
CPU time 462.92 seconds
Started May 05 02:51:47 PM PDT 24
Finished May 05 02:59:30 PM PDT 24
Peak memory 202300 kb
Host smart-30d9b9d4-2f5a-4b69-8483-763ad72c09d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407008323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3407008323
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.477406585
Short name T796
Test name
Test status
Simulation time 122638663441 ps
CPU time 385.05 seconds
Started May 05 02:51:51 PM PDT 24
Finished May 05 02:58:17 PM PDT 24
Peak memory 202604 kb
Host smart-8579df5d-5f03-455f-82cd-4013b14b201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477406585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.477406585
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2738770287
Short name T406
Test name
Test status
Simulation time 35039667901 ps
CPU time 76.34 seconds
Started May 05 02:51:46 PM PDT 24
Finished May 05 02:53:03 PM PDT 24
Peak memory 202112 kb
Host smart-0ac67469-52d0-4cd7-99b8-f3d13f01a3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738770287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2738770287
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2260247632
Short name T531
Test name
Test status
Simulation time 4515838527 ps
CPU time 10.71 seconds
Started May 05 02:51:46 PM PDT 24
Finished May 05 02:51:57 PM PDT 24
Peak memory 202136 kb
Host smart-c5e44b5b-968e-4b84-bec1-4c02e96f4e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260247632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2260247632
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2858664537
Short name T421
Test name
Test status
Simulation time 5947456490 ps
CPU time 2.05 seconds
Started May 05 02:51:47 PM PDT 24
Finished May 05 02:51:50 PM PDT 24
Peak memory 202048 kb
Host smart-cc6870d3-1a7e-4ae8-82b3-2ae2350cdd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858664537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2858664537
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1942764191
Short name T688
Test name
Test status
Simulation time 655302146359 ps
CPU time 1947.6 seconds
Started May 05 02:51:51 PM PDT 24
Finished May 05 03:24:19 PM PDT 24
Peak memory 210856 kb
Host smart-27f85d28-213a-4e00-b8fa-398d90c64d86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942764191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1942764191
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1042336911
Short name T23
Test name
Test status
Simulation time 43370024278 ps
CPU time 28.64 seconds
Started May 05 02:51:53 PM PDT 24
Finished May 05 02:52:22 PM PDT 24
Peak memory 211020 kb
Host smart-b2f02618-1594-4de1-a42e-95f7ad55bcac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042336911 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1042336911
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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