Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7258	1			T7	24		T13	10		T14	7
testmodes[AdcCtrlTestmodeNormal]	5825	1			T1	2		T2	1		T5	3
testmodes[AdcCtrlTestmodeLowpower]	6339	1			T3	15		T7	20		T8	13
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3801	1			T7	21		T13	4		T14	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1892	1			T7	2		T13	6		T14	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1444	1			T14	2		T36	1		T43	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1851	1			T7	2		T13	6		T14	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2094	1			T1	1		T5	2		T7	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1553	1			T7	1		T13	1		T14	7
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1492	1			T7	1		T14	1		T36	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1500	1			T7	1		T14	8		T26	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	3096	1			T3	14		T7	18		T8	12