Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23915

1

T1

20

T2

1

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3257

1

T5

1

T6

25

T13

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21652

1

T3

15

T5

3

T7

58

auto[1]

5520

1

T1

20

T2

1

T6

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38	1			T211	26		T212	12		-	-
values[1]	549	1			T146	21		T37	2		T75	2
values[2]	2730	1			T1	20		T2	1		T6	25
values[3]	654	1			T5	1		T28	3		T33	10
values[4]	725	1			T11	26		T26	22		T30	3
values[5]	719	1			T14	7		T29	27		T174	21
values[6]	696	1			T5	1		T11	15		T12	1
values[7]	714	1			T29	29		T31	8		T190	16
values[8]	809	1			T13	19		T26	25		T36	1
values[9]	1011	1			T5	1		T7	9		T26	9
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	687	1			T146	21		T37	10		T75	2
values[1]	2865	1			T1	20		T2	1		T6	25
values[2]	612	1			T5	1		T33	10		T213	1
values[3]	702	1			T11	26		T14	7		T26	22
values[4]	740	1			T11	15		T12	1		T13	16
values[5]	759	1			T5	1		T29	29		T174	49
values[6]	734	1			T147	1		T159	7		T135	3
values[7]	634	1			T13	19		T26	25		T31	16
values[8]	771	1			T5	1		T7	9		T26	9
values[9]	136	1			T33	2		T157	8		T162	19
minimum	18532	1			T3	15		T7	49		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T37	1		T75	1		T76	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T146	12		T37	6		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T1	2		T2	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	12		T75	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	1		T33	8		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T142	1		T76	1		T157	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T11	14		T14	6		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T26	13		T214	1		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	7		T12	1		T13	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T29	13		T147	1		T38	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T174	14		T66	10		T216	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T29	17		T174	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T147	1		T167	15		T15	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T159	1		T135	1		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T31	8		T36	1		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	9		T26	15		T31	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T5	1		T7	3		T29	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T26	7		T27	12		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T162	7		T39	3		T169	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T33	1		T157	8		T218	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18392	1			T3	15		T7	49		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T37	1		T75	1		T76	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T146	9		T37	2		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	914	1			T1	18		T28	2		T146	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	13		T75	12		T168	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T33	2		T156	8		T80	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T76	2		T38	3		T216	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	12		T14	1		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T26	9		T214	1		T215	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	8		T13	7		T146	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	14		T38	2		T158	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T174	7		T66	7		T216	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T29	12		T174	12		T156	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T167	13		T219	10		T170	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T159	6		T135	2		T168	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T220	9		T218	4		T221	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	10		T26	10		T76	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	6		T29	17		T30	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T26	2		T27	9		T75	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T162	12		T39	1		T204	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T33	1		T222	8		T223	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T37	4		T66	3		T136	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T212	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T211	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T37	1		T75	1		T76	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T146	12		T158	9		T224	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1507	1			T1	2		T2	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	12		T37	6		T75	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	1		T28	1		T33	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T76	1		T157	9		T38	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	14		T30	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T26	13		T142	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T14	6		T174	14		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T29	13		T38	8		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	7		T12	1		T13	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T174	16		T156	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T147	1		T216	3		T167	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T29	17		T31	8		T190	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T36	1		T217	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	9		T26	15		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T5	1		T7	3		T29	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T26	7		T27	12		T33	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T212	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T211	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T37	1		T75	1		T76	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T146	9		T158	4		T224	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	858	1			T1	18		T79	18		T225	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	13		T37	2		T75	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T28	2		T33	2		T146	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T76	2		T38	3		T226	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	12		T30	2		T135	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T26	9		T216	4		T167	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	1		T174	7		T146	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T29	14		T38	2		T219	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	8		T13	7		T66	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T174	12		T156	16		T158	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T216	3		T167	13		T138	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T29	12		T135	2		T227	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T220	9		T219	10		T218	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	10		T26	10		T165	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T7	6		T29	17		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T26	2		T27	9		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	2		T75	2		T76	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T146	10		T37	7		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T1	20		T2	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	14		T75	13		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T5	1		T33	6		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T142	1		T76	3		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T11	13		T14	5		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T26	10		T214	2		T215	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	9		T12	1		T13	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T29	15		T147	1		T38	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T174	8		T66	8		T216	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	1		T29	13		T174	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T147	1		T167	14		T15	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T159	7		T135	3		T168	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T31	2		T36	1		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	11		T26	11		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	1		T7	7		T29	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T26	3		T27	10		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T162	13		T39	3		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T33	2		T157	1		T218	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18530	1			T3	15		T7	49		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T34	4		T228	2		T229	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T146	11		T37	1		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T32	38		T230	15		T231	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	11		T163	4		T232	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T33	4		T156	3		T80	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T157	8		T38	6		T216	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	13		T14	2		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T26	12		T233	10		T234	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	6		T13	8		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T29	12		T38	4		T158	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T174	13		T66	9		T216	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T29	16		T174	15		T190	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T167	14		T170	18		T235	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T169	2		T211	10		T193	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T31	6		T236	9		T218	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	8		T26	14		T31	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	2		T29	15		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T26	6		T27	11		T237	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T162	6		T39	1		T169	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T157	7		T223	3		T202	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T95	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T212	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T211	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T37	2		T75	2		T76	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T146	10		T158	5		T224	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T1	20		T2	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	14		T37	7		T75	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T28	3		T33	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T76	3		T157	1		T38	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	13		T30	3		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T26	10		T142	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	5		T174	8		T146	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T29	15		T38	6		T219	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	9		T12	1		T13	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T174	13		T156	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T147	1		T216	4		T167	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T29	13		T31	1		T190	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T36	1		T217	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	11		T26	11		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T5	1		T7	7		T29	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T26	3		T27	10		T33	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T212	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T211	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T34	4		T238	8		T239	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T146	11		T158	8		T224	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T32	38		T230	15		T231	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	11		T37	1		T38	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T33	4		T156	3		T80	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T157	8		T38	6		T163	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	13		T136	14		T137	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T26	12		T216	13		T167	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	2		T174	13		T146	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T29	12		T38	4		T170	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	6		T13	8		T66	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T174	15		T156	16		T158	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T216	2		T167	14		T138	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T29	16		T31	7		T190	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T236	9		T218	11		T214	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	8		T26	14		T19	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	2		T29	15		T31	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T26	6		T27	11		T157	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23662

1

T1

20

T2

1

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3510

1

T5

1

T6

25

T11

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21481

1

T3

15

T7

49

T8

13

auto[1]

5691

1

T1

20

T2

1

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	35	1			T176	18		T240	1		T241	1
values[1]	460	1			T5	1		T12	1		T27	21
values[2]	696	1			T6	25		T75	9		T157	9
values[3]	586	1			T7	9		T26	47		T174	28
values[4]	2928	1			T1	20		T2	1		T9	3
values[5]	686	1			T14	7		T30	3		T191	1
values[6]	777	1			T5	1		T31	3		T36	1
values[7]	598	1			T5	1		T29	29		T30	3
values[8]	590	1			T11	26		T26	9		T213	1
values[9]	1289	1			T11	15		T13	16		T28	3
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	578	1			T5	1		T12	1		T27	21
values[1]	759	1			T6	25		T26	25		T37	8
values[2]	719	1			T7	9		T26	22		T174	28
values[3]	2831	1			T1	20		T2	1		T9	3
values[4]	710	1			T5	1		T14	7		T30	3
values[5]	774	1			T29	29		T36	1		T33	2
values[6]	546	1			T5	1		T26	9		T30	3
values[7]	717	1			T11	41		T29	27		T33	10
values[8]	809	1			T13	16		T31	13		T142	1
values[9]	184	1			T28	3		T165	2		T152	14
minimum	18545	1			T3	15		T7	49		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	1		T133	1		T76	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	1		T27	12		T75	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T26	15		T75	1		T162	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T6	12		T37	6		T158	29
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	3		T26	13		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T174	16		T133	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T1	2		T2	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	9		T29	16		T136	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	1		T14	6		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T30	1		T191	1		T156	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T152	1		T168	1		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T29	17		T36	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	1		T26	7		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T213	1		T217	1		T174	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	7		T29	13		T190	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	14		T33	8		T38	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T31	5		T150	1		T136	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	9		T31	8		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T28	1		T165	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T239	11		T242	19		T84	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T176	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T76	5		T228	5		T160	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T27	9		T75	1		T243	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T26	10		T75	6		T162	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	13		T37	2		T158	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	6		T26	9		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T174	12		T146	17		T156	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T1	18		T79	18		T225	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	10		T29	17		T136	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	1		T66	7		T224	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	2		T156	8		T38	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T152	2		T168	8		T219	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T29	12		T33	1		T76	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T26	2		T30	2		T75	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T174	7		T158	4		T159	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	8		T29	14		T146	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	12		T33	2		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T136	8		T244	9		T177	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	7		T145	13		T146	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T28	2		T165	1		T152	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T242	13		T84	2		T245	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T176	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T240	1		T241	1		T246	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T176	10		T247	1		T248	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T12	1		T133	1		T76	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	1		T27	12		T169	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T75	1		T157	9		T162	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T6	12		T75	1		T158	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	3		T26	28		T80	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T174	16		T37	6		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1622	1			T1	2		T2	1		T9	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	9		T29	16		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	6		T133	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T30	1		T191	1		T156	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	1		T31	3		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T36	1		T33	1		T76	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	1		T30	1		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T29	17		T217	1		T174	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T26	7		T190	16		T146	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	14		T213	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T11	7		T28	1		T29	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T13	9		T31	8		T33	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T246	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T176	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T76	5		T160	12		T222	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T27	9		T221	9		T249	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T75	6		T162	2		T167	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	13		T75	1		T158	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	6		T26	19		T80	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T174	12		T37	2		T250	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T1	18		T37	1		T79	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	10		T29	17		T146	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	1		T66	7		T159	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	2		T156	8		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T220	9		T168	8		T204	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T33	1		T76	2		T167	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T30	2		T38	2		T153	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	12		T174	7		T244	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T26	2		T146	12		T75	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	12		T158	4		T159	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	8		T28	2		T29	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T13	7		T33	2		T145	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1