Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21688

1

T3

15

T5

1

T7

58

auto[ADC_CTRL_FILTER_COND_OUT]

5484

1

T1

20

T2

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21701

1

T3

15

T5

3

T7

49

auto[1]

5471

1

T1

20

T2

1

T6

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	63	1			T238	18		T254	7		T298	38
values[0]	91	1			T170	29		T215	15		T223	9
values[1]	744	1			T7	9		T31	5		T174	21
values[2]	600	1			T6	25		T26	9		T133	1
values[3]	622	1			T5	1		T29	27		T30	3
values[4]	654	1			T11	41		T33	2		T213	1
values[5]	683	1			T26	25		T29	62		T33	10
values[6]	530	1			T12	1		T13	16		T30	3
values[7]	767	1			T28	3		T31	3		T213	1
values[8]	621	1			T5	1		T13	19		T26	22
values[9]	3270	1			T1	20		T2	1		T5	1
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	964	1			T7	9		T31	5		T133	1
values[1]	2822	1			T1	20		T2	1		T5	1
values[2]	640	1			T11	15		T29	27		T30	3
values[3]	660	1			T11	26		T29	33		T213	1
values[4]	617	1			T26	25		T29	29		T33	10
values[5]	580	1			T12	1		T13	16		T30	3
values[6]	746	1			T13	19		T28	3		T213	1
values[7]	593	1			T5	1		T26	22		T31	8
values[8]	791	1			T5	1		T14	7		T27	21
values[9]	231	1			T264	1		T176	3		T229	8
minimum	18528	1			T3	15		T7	49		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T7	3		T31	5		T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T146	12		T166	8		T163	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T26	7		T142	1		T75	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1566	1			T1	2		T2	1		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T33	1		T151	1		T162	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	7		T29	13		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T29	16		T213	1		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	14		T220	1		T167	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T147	1		T75	1		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T26	15		T29	17		T33	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	1		T31	3		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	9		T30	1		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T13	9		T28	1		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T190	16		T133	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	1		T26	13		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T31	8		T169	15		T211	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T36	1		T146	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	1		T14	6		T27	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T176	3		T229	1		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T264	1		T299	3		T171	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18390	1			T3	15		T7	49		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T7	6		T145	13		T159	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T146	9		T166	7		T160	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T26	2		T75	12		T166	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	914	1			T1	18		T6	13		T174	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T33	1		T162	12		T159	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	8		T29	14		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T29	17		T75	1		T38	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	12		T220	9		T167	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T75	6		T76	11		T80	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T26	10		T29	12		T33	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T76	5		T135	8		T243	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T13	7		T30	2		T146	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	10		T28	2		T174	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T76	2		T80	2		T158	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T26	9		T158	4		T136	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T211	10		T177	13		T300	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T146	17		T165	4		T34	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	1		T27	9		T66	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T229	7		T171	1		T269	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T171	10		T182	3		T242	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T254	4		T298	19		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T238	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T223	4		T245	1		T296	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T170	15		T215	1		T301	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	3		T31	5		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T174	14		T146	12		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T26	7		T133	1		T75	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	12		T152	1		T228	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T151	1		T159	1		T163	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T29	13		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	1		T213	1		T75	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	21		T38	8		T224	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T29	16		T191	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T26	15		T29	17		T33	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	1		T76	1		T157	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T13	9		T30	1		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T28	1		T31	3		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T133	1		T146	10		T156	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	1		T13	9		T26	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T190	16		T142	1		T158	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T36	1		T146	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1687	1			T1	2		T2	1		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T254	3		T298	19		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T238	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T223	5		T245	8		T296	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T170	14		T215	14		T302	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	6		T145	13		T159	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T174	7		T146	9		T166	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T26	2		T75	12		T166	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	13		T152	2		T228	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T159	6		T141	10		T273	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T29	14		T30	2		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T33	1		T75	1		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	20		T38	2		T224	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T29	17		T75	6		T76	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T26	10		T29	12		T33	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T76	5		T135	10		T243	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T13	7		T30	2		T134	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T28	2		T174	12		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T146	12		T156	8		T76	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T13	10		T26	9		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T158	14		T281	12		T229	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T146	17		T165	4		T136	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1079	1			T1	18		T14	1		T27	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T7	7		T31	1		T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T146	10		T166	8		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T26	3		T142	1		T75	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1253	1			T1	20		T2	1		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T33	2		T151	1		T162	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	9		T29	15		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T29	18		T213	1		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	13		T220	10		T167	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T147	1		T75	7		T76	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T26	11		T29	13		T33	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	1		T31	1		T76	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	8		T30	3		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	11		T28	3		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T190	1		T133	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	1		T26	10		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T31	1		T169	1		T211	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T36	1		T146	18		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T5	1		T14	5		T27	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T176	1		T229	8		T171	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T264	1		T299	1		T171	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18528	1			T3	15		T7	49		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	2		T31	4		T138	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T146	11		T166	7		T163	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T26	6		T166	6		T153	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1227	1			T6	11		T32	38		T174	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T162	6		T163	8		T139	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	6		T29	12		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T29	15		T38	6		T193	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T11	13		T167	20		T138	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T80	10		T167	11		T260	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T26	14		T29	16		T33	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T31	2		T157	7		T137	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	8		T146	9		T156	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	8		T174	15		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T190	15		T158	27		T136	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T26	12		T158	8		T136	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T31	7		T169	14		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T157	8		T165	3		T34	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	2		T27	11		T66	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T176	2		T269	9		T303	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T299	2		T171	9		T242	18

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T254	4		T298	20		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T238	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T223	6		T245	9		T296	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T170	15		T215	15		T301	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	7		T31	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T174	8		T146	10		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T26	3		T133	1		T75	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	14		T152	3		T228	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T151	1		T159	7		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	1		T29	15		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T33	2		T213	1		T75	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	22		T38	6		T224	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T29	18		T191	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T26	11		T29	13		T33	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	1		T76	6		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T13	8		T30	3		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T28	3		T31	1		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T133	1		T146	13		T156	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T5	1		T13	11		T26	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T190	1		T142	1		T158	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T36	1		T146	18		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1440	1			T1	20		T2	1		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T254	3		T298	18		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T238	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T223	3		T296	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T170	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	2		T31	4		T249	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T174	13		T146	11		T166	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T26	6		T166	6		T153	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T6	11		T228	12		T304	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T163	8		T141	12		T269	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T29	12		T37	1		T156	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T38	6		T162	6		T139	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	19		T38	4		T224	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T29	15		T80	10		T167	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T26	14		T29	16		T33	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T157	7		T137	8		T243	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T13	8		T216	2		T176	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T31	2		T174	15		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T146	9		T156	3		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T13	8		T26	12		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T190	15		T158	12		T169	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T157	8		T165	3		T136	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1326	1			T14	2		T27	11		T31	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19