Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23762

1

T1

20

T2

1

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3410

1

T5

1

T11

41

T13

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21412

1

T3

15

T5

1

T7

58

auto[1]

5760

1

T1

20

T2

1

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	682	1			T14	5		T43	2		T33	4
values[0]	33	1			T227	33		-	-		-	-
values[1]	676	1			T5	1		T13	19		T26	25
values[2]	2971	1			T1	20		T2	1		T9	3
values[3]	614	1			T5	1		T6	25		T29	27
values[4]	555	1			T11	26		T12	1		T26	9
values[5]	767	1			T11	15		T26	22		T33	10
values[6]	693	1			T5	1		T14	7		T28	3
values[7]	628	1			T29	29		T217	1		T174	28
values[8]	621	1			T7	9		T13	16		T31	8
values[9]	847	1			T75	7		T76	3		T151	1
minimum	18085	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	725	1			T13	19		T26	25		T27	21
values[1]	2842	1			T1	20		T2	1		T9	3
values[2]	600	1			T5	1		T6	25		T11	26
values[3]	645	1			T11	15		T12	1		T26	31
values[4]	698	1			T28	3		T33	10		T191	1
values[5]	643	1			T5	1		T14	7		T38	5
values[6]	613	1			T29	29		T31	8		T217	1
values[7]	746	1			T7	9		T13	16		T146	40
values[8]	733	1			T75	7		T76	3		T151	2
values[9]	160	1			T165	2		T167	24		T140	12
minimum	18767	1			T3	15		T5	1		T7	49

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T27	12		T29	16		T80	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	9		T26	15		T31	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T1	2		T2	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T36	1		T145	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	1		T6	12		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	14		T29	13		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	1		T26	7		T31	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	7		T26	13		T156	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T33	8		T37	6		T66	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T28	1		T191	1		T146	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	6		T162	7		T138	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T5	1		T38	3		T163	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T29	17		T174	16		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T31	8		T217	1		T133	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	3		T13	9		T146	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T146	1		T158	13		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T75	1		T76	1		T232	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T151	2		T259	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T140	12		T192	1		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T165	1		T167	12		T242	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18470	1			T3	15		T5	1		T7	49
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T159	1		T236	10		T299	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T27	9		T29	17		T80	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	10		T26	10		T135	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	932	1			T1	18		T30	2		T79	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T145	13		T134	17		T136	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	13		T162	2		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	12		T29	14		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T26	2		T75	1		T152	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	8		T26	9		T156	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T33	2		T37	2		T66	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T28	2		T146	9		T250	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T14	1		T162	12		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T38	2		T204	8		T221	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T29	12		T174	12		T156	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T80	2		T136	8		T34	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	6		T13	7		T146	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T146	17		T158	14		T216	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T75	6		T76	2		T249	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T159	8		T135	8		T138	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T295	12		T262	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T165	1		T167	12		T242	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T33	1		T174	7		T37	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T159	13		T215	5		T242	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	532	1			T14	5		T43	2		T33	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T151	1		T165	1		T138	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T227	17		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	1		T27	12		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	9		T26	15		T31	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1575	1			T1	2		T2	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T36	1		T145	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	1		T6	12		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T29	13		T30	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T26	7		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	14		T156	17		T218	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T33	8		T37	6		T66	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	7		T26	13		T191	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	6		T224	11		T162	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	1		T28	1		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T29	17		T174	16		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T217	1		T133	2		T147	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	3		T13	9		T146	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T31	8		T146	1		T80	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T75	1		T76	1		T232	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T151	1		T259	1		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17947	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T249	4		T215	14		T197	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T165	1		T138	7		T202	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T227	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T27	9		T33	1		T174	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	10		T26	10		T159	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T1	18		T29	17		T30	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T145	13		T134	17		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	13		T220	9		T40	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T29	14		T30	2		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T26	2		T75	1		T162	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T11	12		T156	16		T218	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T33	2		T37	2		T66	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	8		T26	9		T146	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T14	1		T224	15		T162	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T28	2		T38	2		T260	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T29	12		T174	12		T156	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T136	8		T228	16		T204	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	6		T13	7		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T146	17		T80	2		T158	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T75	6		T76	2		T18	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T159	8		T135	8		T216	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T27	10		T29	18		T80	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T13	11		T26	11		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T1	20		T2	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T36	1		T145	14		T134	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	1		T6	14		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	13		T29	15		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	1		T26	3		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	9		T26	10		T156	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T33	6		T37	7		T66	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T28	3		T191	1		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	5		T162	13		T138	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	1		T38	3		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T29	13		T174	13		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T31	1		T217	1		T133	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	7		T13	8		T146	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T146	18		T158	15		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T75	7		T76	3		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T151	2		T259	1		T159	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T140	1		T192	1		T295	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T165	2		T167	13		T242	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18586	1			T3	15		T5	1		T7	49
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T159	14		T236	1		T299	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T27	11		T29	15		T80	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	8		T26	14		T31	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T32	38		T190	15		T230	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T136	14		T216	2		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	11		T157	8		T162	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T11	13		T29	12		T226	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T26	6		T31	2		T176	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	6		T26	12		T156	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T33	4		T37	1		T66	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T146	11		T169	16		T260	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T14	2		T162	6		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T38	2		T163	14		T204	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T29	16		T174	15		T156	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T31	7		T136	13		T34	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	2		T13	8		T146	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T158	12		T216	13		T163	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T232	11		T35	2		T249	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T138	9		T243	15		T260	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T140	11		T262	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T167	11		T242	9		T296	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T174	13		T157	7		T227	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T236	9		T299	6		T234	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	526	1			T14	5		T43	2		T33	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T151	1		T165	2		T138	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T227	17		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	1		T27	10		T33	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	11		T26	11		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T1	20		T2	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T36	1		T145	14		T134	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	1		T6	14		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T29	15		T30	3		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T26	3		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	13		T156	17		T218	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T33	6		T37	7		T66	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	9		T26	10		T191	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	5		T224	16		T162	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	1		T28	3		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T29	13		T174	13		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T217	1		T133	2		T147	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	7		T13	8		T146	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T31	1		T146	18		T80	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T75	7		T76	3		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T151	1		T259	1		T159	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18085	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T140	11		T249	5		T305	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T138	9		T235	12		T306	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T227	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T27	11		T174	13		T80	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	8		T26	14		T31	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T29	15		T32	38		T190	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T136	14		T216	2		T167	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	11		T157	8		T163	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T29	12		T226	12		T178	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T26	6		T31	2		T162	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	13		T156	16		T218	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T33	4		T37	1		T66	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	6		T26	12		T146	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	2		T224	10		T162	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T38	2		T163	14		T169	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T29	16		T174	15		T156	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T136	13		T228	12		T204	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	2		T13	8		T146	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T31	7		T158	12		T34	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T232	11		T35	2		T235	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T216	13		T167	11		T163	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19