Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23595

1

T1

20

T2

1

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3577

1

T5

2

T6

25

T7

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21499

1

T3

15

T5

1

T6

25

auto[1]

5673

1

T1

20

T2

1

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	297	1			T213	1		T75	2		T224	26
values[0]	75	1			T41	7		T299	3		T20	9
values[1]	804	1			T30	3		T31	8		T145	14
values[2]	453	1			T7	9		T31	5		T33	10
values[3]	705	1			T12	1		T27	21		T213	1
values[4]	726	1			T29	29		T133	1		T146	21
values[5]	2842	1			T1	20		T2	1		T9	3
values[6]	637	1			T5	1		T13	19		T26	22
values[7]	671	1			T26	34		T29	33		T36	1
values[8]	618	1			T5	2		T11	26		T13	16
values[9]	817	1			T6	25		T11	15		T14	7
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	746	1			T30	3		T31	8		T145	14
values[1]	551	1			T7	9		T31	5		T33	10
values[2]	756	1			T12	1		T27	21		T29	29
values[3]	2873	1			T1	20		T2	1		T9	3
values[4]	656	1			T13	19		T174	28		T146	18
values[5]	723	1			T5	1		T26	47		T28	3
values[6]	549	1			T5	1		T11	26		T13	16
values[7]	594	1			T5	1		T29	27		T30	3
values[8]	912	1			T6	25		T11	15		T14	7
values[9]	62	1			T133	1		T287	10		T301	1
minimum	18750	1			T3	15		T7	49		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T30	1		T75	1		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T31	8		T145	1		T156	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T31	5		T146	10		T76	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	3		T33	8		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	1		T27	12		T29	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T213	1		T157	8		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1556	1			T1	2		T2	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T147	1		T76	1		T158	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T146	1		T37	1		T80	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	9		T174	16		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T26	28		T28	1		T31	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	1		T29	16		T191	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T5	1		T11	14		T26	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	9		T169	15		T226	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T133	1		T162	11		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	1		T29	13		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	7		T14	6		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T6	12		T217	1		T37	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T287	10		T253	7		T187	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T133	1		T301	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18439	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T135	1		T41	5		T193	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T30	2		T75	6		T159	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T145	13		T156	16		T38	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T146	12		T76	2		T80	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	6		T33	2		T174	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T27	9		T29	12		T136	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T152	2		T160	12		T243	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T1	18		T146	9		T156	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T76	11		T158	14		T134	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T146	17		T37	1		T80	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	10		T174	12		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T26	19		T28	2		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T29	17		T76	5		T66	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T11	12		T26	2		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	7		T226	13		T138	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T162	2		T160	6		T260	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T29	14		T30	2		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	8		T14	1		T75	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	13		T37	2		T75	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T253	16		T187	6		T307	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	4		T66	3		T152	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T41	2		T20	3		T308	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T213	1		T75	1		T229	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T224	11		T152	1		T138	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T299	3		T309	12		T310	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T41	5		T20	6		T311	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T30	1		T75	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T31	8		T145	1		T156	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T31	5		T146	10		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	3		T33	8		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	1		T27	12		T76	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T213	1		T157	8		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T29	17		T133	1		T146	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T147	1		T76	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T1	2		T2	1		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T174	16		T147	1		T38	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T26	13		T28	1		T31	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	1		T13	9		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T26	22		T36	1		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T29	16		T76	1		T226	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	1		T11	14		T162	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	1		T13	9		T29	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	7		T14	6		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T6	12		T217	1		T190	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T75	1		T229	14		T253	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T224	15		T152	13		T138	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T309	10		T310	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T41	2		T20	3		T311	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T30	2		T75	6		T159	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T145	13		T156	16		T158	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T146	12		T80	2		T165	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	6		T33	2		T174	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T27	9		T76	2		T136	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T159	13		T152	2		T243	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T29	12		T146	9		T156	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T76	11		T134	17		T160	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T1	18		T146	17		T79	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T174	12		T38	2		T158	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T26	9		T28	2		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	10		T66	7		T162	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T26	12		T33	1		T135	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T29	17		T76	5		T226	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	12		T162	2		T160	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	7		T29	14		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	8		T14	1		T40	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	13		T37	2		T75	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T30	3		T75	7		T159	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T31	1		T145	14		T156	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T31	1		T146	13		T76	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	7		T33	6		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	1		T27	10		T29	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T213	1		T157	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T1	20		T2	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T147	1		T76	12		T158	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T146	18		T37	2		T80	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	11		T174	13		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T26	21		T28	3		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T29	18		T191	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	1		T11	13		T26	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	8		T169	1		T226	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T133	1		T162	3		T160	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	1		T29	15		T30	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	9		T14	5		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T6	14		T217	1		T37	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T287	1		T253	17		T187	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T133	1		T301	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18581	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T135	1		T41	5		T193	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T153	5		T274	9		T277	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	7		T156	16		T38	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T31	4		T146	9		T165	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	2		T33	4		T174	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T27	11		T29	16		T136	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T157	7		T243	15		T170	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T32	38		T146	11		T156	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T158	12		T167	11		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T80	10		T166	6		T216	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	8		T174	15		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T26	26		T31	2		T158	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T29	15		T66	9		T157	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T11	13		T26	6		T166	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	8		T169	14		T226	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T162	10		T260	5		T234	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T29	12		T190	15		T38	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	6		T14	2		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	11		T37	1		T224	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T287	9		T253	6		T187	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T216	2		T238	8		T299	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T41	2		T193	13		T20	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T213	1		T75	2		T229	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T224	16		T152	14		T138	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T299	1		T309	11		T310	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T41	5		T20	7		T311	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T30	3		T75	7		T159	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T31	1		T145	14		T156	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T31	1		T146	13		T80	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	7		T33	6		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T27	10		T76	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T213	1		T157	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T29	13		T133	1		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T147	1		T76	12		T134	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T1	20		T2	1		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T174	13		T147	1		T38	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T26	10		T28	3		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	1		T13	11		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T26	14		T36	1		T33	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T29	18		T76	6		T226	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	1		T11	13		T162	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	1		T13	8		T29	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	9		T14	5		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T6	14		T217	1		T190	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T229	2		T287	9		T312	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T224	10		T138	9		T177	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T299	2		T309	11		T310	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T41	2		T20	2		T233	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T216	2		T153	5		T238	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T31	7		T156	16		T158	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T31	4		T146	9		T165	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	2		T33	4		T174	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T27	11		T136	27		T34	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T157	7		T35	2		T236	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T29	16		T146	11		T156	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T19	1		T239	13		T313	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T32	38		T80	10		T230	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T174	15		T38	2		T158	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T26	12		T31	2		T158	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T13	8		T66	9		T157	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T26	20		T166	7		T214	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	15		T226	12		T218	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	13		T162	10		T260	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	8		T29	12		T38	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	6		T14	2		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	11		T190	15		T37	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19