Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21655

1

T3

15

T5

1

T7

58

auto[ADC_CTRL_FILTER_COND_OUT]

5517

1

T1

20

T2

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21757

1

T3

15

T5

3

T7

49

auto[1]

5415

1

T1

20

T2

1

T6

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	300	1			T14	7		T27	21		T147	1
values[0]	32	1			T264	1		T170	29		T301	1
values[1]	828	1			T7	9		T31	5		T174	21
values[2]	612	1			T6	25		T26	9		T133	1
values[3]	570	1			T5	1		T11	15		T30	3
values[4]	664	1			T29	27		T33	2		T213	1
values[5]	665	1			T11	26		T26	25		T29	62
values[6]	563	1			T12	1		T13	16		T30	3
values[7]	787	1			T28	3		T31	3		T213	1
values[8]	541	1			T5	1		T13	19		T26	22
values[9]	3083	1			T1	20		T2	1		T5	1
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	663	1			T174	21		T133	1		T142	1
values[1]	2820	1			T1	20		T2	1		T6	25
values[2]	625	1			T5	1		T11	15		T29	27
values[3]	705	1			T11	26		T29	33		T213	1
values[4]	587	1			T26	25		T29	29		T33	10
values[5]	546	1			T12	1		T13	16		T30	3
values[6]	784	1			T28	3		T31	3		T213	1
values[7]	578	1			T5	2		T13	19		T26	22
values[8]	933	1			T14	7		T27	21		T36	1
values[9]	116	1			T147	1		T176	3		T141	16
minimum	18815	1			T3	15		T7	58		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T133	1		T142	1		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T174	14		T146	12		T166	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T26	7		T145	1		T75	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1548	1			T1	2		T2	1		T6	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T33	1		T151	1		T162	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	1		T11	7		T29	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T29	16		T213	1		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	14		T38	8		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T75	1		T76	1		T80	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T26	15		T29	17		T33	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	1		T76	1		T157	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	9		T30	1		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T28	1		T31	3		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T190	16		T133	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T13	9		T26	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	1		T31	8		T169	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T36	1		T146	1		T157	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T14	6		T27	12		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T147	1		T176	3		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T141	4		T265	1		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18463	1			T3	15		T7	52		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T163	15		T160	1		T264	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T218	4		T249	7		T251	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T174	7		T146	9		T166	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T26	2		T145	13		T75	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	918	1			T1	18		T6	13		T79	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T33	1		T162	12		T159	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	8		T29	14		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T29	17		T75	1		T38	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	12		T38	2		T220	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T75	6		T76	11		T80	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T26	10		T29	12		T33	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T76	5		T243	14		T170	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	7		T30	2		T146	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T28	2		T174	12		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T76	2		T80	2		T158	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T13	10		T26	9		T158	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T177	13		T300	8		T290	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T146	17		T165	4		T34	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T14	1		T27	9		T66	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T171	1		T269	9		T182	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T141	12		T246	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	6		T37	4		T66	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T160	12		T314	10		T170	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T147	1		T226	13		T176	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T14	6		T27	12		T162	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T263	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T264	1		T170	15		T301	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	3		T31	5		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T174	14		T146	12		T166	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T26	7		T133	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T6	12		T147	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T151	1		T159	1		T163	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	1		T11	7		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T33	1		T213	1		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T29	13		T38	8		T224	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T29	16		T147	1		T75	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	14		T26	15		T29	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	1		T76	1		T157	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	9		T30	1		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T28	1		T31	3		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T133	1		T142	1		T146	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	1		T13	9		T26	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T190	16		T158	13		T169	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T36	1		T146	1		T157	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1625	1			T1	2		T2	1		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T226	13		T315	9		T254	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T14	1		T27	9		T162	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T170	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	6		T159	8		T218	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T174	7		T146	9		T166	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T26	2		T145	13		T75	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T6	13		T152	2		T228	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T159	6		T141	10		T269	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	8		T30	2		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T33	1		T75	1		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T29	14		T38	2		T224	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T29	17		T75	6		T76	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	12		T26	10		T29	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T76	5		T243	14		T17	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T13	7		T30	2		T134	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T28	2		T174	12		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T146	12		T156	8		T76	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T13	10		T26	9		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T158	14		T177	13		T316	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T146	17		T165	4		T136	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1030	1			T1	18		T66	7		T79	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T133	1		T142	1		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T174	8		T146	10		T166	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T26	3		T145	14		T75	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1255	1			T1	20		T2	1		T6	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T33	2		T151	1		T162	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	1		T11	9		T29	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T29	18		T213	1		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	13		T38	6		T220	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T75	7		T76	12		T80	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T26	11		T29	13		T33	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	1		T76	6		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	8		T30	3		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T28	3		T31	1		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T190	1		T133	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	1		T13	11		T26	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	1		T31	1		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T36	1		T146	18		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T14	5		T27	10		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T147	1		T176	1		T171	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T141	13		T265	1		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18627	1			T3	15		T7	56		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T163	1		T160	13		T264	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T218	11		T249	1		T251	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T174	13		T146	11		T166	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T26	6		T166	6		T153	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1211	1			T6	11		T32	38		T230	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T162	6		T139	5		T234	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	6		T29	12		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T29	15		T38	6		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	13		T38	4		T167	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T80	10		T260	5		T17	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T26	14		T29	16		T33	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T157	7		T137	8		T243	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	8		T146	9		T156	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T31	2		T174	15		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T190	15		T158	27		T136	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T13	8		T26	12		T158	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T31	7		T169	14		T270	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T157	8		T165	3		T34	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	2		T27	11		T66	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T176	2		T269	9		T303	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T141	3		T317	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T7	2		T31	4		T235	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T163	14		T170	14		T233	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T147	1		T226	14		T176	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T14	5		T27	10		T162	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T263	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T264	1		T170	15		T301	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	7		T31	1		T159	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T174	8		T146	10		T166	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T26	3		T133	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	14		T147	1		T152	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T151	1		T159	7		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	1		T11	9		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T33	2		T213	1		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T29	15		T38	6		T224	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T29	18		T147	1		T75	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	13		T26	11		T29	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T76	6		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	8		T30	3		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T28	3		T31	1		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T133	1		T142	1		T146	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	1		T13	11		T26	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T190	1		T158	15		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T36	1		T146	18		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1378	1			T1	20		T2	1		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T226	12		T176	2		T233	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T14	2		T27	11		T162	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T170	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	2		T31	4		T218	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T174	13		T146	11		T166	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T26	6		T166	6		T153	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T6	11		T228	12		T304	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T163	8		T141	12		T238	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	6		T37	1		T156	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T38	6		T162	6		T139	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T29	12		T38	4		T224	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T29	15		T80	10		T167	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	13		T26	14		T29	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T157	7		T137	8		T243	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T13	8		T216	2		T176	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T31	2		T174	15		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T146	9		T156	3		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	8		T26	12		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T190	15		T158	12		T169	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T157	8		T165	3		T136	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1277	1			T31	7		T32	38		T66	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19