Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23790

1

T1

20

T2

1

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3382

1

T5

1

T6

25

T7

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21344

1

T3

15

T5

3

T7

58

auto[1]

5828

1

T1

20

T2

1

T6

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	267	1			T36	1		T33	2		T147	1
values[0]	43	1			T157	9		T268	3		T278	11
values[1]	656	1			T5	1		T29	29		T33	10
values[2]	729	1			T13	19		T26	31		T29	33
values[3]	651	1			T76	3		T80	15		T38	12
values[4]	580	1			T6	25		T12	1		T30	6
values[5]	720	1			T5	1		T27	21		T213	1
values[6]	605	1			T5	1		T29	27		T31	8
values[7]	567	1			T7	9		T11	26		T146	18
values[8]	2764	1			T1	20		T2	1		T9	3
values[9]	1063	1			T11	15		T13	16		T14	7
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	672	1			T5	1		T13	19		T33	10
values[1]	685	1			T26	31		T29	33		T31	3
values[2]	615	1			T12	1		T147	1		T38	12
values[3]	685	1			T6	25		T27	21		T30	6
values[4]	683	1			T5	1		T31	8		T213	1
values[5]	629	1			T5	1		T29	27		T174	21
values[6]	2737	1			T1	20		T2	1		T7	9
values[7]	510	1			T11	15		T26	25		T28	3
values[8]	973	1			T13	16		T14	7		T147	1
values[9]	240	1			T36	1		T33	2		T136	22
minimum	18743	1			T3	15		T7	49		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	1		T142	1		T156	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	9		T33	8		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T26	7		T146	10		T80	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T26	13		T29	16		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T38	9		T167	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T147	1		T176	3		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T146	12		T228	3		T260	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	12		T27	12		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T31	8		T156	4		T237	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	1		T213	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	1		T66	10		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T29	13		T174	14		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1472	1			T1	2		T2	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	3		T147	1		T158	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T31	5		T133	1		T37	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	7		T26	15		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T13	9		T14	6		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T159	1		T175	1		T163	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T136	14		T227	17		T252	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T36	1		T33	1		T187	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18479	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T76	1		T151	1		T238	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T156	16		T158	4		T167	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	10		T33	2		T174	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T26	2		T146	12		T80	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T26	9		T29	17		T76	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T38	3		T167	13		T141	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T219	10		T244	9		T183	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T146	9		T228	5		T260	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	13		T27	9		T30	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T156	8		T274	4		T215	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T75	12		T162	2		T166	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T66	7		T134	17		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T29	14		T174	7		T146	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T1	18		T11	12		T75	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	6		T158	14		T165	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T37	2		T75	6		T135	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T11	8		T26	10		T28	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	7		T14	1		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T159	6		T228	16		T15	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T136	8		T227	16		T275	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T33	1		T187	12		T276	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T29	12		T37	4		T66	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T76	11		T238	9		T304	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T147	1		T158	9		T136	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T36	1		T33	1		T15	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T157	9		T268	1		T279	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T278	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	1		T29	17		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T33	8		T217	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T26	7		T146	10		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	9		T26	13		T29	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T80	11		T38	9		T167	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T76	1		T176	3		T140	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	1		T146	12		T228	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	12		T30	2		T190	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T156	4		T237	14		T274	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	1		T27	12		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	1		T31	8		T226	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T29	13		T174	14		T75	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	14		T75	1		T66	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	3		T146	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1502	1			T1	2		T2	1		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T133	1		T157	8		T158	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T13	9		T14	6		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T11	7		T26	15		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T158	4		T136	8		T227	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T33	1		T15	5		T219	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T268	2		T279	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T278	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T29	12		T156	16		T158	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T33	2		T145	13		T76	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T26	2		T146	12		T167	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	10		T26	9		T29	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T80	4		T38	3		T167	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T76	2		T244	9		T183	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T146	9		T228	5		T260	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	13		T30	4		T162	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T156	8		T274	4		T215	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T27	9		T162	2		T166	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T226	2		T281	12		T244	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T29	14		T174	7		T75	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	12		T75	1		T66	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	6		T146	17		T159	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T1	18		T37	2		T75	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T158	14		T165	4		T152	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	7		T14	1		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T11	8		T26	10		T28	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	1		T142	1		T156	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	11		T33	6		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T26	3		T146	13		T80	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T26	10		T29	18		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	1		T38	6		T167	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T147	1		T176	1		T219	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T146	10		T228	6		T260	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	14		T27	10		T30	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T31	1		T156	9		T237	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	1		T213	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	1		T66	8		T134	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T29	15		T174	8		T146	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T1	20		T2	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	7		T147	1		T158	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T31	1		T133	1		T37	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	9		T26	11		T28	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T13	8		T14	5		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T159	7		T175	1		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T136	9		T227	17		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T36	1		T33	2		T187	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18600	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T76	12		T151	1		T238	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T156	16		T158	15		T167	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	8		T33	4		T174	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T26	6		T146	9		T80	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T26	12		T29	15		T31	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T38	6		T167	14		T169	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T176	2		T140	15		T244	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T146	11		T228	2		T260	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	11		T27	11		T190	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T31	7		T156	3		T237	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T162	10		T166	6		T216	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T66	9		T153	5		T226	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T29	12		T174	13		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1140	1			T11	13		T32	38		T230	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	2		T158	12		T165	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T31	4		T37	1		T243	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T11	6		T26	14		T157	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T13	8		T14	2		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T163	8		T228	12		T15	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T136	13		T227	16		T252	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T187	11		T282	8		T276	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T29	16		T157	8		T163	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T238	8		T272	13		T304	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T147	1		T158	5		T136	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T36	1		T33	2		T15	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T157	1		T268	3		T279	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T278	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	1		T29	13		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T33	6		T217	1		T145	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T26	3		T146	13		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	11		T26	10		T29	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T80	5		T38	6		T167	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T76	3		T176	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	1		T146	10		T228	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	14		T30	6		T190	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T156	9		T237	1		T274	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	1		T27	10		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	1		T31	1		T226	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T29	15		T174	8		T75	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	13		T75	2		T66	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	7		T146	18		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T1	20		T2	1		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T133	1		T157	1		T158	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T13	8		T14	5		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T11	9		T26	11		T28	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T158	8		T136	13		T227	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T15	7		T41	2		T251	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T157	8		T279	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T29	16		T156	16		T158	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T33	4		T232	11		T238	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T26	6		T146	9		T167	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	8		T26	12		T29	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T80	10		T38	6		T167	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T176	2		T140	15		T244	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T146	11		T228	2		T236	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T6	11		T190	15		T162	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T156	3		T237	13		T274	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T27	11		T162	10		T166	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T31	7		T226	8		T193	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T29	12		T174	13		T169	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T11	13		T66	9		T38	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T7	2		T216	13		T163	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1167	1			T31	4		T32	38		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T157	7		T158	12		T165	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	8		T14	2		T166	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	6		T26	14		T163	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19