Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23668

1

T1

20

T2

1

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3504

1

T5

1

T6

25

T11

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21481

1

T3

15

T7

49

T8

13

auto[1]

5691

1

T1

20

T2

1

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	262	1			T145	14		T152	14		T136	22
values[0]	20	1			T176	18		T246	2		-	-
values[1]	467	1			T5	1		T12	1		T27	21
values[2]	701	1			T6	25		T75	9		T157	9
values[3]	597	1			T7	9		T26	47		T37	8
values[4]	2943	1			T1	20		T2	1		T9	3
values[5]	639	1			T14	7		T30	3		T191	1
values[6]	821	1			T5	1		T31	3		T36	1
values[7]	548	1			T5	1		T29	29		T30	3
values[8]	617	1			T11	26		T26	9		T190	16
values[9]	1030	1			T11	15		T13	16		T28	3
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	371	1			T5	1		T12	1		T27	21
values[1]	815	1			T6	25		T26	25		T37	8
values[2]	710	1			T7	9		T26	22		T174	28
values[3]	2776	1			T1	20		T2	1		T9	3
values[4]	801	1			T5	1		T14	7		T30	3
values[5]	762	1			T29	29		T36	1		T33	2
values[6]	517	1			T5	1		T30	3		T213	1
values[7]	719	1			T11	26		T26	9		T29	27
values[8]	893	1			T11	15		T13	16		T31	13
values[9]	103	1			T28	3		T145	14		T165	2
minimum	18705	1			T3	15		T7	49		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T12	1		T133	1		T157	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T5	1		T27	12		T75	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T26	15		T75	1		T80	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T6	12		T37	6		T158	29
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	3		T26	13		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T174	16		T133	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T1	2		T2	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	9		T29	16		T136	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	1		T14	6		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T30	1		T191	1		T156	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T213	1		T152	1		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T29	17		T36	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T30	1		T75	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T213	1		T217	1		T174	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T26	7		T29	13		T190	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	14		T33	8		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T11	7		T31	5		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	9		T31	8		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T28	1		T165	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T145	1		T239	11		T84	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18405	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T169	3		T176	10		T221	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T228	5		T160	12		T222	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T27	9		T75	1		T238	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T26	10		T75	6		T80	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	13		T37	2		T158	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T7	6		T26	9		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T174	12		T146	17		T156	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T1	18		T79	18		T225	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	10		T29	17		T136	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	1		T66	7		T224	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T30	2		T156	8		T38	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T152	2		T168	8		T219	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T29	12		T33	1		T76	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T30	2		T75	12		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T174	7		T158	4		T159	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T26	2		T29	14		T146	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	12		T33	2		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	8		T136	8		T244	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	7		T146	9		T80	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T28	2		T165	1		T152	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T145	13		T84	2		T254	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T37	4		T76	5		T66	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T176	8		T221	9		T171	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T152	1		T136	14		T16	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T145	1		T18	4		T20	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T246	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T176	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T12	1		T133	1		T76	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	1		T27	12		T169	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T75	1		T157	9		T162	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T6	12		T75	1		T158	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	3		T26	28		T80	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T37	6		T76	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1621	1			T1	2		T2	1		T9	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	9		T29	16		T174	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	6		T133	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	1		T191	1		T156	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	1		T31	3		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T36	1		T33	1		T76	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	1		T30	1		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T29	17		T213	1		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T26	7		T190	16		T146	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	14		T147	1		T38	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T11	7		T28	1		T29	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T13	9		T31	8		T33	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T152	13		T136	8		T184	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T145	13		T18	2		T20	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T246	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T176	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T76	5		T228	5		T160	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T27	9		T221	9		T238	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T75	6		T162	2		T167	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	13		T75	1		T158	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	6		T26	19		T80	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T37	2		T76	11		T250	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T1	18		T37	1		T79	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	10		T29	17		T174	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	1		T66	7		T224	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T30	2		T156	8		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T152	2		T220	9		T168	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T33	1		T76	2		T167	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T30	2		T38	2		T153	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T29	12		T174	7		T244	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T26	2		T146	12		T75	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	12		T38	2		T158	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	8		T28	2		T29	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	7		T33	2		T146	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	1		T133	1		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T5	1		T27	10		T75	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T26	11		T75	7		T80	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T6	14		T37	7		T158	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	7		T26	10		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T174	13		T133	1		T146	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T1	20		T2	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	11		T29	18		T136	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	1		T14	5		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T30	3		T191	1		T156	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T213	1		T152	3		T168	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T29	13		T36	1		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T30	3		T75	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T213	1		T217	1		T174	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T26	3		T29	15		T190	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	13		T33	6		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	9		T31	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T13	8		T31	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T28	3		T165	2		T152	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T145	14		T239	1		T84	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18566	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T169	1		T176	9		T221	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T157	8		T228	2		T251	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T27	11		T238	8		T193	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T26	14		T80	10		T162	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	11		T37	1		T158	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	2		T26	12		T34	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T174	15		T156	16		T176	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T32	38		T230	15		T231	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	8		T29	15		T136	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	2		T31	2		T66	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T156	3		T38	6		T163	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T229	2		T238	2		T193	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T29	16		T167	25		T163	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T38	2		T153	5		T169	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T174	13		T158	8		T232	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T26	6		T29	12		T190	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	13		T33	4		T38	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	6		T31	4		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	8		T31	7		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T252	13		T318	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T239	10		T254	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T84	1		T304	2		T200	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T169	2		T176	9		T221	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T152	14		T136	9		T16	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T145	14		T18	4		T20	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T246	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T176	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T133	1		T76	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	1		T27	10		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T75	7		T157	1		T162	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T6	14		T75	2		T158	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	7		T26	21		T80	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T37	7		T76	12		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T1	20		T2	1		T9	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	11		T29	18		T174	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T14	5		T133	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T30	3		T191	1		T156	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	1		T31	1		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T36	1		T33	2		T76	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	1		T30	3		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T29	13		T213	1		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T26	3		T190	1		T146	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	13		T147	1		T38	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	9		T28	3		T29	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T13	8		T31	1		T33	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T136	13		T252	13		T184	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T18	2		T20	2		T239	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T176	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T228	2		T251	16		T269	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T27	11		T169	2		T221	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T157	8		T162	10		T167	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	11		T158	27		T237	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	2		T26	26		T80	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T37	1		T40	1		T178	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T32	38		T230	15		T231	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	8		T29	15		T174	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	2		T66	9		T224	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T156	3		T38	6		T163	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T31	2		T163	4		T204	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T167	25		T163	14		T236	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T38	2		T153	5		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T29	16		T174	13		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T26	6		T190	15		T146	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	13		T38	4		T158	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	6		T29	12		T31	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	8		T31	7		T33	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19