Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T133	1		T76	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	1		T27	10		T75	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T26	11		T75	7		T162	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T6	14		T37	7		T158	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	7		T26	10		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T174	13		T133	1		T146	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T1	20		T2	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	11		T29	18		T136	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	1		T14	5		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T30	3		T191	1		T156	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T152	3		T168	9		T219	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T29	13		T36	1		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	1		T26	3		T30	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T213	1		T217	1		T174	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	9		T29	15		T190	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	13		T33	6		T38	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T31	1		T150	1		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T13	8		T31	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T28	3		T165	2		T152	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T239	1		T242	14		T84	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T176	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T157	8		T228	2		T251	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T27	11		T169	2		T243	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T26	14		T162	10		T167	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	11		T37	1		T158	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	2		T26	12		T80	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T174	15		T156	16		T176	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T32	38		T230	15		T231	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	8		T29	15		T136	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	2		T31	2		T66	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T156	3		T38	6		T163	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T229	2		T140	11		T193	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T29	16		T167	25		T163	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T26	6		T38	2		T153	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T174	13		T158	8		T232	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	6		T29	12		T190	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	13		T33	4		T38	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T31	4		T136	13		T35	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	8		T31	7		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T17	6		T252	13		T253	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T239	10		T242	18		T254	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T176	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T240	1		T241	1		T246	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T176	9		T247	1		T248	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	1		T133	1		T76	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	1		T27	10		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T75	7		T157	1		T162	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	14		T75	2		T158	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	7		T26	21		T80	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T174	13		T37	7		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T1	20		T2	1		T9	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	11		T29	18		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	5		T133	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T30	3		T191	1		T156	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	1		T31	1		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T36	1		T33	2		T76	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	1		T30	3		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T29	13		T217	1		T174	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T26	3		T190	1		T146	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	13		T213	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T11	9		T28	3		T29	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T13	8		T31	1		T33	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T176	9		T248	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T235	15		T251	16		T255	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T27	11		T169	2		T221	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T157	8		T162	10		T167	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	11		T158	27		T237	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	2		T26	26		T80	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T174	15		T37	1		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T32	38		T230	15		T231	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	8		T29	15		T156	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	2		T66	9		T226	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T156	3		T38	6		T216	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T31	2		T163	4		T204	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T167	25		T163	14		T15	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T38	2		T153	5		T169	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T29	16		T174	13		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T26	6		T190	15		T146	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T11	13		T158	8		T216	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T11	6		T29	12		T31	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T13	8		T31	7		T33	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19