Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23843

1

T1

20

T2

1

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3329

1

T5

1

T6

25

T11

41

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21707

1

T3

15

T7

49

T8

13

auto[1]

5465

1

T1

20

T2

1

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T182	10		T256	13		-	-
values[0]	23	1			T257	11		T258	1		T94	11
values[1]	605	1			T5	1		T13	19		T30	3
values[2]	704	1			T11	15		T31	5		T146	22
values[3]	710	1			T26	9		T28	3		T30	3
values[4]	675	1			T5	1		T36	1		T133	1
values[5]	2568	1			T1	20		T2	1		T7	9
values[6]	946	1			T26	25		T33	12		T213	1
values[7]	652	1			T6	25		T11	26		T12	1
values[8]	597	1			T5	1		T14	7		T29	33
values[9]	1142	1			T26	22		T27	21		T29	56
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	796	1			T5	1		T13	19		T30	3
values[1]	767	1			T11	15		T145	14		T146	22
values[2]	638	1			T5	1		T26	9		T28	3
values[3]	2743	1			T1	20		T2	1		T9	3
values[4]	717	1			T7	9		T33	10		T147	1
values[5]	707	1			T12	1		T26	25		T33	2
values[6]	700	1			T6	25		T11	26		T13	16
values[7]	630	1			T5	1		T29	33		T213	1
values[8]	782	1			T26	22		T27	21		T29	27
values[9]	165	1			T29	29		T76	12		T35	3
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T30	1		T31	5		T174	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	1		T13	9		T31	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T146	10		T165	4		T216	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	7		T145	1		T259	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	1		T26	7		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T30	1		T190	16		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1510	1			T1	2		T2	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T36	1		T66	10		T166	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T7	3		T33	8		T158	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T147	1		T76	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	1		T33	1		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T26	15		T166	1		T204	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	6		T135	1		T153	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T6	12		T11	14		T13	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	1		T213	1		T157	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T29	16		T217	1		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T26	13		T29	13		T75	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T27	12		T142	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T29	17		T35	3		T82	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T76	1		T211	13		T214	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T30	2		T174	7		T75	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	10		T174	12		T146	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T146	12		T165	4		T216	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T11	8		T145	13		T162	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T26	2		T28	2		T146	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T30	2		T75	12		T80	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	906	1			T1	18		T79	18		T38	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T66	7		T166	14		T216	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	6		T33	2		T158	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T76	2		T38	2		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T33	1		T37	1		T165	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T26	10		T166	1		T204	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T14	1		T135	2		T153	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	13		T11	12		T13	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T38	2		T228	5		T249	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T29	17		T156	24		T159	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T26	9		T29	14		T75	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T27	9		T134	17		T168	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T29	12		T82	2		T245	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T76	11		T211	13		T214	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T256	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T182	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T257	8		T258	1		T94	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T30	1		T174	14		T75	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	1		T13	9		T31	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T31	5		T146	10		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	7		T136	14		T176	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T26	7		T28	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T30	1		T190	16		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	1		T133	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T36	1		T166	7		T216	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1496	1			T1	2		T2	1		T7	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T147	1		T66	10		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T33	9		T213	1		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T26	15		T76	1		T38	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	1		T135	1		T153	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T6	12		T11	14		T13	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	1		T14	6		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T29	16		T191	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T26	13		T29	30		T75	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T27	12		T217	1		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T256	5		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T182	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T257	3		T94	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T30	2		T174	7		T75	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	10		T174	12		T146	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T146	12		T165	4		T216	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	8		T136	8		T176	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T26	2		T28	2		T135	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T30	2		T145	13		T75	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T146	17		T37	2		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T166	7		T216	4		T226	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	908	1			T1	18		T7	6		T79	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T66	7		T152	2		T166	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T33	3		T37	1		T158	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T26	10		T76	2		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T135	2		T153	9		T218	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	13		T11	12		T13	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T14	1		T38	2		T228	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	17		T156	24		T159	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T26	9		T29	26		T75	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T27	9		T76	11		T159	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T30	3		T31	1		T174	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	1		T13	11		T31	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T146	13		T165	5		T216	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T11	9		T145	14		T259	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	1		T26	3		T28	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T30	3		T190	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T1	20		T2	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T36	1		T66	8		T166	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T7	7		T33	6		T158	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T147	1		T76	3		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	1		T33	2		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T26	11		T166	2		T204	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	5		T135	3		T153	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	14		T11	13		T13	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	1		T213	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T29	18		T217	1		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T26	10		T29	15		T75	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T27	10		T142	1		T134	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T29	13		T35	1		T82	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T76	12		T211	14		T214	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T31	4		T174	13		T34	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	8		T31	9		T174	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T146	9		T165	3		T216	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	6		T162	10		T232	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T26	6		T37	1		T226	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T190	15		T80	10		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T32	38		T230	15		T38	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T66	9		T166	13		T216	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	2		T33	4		T158	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T38	4		T169	14		T221	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T163	4		T138	10		T218	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T26	14		T204	5		T244	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T14	2		T153	5		T41	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T6	11		T11	13		T13	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T157	7		T38	2		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T29	15		T156	19		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T26	12		T29	12		T158	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T27	11		T169	2		T260	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T29	16		T35	2		T82	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T211	12		T214	1		T23	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T256	6		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T182	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T257	4		T258	1		T94	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T30	3		T174	8		T75	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	1		T13	11		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T31	1		T146	13		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	9		T136	9		T176	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T26	3		T28	3		T135	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T30	3		T190	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T133	1		T146	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T36	1		T166	8		T216	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T1	20		T2	1		T7	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T147	1		T66	8		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T33	8		T213	1		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T26	11		T76	3		T38	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	1		T135	3		T153	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	14		T11	13		T13	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T5	1		T14	5		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T29	18		T191	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T26	10		T29	28		T75	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T27	10		T217	1		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T256	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T257	7		T94	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T174	13		T34	4		T243	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T13	8		T31	9		T174	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T31	4		T146	9		T165	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	6		T136	13		T176	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T26	6		T226	8		T227	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T190	15		T80	10		T162	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T37	1		T38	6		T237	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T166	6		T216	13		T226	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1178	1			T7	2		T32	38		T230	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T66	9		T166	7		T21	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T33	4		T158	15		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T26	14		T38	4		T169	32
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T153	5		T218	11		T41	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	11		T11	13		T13	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T14	2		T157	7		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T29	15		T156	19		T157	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T26	12		T29	28		T158	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T27	11		T169	2		T229	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19