Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23933

1

T1

20

T2

1

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3239

1

T5

1

T13

19

T26

56

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21681

1

T3

15

T5

3

T6

25

auto[1]

5491

1

T1

20

T2

1

T9

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	274	1			T26	9		T29	33		T33	2
values[1]	558	1			T146	21		T37	2		T75	2
values[2]	2794	1			T1	20		T2	1		T6	25
values[3]	647	1			T5	1		T28	3		T33	10
values[4]	726	1			T11	26		T14	7		T26	22
values[5]	671	1			T13	16		T29	27		T146	22
values[6]	732	1			T5	1		T11	15		T12	1
values[7]	785	1			T29	29		T31	8		T190	16
values[8]	708	1			T13	19		T26	25		T36	1
values[9]	750	1			T5	1		T7	9		T27	21
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	575	1			T146	21		T37	10		T75	2
values[1]	2855	1			T1	20		T2	1		T6	25
values[2]	593	1			T5	1		T33	10		T213	1
values[3]	736	1			T11	26		T14	7		T26	22
values[4]	865	1			T11	15		T12	1		T13	16
values[5]	660	1			T5	1		T29	29		T174	28
values[6]	716	1			T36	1		T147	1		T159	7
values[7]	654	1			T13	19		T26	25		T30	3
values[8]	775	1			T5	1		T7	9		T26	9
values[9]	109	1			T33	2		T142	1		T39	4
minimum	18634	1			T3	15		T7	49		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T37	1		T75	1		T76	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T146	12		T37	6		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T1	2		T2	1		T6	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T75	1		T76	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	1		T33	8		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T142	1		T157	9		T38	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	14		T14	6		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T26	13		T147	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	7		T12	1		T13	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T29	13		T156	17		T38	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T66	10		T216	3		T141	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	1		T29	17		T174	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T36	1		T147	1		T167	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T159	1		T135	1		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T30	1		T31	8		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	9		T26	15		T31	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	1		T7	3		T29	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T26	7		T27	12		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T142	1		T39	3		T169	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T33	1		T218	1		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18407	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T158	9		T166	8		T211	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T37	1		T75	1		T76	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T146	9		T37	2		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	930	1			T1	18		T6	13		T28	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T75	12		T76	2		T168	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T33	2		T156	8		T80	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T38	3		T216	4		T167	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	12		T14	1		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T26	9		T219	4		T170	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	8		T13	7		T174	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T29	14		T156	16		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T66	7		T216	3		T141	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T29	12		T174	12		T159	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T167	13		T138	7		T219	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T159	6		T135	2		T168	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T30	2		T220	9		T218	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	10		T26	10		T76	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	6		T29	17		T145	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T26	2		T27	9		T75	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T39	1		T204	8		T261	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T33	1		T222	8		T202	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T37	4		T66	3		T136	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T158	4		T166	7		T211	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T29	16		T142	1		T152	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T26	7		T33	1		T157	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T37	1		T75	1		T76	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T146	12		T158	9		T224	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T1	2		T2	1		T6	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T37	6		T75	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	1		T28	1		T33	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T142	1		T76	1		T157	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	14		T14	6		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T26	13		T147	1		T216	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	9		T146	10		T80	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T29	13		T38	8		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	7		T12	1		T174	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	1		T174	16		T156	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T147	1		T216	3		T167	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T29	17		T31	8		T190	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T36	1		T217	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	9		T26	15		T76	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	1		T7	3		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T27	12		T217	1		T75	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T29	17		T152	2		T167	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T26	2		T33	1		T141	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T37	1		T75	1		T76	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T146	9		T158	4		T224	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	901	1			T1	18		T6	13		T79	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T37	2		T75	12		T38	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T28	2		T33	2		T146	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T76	2		T38	3		T226	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	12		T14	1		T30	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T26	9		T216	4		T167	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	7		T146	12		T80	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T29	14		T38	2		T219	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	8		T174	7		T66	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T174	12		T156	16		T158	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T216	3		T167	13		T138	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	12		T135	2		T227	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T220	9		T218	4		T178	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	10		T26	10		T76	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	6		T30	2		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T27	9		T75	6		T166	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T37	2		T75	2		T76	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T146	10		T37	7		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T1	20		T2	1		T6	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T75	13		T76	3		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	1		T33	6		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T142	1		T157	1		T38	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T11	13		T14	5		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T26	10		T147	1		T219	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T11	9		T12	1		T13	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T29	15		T156	17		T38	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T66	8		T216	4		T141	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	1		T29	13		T174	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T36	1		T147	1		T167	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T159	7		T135	3		T168	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T30	3		T31	2		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	11		T26	11		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T5	1		T7	7		T29	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T26	3		T27	10		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T142	1		T39	3		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T33	2		T218	1		T222	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18533	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T158	5		T166	8		T211	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T34	4		T228	2		T229	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T146	11		T37	1		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T6	11		T32	38		T230	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T163	4		T232	11		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T33	4		T156	3		T80	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T157	8		T38	6		T216	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	13		T14	2		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T26	12		T170	14		T233	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	6		T13	8		T174	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T29	12		T156	16		T38	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T66	9		T216	2		T141	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T29	16		T174	15		T190	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T167	14		T138	1		T170	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T169	2		T211	10		T193	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T31	6		T236	9		T218	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	8		T26	14		T31	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	2		T29	15		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T26	6		T27	11		T157	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T39	1		T169	14		T204	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T202	4		T262	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T239	12		T95	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T158	8		T166	7		T211	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T29	18		T142	1		T152	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T26	3		T33	2		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T37	2		T75	2		T76	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T146	10		T158	5		T224	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T1	20		T2	1		T6	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T37	7		T75	13		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	1		T28	3		T33	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T142	1		T76	3		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	13		T14	5		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T26	10		T147	1		T216	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	8		T146	13		T80	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T29	15		T38	6		T219	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	9		T12	1		T174	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	1		T174	13		T156	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T147	1		T216	4		T167	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T29	13		T31	1		T190	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	1		T217	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	11		T26	11		T76	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	1		T7	7		T30	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T27	10		T217	1		T75	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T29	15		T167	11		T163	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T26	6		T157	7		T141	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T34	4		T238	8		T239	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T146	11		T158	8		T224	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T6	11		T32	38		T230	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T37	1		T38	2		T136	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T33	4		T156	3		T80	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T157	8		T38	6		T163	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	13		T14	2		T136	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T26	12		T216	13		T167	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	8		T146	9		T228	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T29	12		T38	4		T170	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	6		T174	13		T66	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T174	15		T156	16		T158	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T216	2		T167	14		T138	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T29	16		T31	7		T190	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T236	9		T218	11		T178	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	8		T26	14		T19	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	2		T31	6		T158	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T27	11		T237	13		T163	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19