Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23759

1

T1

20

T2

1

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3413

1

T5

2

T6

25

T11

41

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21319

1

T3

15

T5

1

T6

25

auto[1]

5853

1

T1

20

T2

1

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	18	1			T187	17		T263	1		-	-
values[0]	57	1			T168	9		T226	26		T183	9
values[1]	602	1			T174	21		T75	13		T80	3
values[2]	731	1			T6	25		T26	22		T29	33
values[3]	840	1			T14	7		T30	3		T217	1
values[4]	572	1			T31	5		T33	2		T133	1
values[5]	766	1			T7	9		T13	19		T28	3
values[6]	499	1			T5	1		T26	25		T29	29
values[7]	685	1			T5	1		T147	1		T75	7
values[8]	626	1			T11	41		T12	1		T29	27
values[9]	3249	1			T1	20		T2	1		T5	1
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	802	1			T29	33		T213	2		T75	13
values[1]	799	1			T6	25		T26	22		T174	21
values[2]	621	1			T14	7		T30	3		T31	5
values[3]	804	1			T28	3		T33	2		T146	22
values[4]	678	1			T5	1		T13	19		T26	25
values[5]	667	1			T5	1		T7	9		T29	29
values[6]	2645	1			T1	20		T2	1		T9	3
values[7]	634	1			T11	41		T29	27		T31	3
values[8]	873	1			T13	16		T27	21		T30	3
values[9]	120	1			T5	1		T26	9		T165	8
minimum	18529	1			T3	15		T7	49		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T213	1		T80	1		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T29	16		T213	1		T75	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T26	13		T191	1		T146	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T6	12		T174	14		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T30	1		T31	5		T190	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	6		T217	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T28	1		T33	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T146	10		T156	4		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	9		T217	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T5	1		T26	15		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T7	3		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T29	17		T133	2		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1480	1			T1	2		T2	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	1		T174	16		T75	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T37	1		T151	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	21		T29	13		T31	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	9		T27	12		T31	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T30	1		T80	11		T38	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T26	7		T165	4		T218	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T5	1		T264	1		T40	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18390	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T265	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T80	2		T165	1		T159	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T29	17		T75	12		T159	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T26	9		T146	9		T166	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	13		T174	7		T38	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T30	2		T75	1		T220	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T14	1		T76	5		T219	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T28	2		T33	1		T224	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T146	12		T156	8		T76	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	10		T146	17		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T26	10		T145	13		T76	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T7	6		T152	2		T41	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T29	12		T216	4		T167	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	882	1			T1	18		T79	18		T225	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T174	12		T75	6		T249	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	1		T135	2		T176	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	20		T29	14		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	7		T27	9		T33	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T30	2		T80	4		T38	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T26	2		T165	4		T218	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T40	2		T266	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T187	9		T263	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T267	4		T102	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T168	1		T226	13		T183	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T80	1		T165	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T174	14		T75	1		T259	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T26	13		T213	1		T146	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T6	12		T29	16		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T30	1		T190	16		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	6		T217	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T31	5		T33	1		T75	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T133	1		T146	10		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T7	3		T13	9		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T142	1		T145	1		T156	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T163	9		T34	5		T169	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	1		T26	15		T29	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	1		T152	1		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T147	1		T75	1		T167	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T36	1		T151	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	21		T12	1		T29	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1706	1			T1	2		T2	1		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T5	1		T30	1		T31	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T187	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T267	2		T102	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T168	8		T226	13		T183	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T80	2		T165	1		T134	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T174	7		T75	12		T159	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T26	9		T146	9		T159	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	13		T29	17		T38	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T30	2		T220	9		T167	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	1		T76	5		T228	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T33	1		T75	1		T162	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T146	12		T76	11		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T7	6		T13	10		T28	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T145	13		T156	8		T76	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T34	6		T160	12		T268	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T26	10		T29	12		T216	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T152	2		T160	6		T41	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T75	6		T167	13		T141	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T135	2		T176	8		T197	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	20		T29	14		T174	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T1	18		T13	7		T26	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T30	2		T80	4		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T213	1		T80	3		T165	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T29	18		T213	1		T75	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T26	10		T191	1		T146	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T6	14		T174	8		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T30	3		T31	1		T190	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	5		T217	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T28	3		T33	2		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T146	13		T156	9		T76	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T13	11		T217	1		T146	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	1		T26	11		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	1		T7	7		T152	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T29	13		T133	2		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T1	20		T2	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	1		T174	13		T75	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T37	2		T151	1		T135	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	22		T29	15		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	8		T27	10		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T30	3		T80	5		T38	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T26	3		T165	5		T218	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T5	1		T264	1		T40	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18528	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T265	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T169	14		T226	8		T139	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T29	15		T136	13		T153	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T26	12		T146	11		T157	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	11		T174	13		T38	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T31	4		T190	15		T167	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	2		T157	8		T260	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T224	10		T162	10		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T146	9		T156	3		T66	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	8		T37	1		T156	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T26	14		T193	11		T269	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	2		T169	18		T137	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T29	16		T216	13		T167	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1157	1			T32	38		T230	15		T231	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T174	15		T270	10		T249	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T176	11		T140	15		T234	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	19		T29	12		T31	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	8		T27	11		T31	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T80	10		T38	2		T162	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T26	6		T165	3		T218	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T40	1		T266	3		T271	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T187	9		T263	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T267	3		T102	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T168	9		T226	14		T183	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T80	3		T165	2		T134	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T174	8		T75	13		T259	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T26	10		T213	1		T146	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T6	14		T29	18		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T30	3		T190	1		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	5		T217	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T31	1		T33	2		T75	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T133	1		T146	13		T76	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T7	7		T13	11		T28	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T142	1		T145	14		T156	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T163	1		T34	7		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	1		T26	11		T29	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	1		T152	3		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T147	1		T75	7		T167	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T36	1		T151	1		T135	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T11	22		T12	1		T29	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1403	1			T1	20		T2	1		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T5	1		T30	3		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T187	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T267	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T226	12		T183	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T169	14		T226	8		T139	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T174	13		T136	13		T153	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T26	12		T146	11		T237	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	11		T29	15		T38	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T190	15		T157	7		T167	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	2		T157	8		T228	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T31	4		T162	10		T166	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T146	9		T158	8		T166	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	2		T13	8		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T156	3		T66	9		T17	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T163	8		T34	4		T169	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T26	14		T29	16		T216	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T137	8		T41	2		T214	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T167	14		T35	2		T141	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T176	11		T239	13		T234	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	19		T29	12		T174	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T13	8		T26	6		T27	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T31	2		T80	10		T38	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19