Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23753

1

T1

20

T2

1

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3419

1

T5

1

T6

25

T7

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21381

1

T3

15

T5

3

T7

58

auto[1]

5791

1

T1

20

T2

1

T6

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	59	1			T13	16		T226	26		T22	3
values[0]	57	1			T157	9		T272	14		T268	3
values[1]	635	1			T5	1		T29	29		T33	10
values[2]	750	1			T13	19		T26	31		T29	33
values[3]	639	1			T12	1		T76	3		T80	15
values[4]	557	1			T6	25		T30	3		T190	16
values[5]	739	1			T27	21		T30	3		T213	1
values[6]	629	1			T5	2		T29	27		T31	8
values[7]	590	1			T7	9		T11	26		T146	18
values[8]	2748	1			T1	20		T2	1		T9	3
values[9]	1242	1			T11	15		T14	7		T26	25
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	867	1			T5	1		T13	19		T29	29
values[1]	643	1			T26	31		T29	33		T31	3
values[2]	691	1			T12	1		T147	1		T80	15
values[3]	675	1			T6	25		T27	21		T30	6
values[4]	647	1			T5	1		T31	8		T213	1
values[5]	653	1			T5	1		T29	27		T174	21
values[6]	2752	1			T1	20		T2	1		T7	9
values[7]	528	1			T11	15		T26	25		T31	5
values[8]	940	1			T13	16		T14	7		T28	3
values[9]	249	1			T36	1		T33	2		T147	1
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	1		T29	17		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	9		T33	8		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T26	7		T146	10		T40	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T26	13		T29	16		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	1		T80	11		T38	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T147	1		T15	3		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T146	12		T260	6		T214	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	12		T27	12		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T31	8		T156	4		T237	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	1		T213	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	1		T66	10		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T29	13		T174	14		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T1	2		T2	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	3		T158	13		T165	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T31	5		T133	1		T37	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	7		T26	15		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T13	9		T14	6		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T28	1		T159	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T147	1		T136	14		T227	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T36	1		T33	1		T187	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T29	12		T156	16		T158	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	10		T33	2		T174	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T26	2		T146	12		T40	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T26	9		T29	17		T76	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T80	4		T38	3		T167	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T219	10		T244	9		T183	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T146	9		T260	14		T273	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	13		T27	9		T30	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T156	8		T274	4		T215	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T75	12		T166	8		T216	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T66	7		T134	17		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T29	14		T174	7		T146	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	910	1			T1	18		T11	12		T75	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	6		T158	14		T165	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T37	2		T75	6		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	8		T26	10		T152	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	7		T14	1		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T28	2		T159	6		T152	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T136	8		T227	16		T275	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T33	1		T187	12		T276	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T13	9		T226	13		T277	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T22	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T157	9		T272	14		T268	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T278	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T29	17		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T33	8		T217	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T26	7		T146	10		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T13	9		T26	13		T29	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T80	11		T38	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T76	1		T15	3		T140	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T146	12		T236	10		T260	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	12		T30	1		T190	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T156	4		T237	14		T274	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T27	12		T30	1		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	1		T31	8		T226	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	1		T29	13		T174	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	14		T147	1		T75	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	3		T146	1		T158	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1499	1			T1	2		T2	1		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T133	1		T157	8		T165	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T14	6		T147	1		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T11	7		T26	15		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T13	7		T226	13		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T22	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T268	2		T279	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T278	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T29	12		T156	16		T158	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T33	2		T145	13		T76	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T26	2		T146	12		T167	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	10		T26	9		T29	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T80	4		T38	3		T167	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T76	2		T244	9		T183	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T146	9		T260	14		T273	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T6	13		T30	2		T162	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T156	8		T274	4		T280	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T27	9		T30	2		T162	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T226	2		T281	12		T244	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T29	14		T174	7		T75	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	12		T75	1		T66	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	6		T146	17		T158	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	915	1			T1	18		T37	2		T75	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T165	4		T152	17		T136	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	1		T37	1		T80	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T11	8		T26	10		T28	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	1		T29	13		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	11		T33	6		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T26	3		T146	13		T40	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T26	10		T29	18		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	1		T80	5		T38	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T147	1		T15	3		T219	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T146	10		T260	15		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	14		T27	10		T30	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T31	1		T156	9		T237	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	1		T213	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	1		T66	8		T134	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T29	15		T174	8		T146	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T1	20		T2	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	7		T158	15		T165	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T31	1		T133	1		T37	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	9		T26	11		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	8		T14	5		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T28	3		T159	7		T152	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T147	1		T136	9		T227	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T36	1		T33	2		T187	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T29	16		T156	16		T157	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	8		T33	4		T174	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T26	6		T146	9		T40	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T26	12		T29	15		T31	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T80	10		T38	6		T167	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T140	15		T244	3		T183	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T146	11		T260	5		T214	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	11		T27	11		T190	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T31	7		T156	3		T237	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T166	6		T216	2		T169	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T66	9		T153	5		T226	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T29	12		T174	13		T34	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T11	13		T32	38		T230	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	2		T158	12		T165	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T31	4		T37	1		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T11	6		T26	14		T157	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	8		T14	2		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T163	8		T228	12		T15	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T136	13		T227	16		T252	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T187	11		T282	8		T276	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T13	8		T226	14		T277	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T22	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T157	1		T272	1		T268	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T278	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	1		T29	13		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T33	6		T217	1		T145	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T26	3		T146	13		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	11		T26	10		T29	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	1		T80	5		T38	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T76	3		T15	3		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T146	10		T236	1		T260	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	14		T30	3		T190	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T156	9		T237	1		T274	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T27	10		T30	3		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T5	1		T31	1		T226	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	1		T29	15		T174	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	13		T147	1		T75	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	7		T146	18		T158	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T1	20		T2	1		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T133	1		T157	1		T165	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T14	5		T147	1		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T11	9		T26	11		T28	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T13	8		T226	12		T277	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T157	8		T272	13		T279	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T29	16		T156	16		T158	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T33	4		T232	11		T238	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T26	6		T146	9		T167	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	8		T26	12		T29	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T80	10		T38	6		T167	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T140	15		T244	3		T270	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T146	11		T236	9		T260	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	11		T190	15		T162	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T156	3		T237	13		T274	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T27	11		T162	10		T166	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T31	7		T226	8		T193	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T29	12		T174	13		T169	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T11	13		T66	9		T38	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	2		T158	12		T216	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1167	1			T31	4		T32	38		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T157	7		T165	3		T136	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T14	2		T158	8		T136	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T11	6		T26	14		T163	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19