Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23842

1

T1

20

T2

1

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3330

1

T5

1

T6

25

T11

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21583

1

T3

15

T7

49

T8

13

auto[1]

5589

1

T1

20

T2

1

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	224	1			T26	22		T29	29		T158	27
values[0]	1	1			T258	1		-	-		-	-
values[1]	653	1			T5	1		T13	19		T30	3
values[2]	734	1			T11	15		T31	5		T146	22
values[3]	586	1			T26	9		T28	3		T30	3
values[4]	720	1			T5	1		T36	1		T133	1
values[5]	2672	1			T1	20		T2	1		T7	9
values[6]	867	1			T26	25		T33	12		T213	1
values[7]	652	1			T6	25		T12	1		T13	16
values[8]	628	1			T5	1		T11	26		T14	7
values[9]	908	1			T27	21		T29	27		T213	1
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	614	1			T5	1		T13	19		T30	3
values[1]	786	1			T11	15		T145	14		T146	22
values[2]	620	1			T5	1		T26	9		T28	3
values[3]	2823	1			T1	20		T2	1		T9	3
values[4]	677	1			T7	9		T33	10		T147	1
values[5]	747	1			T12	1		T26	25		T33	2
values[6]	653	1			T6	25		T13	16		T80	3
values[7]	673	1			T5	1		T11	26		T14	7
values[8]	840	1			T26	22		T27	21		T29	27
values[9]	73	1			T29	29		T35	3		T268	3
minimum	18666	1			T3	15		T7	49		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	9		T30	1		T31	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T5	1		T31	8		T174	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	7		T145	1		T146	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T259	1		T162	11		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T26	7		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T30	1		T190	16		T75	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T1	2		T2	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T36	1		T66	10		T166	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T7	3		T33	8		T224	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T147	1		T76	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	1		T33	1		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T26	15		T142	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T80	1		T135	1		T153	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	12		T13	9		T157	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	1		T14	6		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	14		T29	16		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T29	13		T75	1		T76	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T26	13		T27	12		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T35	3		T283	1		T102	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T29	17		T268	1		T23	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18423	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T31	3		T167	7		T163	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	10		T30	2		T174	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T174	12		T146	9		T220	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	8		T145	13		T146	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T162	2		T159	13		T152	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T26	2		T28	2		T37	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T30	2		T75	12		T80	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T1	18		T146	17		T79	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T66	7		T166	14		T216	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	6		T33	2		T224	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T76	2		T38	2		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T33	1		T37	1		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T26	10		T166	1		T204	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T80	2		T135	2		T153	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T6	13		T13	7		T167	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T14	1		T228	5		T249	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	12		T29	17		T156	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T29	14		T75	1		T76	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T26	9		T27	9		T76	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T102	5		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T29	12		T268	2		T23	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T37	4		T75	6		T66	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T167	6		T228	16		T284	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T158	13		T35	3		T285	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T26	13		T29	17		T168	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T258	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	9		T30	1		T174	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	1		T31	11		T174	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	7		T31	5		T146	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T176	10		T260	13		T141	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T26	7		T28	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T30	1		T190	16		T75	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	1		T133	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T36	1		T166	15		T216	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T1	2		T2	1		T7	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T147	1		T66	10		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T33	9		T213	1		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T26	15		T142	1		T76	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	1		T80	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	12		T13	9		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	1		T14	6		T157	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	14		T29	16		T191	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T29	13		T213	1		T75	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T27	12		T217	1		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T158	14		T286	10		T82	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T26	9		T29	12		T168	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	10		T30	2		T174	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T174	12		T146	9		T220	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	8		T146	12		T165	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T176	8		T260	16		T141	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T26	2		T28	2		T145	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T30	2		T75	12		T80	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T146	17		T37	2		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T166	14		T216	4		T226	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	905	1			T1	18		T7	6		T79	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T66	7		T152	2		T219	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T33	3		T37	1		T158	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T26	10		T76	2		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T80	2		T135	2		T153	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T6	13		T13	7		T166	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T14	1		T228	5		T244	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	12		T29	17		T156	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T29	14		T75	1		T76	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T27	9		T76	11		T134	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T13	11		T30	3		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T5	1		T31	1		T174	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	9		T145	14		T146	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T259	1		T162	3		T159	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	1		T26	3		T28	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T30	3		T190	1		T75	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T1	20		T2	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T36	1		T66	8		T166	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	7		T33	6		T224	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T147	1		T76	3		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T12	1		T33	2		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T26	11		T142	1		T166	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T80	3		T135	3		T153	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T6	14		T13	8		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	1		T14	5		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	13		T29	18		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T29	15		T75	2		T76	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T26	10		T27	10		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T35	1		T283	1		T102	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T29	13		T268	3		T23	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18555	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T31	1		T167	7		T163	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	8		T31	4		T174	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T31	7		T174	15		T146	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	6		T146	9		T165	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T162	10		T232	11		T176	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T26	6		T37	1		T272	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T190	15		T80	10		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T32	38		T230	15		T38	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T66	9		T166	13		T216	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	2		T33	4		T224	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T38	4		T221	10		T270	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T158	15		T163	4		T138	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T26	14		T169	18		T204	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T153	5		T41	2		T287	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	11		T13	8		T157	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	2		T157	7		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	13		T29	15		T156	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T29	12		T158	20		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T26	12		T27	11		T169	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T35	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T29	16		T23	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T34	4		T221	2		T82	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T31	2		T167	6		T163	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T158	15		T35	1		T285	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T26	10		T29	13		T168	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T258	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	11		T30	3		T174	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T31	2		T174	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	9		T31	1		T146	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T176	9		T260	17		T141	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T26	3		T28	3		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T30	3		T190	1		T75	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	1		T133	1		T146	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T36	1		T166	16		T216	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T1	20		T2	1		T7	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T147	1		T66	8		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T33	8		T213	1		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T26	11		T142	1		T76	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	1		T80	3		T135	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	14		T13	8		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	1		T14	5		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	13		T29	18		T191	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T29	15		T213	1		T75	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T27	10		T217	1		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T158	12		T35	2		T82	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T26	12		T29	16		T169	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	8		T174	13		T34	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T31	9		T174	15		T146	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	6		T31	4		T146	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T176	9		T260	12		T141	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T26	6		T227	16		T272	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T190	15		T80	10		T162	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T37	1		T38	6		T237	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T166	13		T216	13		T226	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T7	2		T32	38		T230	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T66	9		T270	11		T21	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T33	4		T158	15		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T26	14		T38	4		T169	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T153	5		T218	11		T41	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	11		T13	8		T167	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	2		T157	7		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	13		T29	15		T156	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T29	12		T158	8		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T27	11		T229	2		T260	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19