Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23795

1

T1

20

T2

1

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3377

1

T5

3

T6

25

T11

41

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21412

1

T3

15

T6

25

T7

49

auto[1]

5760

1

T1

20

T2

1

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	257	1			T31	8		T38	5		T158	27
values[0]	6	1			T102	6		-	-		-	-
values[1]	642	1			T75	13		T80	3		T165	2
values[2]	725	1			T6	25		T26	22		T29	33
values[3]	825	1			T14	7		T30	3		T31	5
values[4]	641	1			T33	2		T133	1		T146	22
values[5]	736	1			T7	9		T13	19		T28	3
values[6]	487	1			T5	1		T26	25		T29	29
values[7]	653	1			T5	1		T147	1		T75	7
values[8]	619	1			T11	41		T12	1		T29	27
values[9]	3054	1			T1	20		T2	1		T5	1
minimum	18527	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	666	1			T26	22		T29	33		T213	1
values[1]	726	1			T6	25		T213	1		T174	21
values[2]	650	1			T14	7		T30	3		T31	5
values[3]	758	1			T28	3		T33	2		T146	22
values[4]	701	1			T5	1		T7	9		T13	19
values[5]	649	1			T5	1		T29	29		T133	2
values[6]	2655	1			T1	20		T2	1		T9	3
values[7]	633	1			T11	41		T29	27		T31	3
values[8]	907	1			T5	1		T13	16		T27	21
values[9]	94	1			T26	9		T165	8		T218	16
minimum	18733	1			T3	15		T7	49		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T26	13		T165	1		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T29	16		T213	1		T75	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T213	1		T174	14		T190	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	12		T147	1		T38	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T30	1		T31	5		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	6		T217	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T28	1		T33	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T146	10		T156	4		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	3		T13	9		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	1		T26	15		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T152	1		T216	14		T169	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	1		T29	17		T133	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1506	1			T1	2		T2	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	1		T75	1		T34	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T37	1		T151	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	21		T29	13		T31	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T13	9		T27	12		T31	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	1		T30	1		T80	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T26	7		T165	4		T218	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T288	17		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18438	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T259	1		T159	1		T168	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T26	9		T165	1		T159	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T29	17		T75	12		T136	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T174	7		T146	9		T138	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	13		T38	3		T166	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T30	2		T75	1		T76	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T14	1		T219	10		T260	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T28	2		T33	1		T224	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T146	12		T156	8		T76	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	6		T13	10		T146	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T26	10		T145	13		T37	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T152	2		T216	4		T41	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T29	12		T167	13		T141	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	891	1			T1	18		T79	18		T225	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T75	6		T34	6		T249	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T37	1		T135	2		T176	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	20		T29	14		T174	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	7		T27	9		T33	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T30	2		T80	4		T38	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T26	2		T165	4		T218	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T288	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T37	4		T66	3		T80	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T159	13		T168	8		T281	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T31	8		T158	13		T165	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T38	3		T264	1		T289	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T102	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T80	1		T165	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T75	1		T259	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T26	13		T213	1		T174	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	12		T29	16		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T30	1		T31	5		T190	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	6		T217	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T33	1		T75	1		T162	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T133	1		T146	10		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	3		T13	9		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T142	1		T145	1		T37	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T152	1		T216	14		T163	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	1		T26	15		T29	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T35	1		T160	1		T137	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	1		T147	1		T75	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T36	1		T151	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	21		T12	1		T29	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T1	2		T2	1		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	1		T30	1		T31	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18389	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T158	14		T165	4		T244	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T38	2		T289	13		T290	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T102	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T80	2		T165	1		T134	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T75	12		T159	13		T136	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T26	9		T174	7		T146	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	13		T29	17		T38	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T30	2		T76	5		T220	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	1		T228	16		T219	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T33	1		T75	1		T162	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T146	12		T76	11		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T7	6		T13	10		T28	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T145	13		T37	2		T156	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T152	2		T216	4		T268	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T26	10		T29	12		T291	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T160	6		T41	2		T244	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T75	6		T167	13		T34	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T135	2		T176	8		T197	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	20		T29	14		T174	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T1	18		T13	7		T26	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T30	2		T80	4		T162	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T26	10		T165	2		T159	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T29	18		T213	1		T75	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T213	1		T174	8		T190	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	14		T147	1		T38	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T30	3		T31	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	5		T217	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T28	3		T33	2		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T146	13		T156	9		T76	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T7	7		T13	11		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	1		T26	11		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T152	3		T216	5		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	1		T29	13		T133	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T1	20		T2	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	1		T75	7		T34	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T37	2		T151	1		T135	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	22		T29	15		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T13	8		T27	10		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T5	1		T30	3		T80	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T26	3		T165	5		T218	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T288	4		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18579	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T259	1		T159	14		T168	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T26	12		T169	14		T226	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T29	15		T136	13		T153	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T174	13		T190	15		T146	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	11		T38	6		T228	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T31	4		T157	7		T167	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	2		T157	8		T260	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T224	10		T162	10		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T146	9		T156	3		T66	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T13	8		T166	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T26	14		T37	1		T156	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T216	13		T169	18		T137	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T29	16		T167	14		T35	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T32	38		T230	15		T231	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T34	4		T270	10		T249	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T176	11		T252	13		T234	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	19		T29	12		T31	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	8		T27	11		T31	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T80	10		T38	2		T162	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T26	6		T165	3		T218	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T288	16		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T280	10		T292	4		T198	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T178	10		T293	4		T294	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T31	1		T158	15		T165	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T38	3		T264	1		T289	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T102	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T80	3		T165	2		T134	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T75	13		T259	1		T159	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T26	10		T213	1		T174	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	14		T29	18		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T30	3		T31	1		T190	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	5		T217	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T33	2		T75	2		T162	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T133	1		T146	13		T76	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T7	7		T13	11		T28	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T142	1		T145	14		T37	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T152	3		T216	5		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T26	11		T29	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T35	1		T160	7		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	1		T147	1		T75	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T36	1		T151	1		T135	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T11	22		T12	1		T29	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T1	20		T2	1		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T5	1		T30	3		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18527	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T31	7		T158	12		T165	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T38	2		T289	14		T290	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T169	14		T226	8		T139	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T136	13		T153	5		T226	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T26	12		T174	13		T146	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	11		T29	15		T38	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T31	4		T190	15		T157	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	2		T157	8		T228	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T162	10		T235	2		T233	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T146	9		T158	8		T166	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	2		T13	8		T224	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T37	1		T156	19		T66	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T216	13		T163	8		T169	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T26	14		T29	16		T291	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T137	8		T41	2		T214	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T167	14		T34	4		T35	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T176	11		T252	13		T239	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	19		T29	12		T174	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T13	8		T26	6		T27	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T31	2		T80	10		T162	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19