Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27172

1

T1

20

T2

1

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23621

1

T1

20

T2

1

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3551

1

T5

1

T11

41

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21250

1

T3

15

T5

1

T7

58

auto[1]

5922

1

T1

20

T2

1

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23327

1

T1

2

T2

1

T3

15

auto[1]

3845

1

T1

18

T6

13

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	487	1			T14	5		T43	2		T33	4
values[0]	36	1			T33	2		T142	1		T227	33
values[1]	708	1			T5	1		T13	19		T26	25
values[2]	2936	1			T1	20		T2	1		T9	3
values[3]	574	1			T5	1		T6	25		T29	27
values[4]	618	1			T11	26		T12	1		T26	9
values[5]	697	1			T11	15		T26	22		T33	10
values[6]	729	1			T5	1		T14	7		T28	3
values[7]	653	1			T29	29		T217	1		T174	28
values[8]	616	1			T7	9		T13	16		T31	8
values[9]	1033	1			T75	7		T76	3		T151	2
minimum	18085	1			T3	15		T7	49		T8	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	937	1			T5	1		T13	19		T27	21
values[1]	2858	1			T1	20		T2	1		T9	3
values[2]	570	1			T5	1		T6	25		T11	26
values[3]	688	1			T11	15		T12	1		T26	31
values[4]	660	1			T28	3		T33	10		T191	1
values[5]	686	1			T5	1		T14	7		T38	5
values[6]	595	1			T29	29		T31	8		T217	1
values[7]	752	1			T7	9		T13	16		T133	1
values[8]	684	1			T75	7		T76	3		T151	2
values[9]	205	1			T140	12		T141	23		T192	1
minimum	18537	1			T3	15		T7	49		T8	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

3905

1

T6

11

T7

2

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T5	1		T27	12		T29	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	9		T142	1		T80	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1509	1			T1	2		T2	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T26	15		T145	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	1		T6	12		T157	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	14		T29	13		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T26	7		T31	3		T75	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	7		T12	1		T26	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T33	8		T37	6		T66	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T28	1		T191	1		T146	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	6		T162	7		T138	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	1		T38	3		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T29	17		T217	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T31	8		T174	16		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	3		T13	9		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T146	1		T158	29		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T75	1		T76	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T151	2		T165	1		T259	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T140	12		T192	1		T249	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T141	13		T251	12		T242	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18390	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T284	1		T271	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T27	9		T29	17		T33	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	10		T80	4		T159	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T1	18		T30	2		T79	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T26	10		T145	13		T136	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T6	13		T162	2		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	12		T29	14		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T26	2		T75	1		T152	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	8		T26	9		T156	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T33	2		T37	2		T66	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T28	2		T146	9		T76	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T14	1		T162	12		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T38	2		T204	8		T15	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T29	12		T156	8		T224	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T174	12		T80	2		T38	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	6		T13	7		T146	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T146	17		T158	18		T216	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T75	6		T76	2		T135	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T165	1		T159	8		T167	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T249	4		T295	12		T202	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T141	10		T242	4		T296	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T284	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	463	1			T14	5		T43	2		T33	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T215	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T33	1		T227	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T142	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	1		T27	12		T31	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	9		T26	15		T80	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T1	2		T2	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T213	1		T145	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T6	12		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	13		T30	1		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T26	7		T31	3		T75	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	14		T12	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T33	8		T37	6		T158	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	7		T26	13		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	6		T66	10		T224	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	1		T28	1		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T29	17		T217	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T174	16		T133	1		T147	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	3		T13	9		T146	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T31	8		T146	1		T80	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T75	1		T76	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T151	2		T165	1		T259	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17947	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T297	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T215	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T33	1		T227	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T27	9		T174	7		T159	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	10		T26	10		T80	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	945	1			T1	18		T29	17		T30	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T145	13		T216	3		T167	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T6	13		T220	9		T40	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T29	14		T30	2		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T26	2		T75	1		T162	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	12		T156	16		T250	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T33	2		T37	2		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	8		T26	9		T146	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	1		T66	7		T224	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T28	2		T38	2		T221	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T29	12		T156	8		T152	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T174	12		T38	3		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	6		T13	7		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T146	17		T80	2		T158	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T75	6		T76	2		T135	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T165	1		T159	8		T216	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	4		T66	3		T136	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T5	1		T27	10		T29	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T13	11		T142	1		T80	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1220	1			T1	20		T2	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T26	11		T145	14		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	1		T6	14		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	13		T29	15		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T26	3		T31	1		T75	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	9		T12	1		T26	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T33	6		T37	7		T66	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T28	3		T191	1		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	5		T162	13		T138	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	1		T38	3		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T29	13		T217	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T31	1		T174	13		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	7		T13	8		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T146	18		T158	20		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T75	7		T76	3		T135	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T151	2		T165	2		T259	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T140	1		T192	1		T249	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T141	11		T251	1		T242	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18528	1			T3	15		T7	49		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T284	8		T271	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T27	11		T29	15		T31	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	8		T80	10		T167	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T32	38		T230	15		T231	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T26	14		T136	14		T216	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T6	11		T157	8		T162	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	13		T29	12		T226	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T26	6		T31	2		T176	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	6		T26	12		T156	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T33	4		T37	1		T66	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T146	11		T169	16		T260	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T14	2		T162	6		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T38	2		T163	14		T204	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T29	16		T156	3		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T31	7		T174	15		T38	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	2		T13	8		T146	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T158	27		T216	13		T228	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T232	11		T35	2		T260	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T167	11		T138	9		T243	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T140	11		T249	5		T298	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T141	12		T251	11		T242	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	453	1			T14	5		T43	2		T33	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T215	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T33	2		T227	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T142	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	1		T27	10		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	11		T26	11		T80	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T1	20		T2	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T213	1		T145	14		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T6	14		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T29	15		T30	3		T37	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T26	3		T31	1		T75	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	13		T12	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T33	6		T37	7		T158	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	9		T26	10		T146	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	5		T66	8		T224	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	1		T28	3		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T29	13		T217	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T174	13		T133	1		T147	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	7		T13	8		T146	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T31	1		T146	18		T80	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T75	7		T76	3		T135	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T151	2		T165	2		T259	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18085	1			T3	15		T7	49		T8	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T140	11		T297	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T227	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T27	11		T31	4		T174	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	8		T26	14		T80	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T29	15		T32	38		T190	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T216	2		T167	14		T226	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T6	11		T157	8		T163	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T29	12		T136	14		T238	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T26	6		T31	2		T162	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	13		T156	16		T218	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T33	4		T37	1		T158	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	6		T26	12		T146	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	2		T66	9		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T38	2		T169	14		T140	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T29	16		T156	3		T166	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T174	15		T38	6		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T7	2		T13	8		T146	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T31	7		T158	27		T34	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T163	8		T232	11		T35	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T216	13		T167	11		T138	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23267

1

T1

20

T2

1

T3

15

auto[1]

auto[0]

3905

1

T6

11

T7

2

T11

19