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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.66 99.07 96.62 100.00 100.00 98.83 98.33 90.79


Total test records in report: 919
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T802 /workspace/coverage/default/16.adc_ctrl_poweron_counter.2716293391 May 07 03:25:32 PM PDT 24 May 07 03:25:34 PM PDT 24 4343789159 ps
T803 /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4144209370 May 07 03:25:20 PM PDT 24 May 07 03:31:38 PM PDT 24 162272750295 ps
T323 /workspace/coverage/default/39.adc_ctrl_clock_gating.2856415316 May 07 03:27:07 PM PDT 24 May 07 03:40:28 PM PDT 24 328758980847 ps
T279 /workspace/coverage/default/49.adc_ctrl_stress_all.2628067346 May 07 03:28:31 PM PDT 24 May 07 03:33:09 PM PDT 24 405322745364 ps
T49 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3818623510 May 07 03:22:01 PM PDT 24 May 07 03:22:10 PM PDT 24 5189880753 ps
T52 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.283433933 May 07 03:21:52 PM PDT 24 May 07 03:22:06 PM PDT 24 4355778599 ps
T50 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3362156985 May 07 03:21:55 PM PDT 24 May 07 03:22:00 PM PDT 24 2936663199 ps
T51 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3847353179 May 07 03:22:00 PM PDT 24 May 07 03:22:20 PM PDT 24 4241957366 ps
T804 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2369059210 May 07 03:22:01 PM PDT 24 May 07 03:22:05 PM PDT 24 371618884 ps
T53 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2334021401 May 07 03:22:02 PM PDT 24 May 07 03:22:10 PM PDT 24 8099736454 ps
T54 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1631762656 May 07 03:21:57 PM PDT 24 May 07 03:22:04 PM PDT 24 9366453925 ps
T104 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.797879673 May 07 03:21:53 PM PDT 24 May 07 03:21:56 PM PDT 24 569704706 ps
T59 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.530940716 May 07 03:22:08 PM PDT 24 May 07 03:22:14 PM PDT 24 527565158 ps
T805 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3639662022 May 07 03:22:08 PM PDT 24 May 07 03:22:12 PM PDT 24 490360027 ps
T806 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.768950466 May 07 03:22:08 PM PDT 24 May 07 03:22:11 PM PDT 24 464680706 ps
T127 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.368859113 May 07 03:22:00 PM PDT 24 May 07 03:22:03 PM PDT 24 579137999 ps
T60 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2570740624 May 07 03:21:51 PM PDT 24 May 07 03:21:56 PM PDT 24 394885676 ps
T83 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3264357315 May 07 03:22:09 PM PDT 24 May 07 03:22:13 PM PDT 24 464322319 ps
T105 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2285927776 May 07 03:21:51 PM PDT 24 May 07 03:23:20 PM PDT 24 26293007283 ps
T122 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2701689164 May 07 03:21:50 PM PDT 24 May 07 03:21:54 PM PDT 24 2699247110 ps
T55 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2086119438 May 07 03:22:03 PM PDT 24 May 07 03:22:10 PM PDT 24 3899763314 ps
T70 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3285948766 May 07 03:21:55 PM PDT 24 May 07 03:22:05 PM PDT 24 9127155094 ps
T71 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.852253369 May 07 03:22:06 PM PDT 24 May 07 03:22:21 PM PDT 24 4268814051 ps
T62 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1754648066 May 07 03:21:58 PM PDT 24 May 07 03:22:10 PM PDT 24 3994748013 ps
T807 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.41581971 May 07 03:22:08 PM PDT 24 May 07 03:22:11 PM PDT 24 443961475 ps
T61 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.952386498 May 07 03:22:07 PM PDT 24 May 07 03:22:11 PM PDT 24 598642015 ps
T63 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.868366661 May 07 03:21:55 PM PDT 24 May 07 03:22:01 PM PDT 24 426088488 ps
T128 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4240907107 May 07 03:21:54 PM PDT 24 May 07 03:22:42 PM PDT 24 53320421297 ps
T808 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1033862023 May 07 03:21:49 PM PDT 24 May 07 03:21:52 PM PDT 24 375796356 ps
T809 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2455873251 May 07 03:22:06 PM PDT 24 May 07 03:22:09 PM PDT 24 482429378 ps
T129 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1593093508 May 07 03:21:53 PM PDT 24 May 07 03:22:15 PM PDT 24 26658140731 ps
T810 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1359251394 May 07 03:22:03 PM PDT 24 May 07 03:22:07 PM PDT 24 489120819 ps
T123 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2036759428 May 07 03:22:06 PM PDT 24 May 07 03:22:16 PM PDT 24 2040556422 ps
T811 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2047567514 May 07 03:22:06 PM PDT 24 May 07 03:22:10 PM PDT 24 320480490 ps
T106 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2289716145 May 07 03:21:52 PM PDT 24 May 07 03:21:56 PM PDT 24 1371756437 ps
T812 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3804612483 May 07 03:22:06 PM PDT 24 May 07 03:22:10 PM PDT 24 329546357 ps
T64 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.625088272 May 07 03:22:00 PM PDT 24 May 07 03:22:05 PM PDT 24 527170282 ps
T813 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1521930708 May 07 03:22:06 PM PDT 24 May 07 03:22:10 PM PDT 24 373391227 ps
T124 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3157808180 May 07 03:22:05 PM PDT 24 May 07 03:22:17 PM PDT 24 2383083846 ps
T814 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.802608583 May 07 03:21:58 PM PDT 24 May 07 03:22:02 PM PDT 24 354975981 ps
T815 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3919151172 May 07 03:22:05 PM PDT 24 May 07 03:22:09 PM PDT 24 509414924 ps
T816 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4291636987 May 07 03:21:52 PM PDT 24 May 07 03:22:01 PM PDT 24 8632623424 ps
T125 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3254581557 May 07 03:22:00 PM PDT 24 May 07 03:22:03 PM PDT 24 462528513 ps
T817 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2820437554 May 07 03:22:06 PM PDT 24 May 07 03:22:09 PM PDT 24 334490076 ps
T818 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.921400118 May 07 03:22:02 PM PDT 24 May 07 03:22:05 PM PDT 24 521761530 ps
T819 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2100154466 May 07 03:21:59 PM PDT 24 May 07 03:22:04 PM PDT 24 820478635 ps
T65 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2761673641 May 07 03:22:02 PM PDT 24 May 07 03:22:06 PM PDT 24 457604517 ps
T820 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1773311610 May 07 03:22:03 PM PDT 24 May 07 03:22:06 PM PDT 24 641271187 ps
T107 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3562539607 May 07 03:21:59 PM PDT 24 May 07 03:22:03 PM PDT 24 453030315 ps
T821 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3015245099 May 07 03:22:01 PM PDT 24 May 07 03:22:07 PM PDT 24 622813309 ps
T822 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2319827522 May 07 03:21:58 PM PDT 24 May 07 03:22:01 PM PDT 24 562121338 ps
T126 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.128649063 May 07 03:21:48 PM PDT 24 May 07 03:21:55 PM PDT 24 3607047142 ps
T823 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2029115273 May 07 03:21:53 PM PDT 24 May 07 03:22:08 PM PDT 24 4385941156 ps
T824 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.610935925 May 07 03:21:57 PM PDT 24 May 07 03:22:01 PM PDT 24 681382180 ps
T825 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3811541552 May 07 03:22:00 PM PDT 24 May 07 03:22:03 PM PDT 24 474695497 ps
T826 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4148409283 May 07 03:22:13 PM PDT 24 May 07 03:22:15 PM PDT 24 494385448 ps
T827 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1619712965 May 07 03:21:59 PM PDT 24 May 07 03:22:03 PM PDT 24 480329755 ps
T828 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3741509334 May 07 03:22:05 PM PDT 24 May 07 03:22:29 PM PDT 24 8536944173 ps
T69 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.448935836 May 07 03:21:53 PM PDT 24 May 07 03:21:59 PM PDT 24 598011895 ps
T326 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2696346480 May 07 03:21:51 PM PDT 24 May 07 03:21:55 PM PDT 24 4574879798 ps
T108 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.686006375 May 07 03:21:55 PM PDT 24 May 07 03:21:59 PM PDT 24 943549579 ps
T829 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3878437899 May 07 03:22:05 PM PDT 24 May 07 03:22:08 PM PDT 24 319208126 ps
T109 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.994773070 May 07 03:21:53 PM PDT 24 May 07 03:21:56 PM PDT 24 359554862 ps
T830 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3659397318 May 07 03:21:58 PM PDT 24 May 07 03:22:01 PM PDT 24 368931797 ps
T831 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4172690014 May 07 03:21:53 PM PDT 24 May 07 03:21:57 PM PDT 24 449208452 ps
T832 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1348140876 May 07 03:22:02 PM PDT 24 May 07 03:22:06 PM PDT 24 519473376 ps
T833 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3260408320 May 07 03:22:04 PM PDT 24 May 07 03:22:07 PM PDT 24 418470996 ps
T834 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1598439913 May 07 03:21:59 PM PDT 24 May 07 03:22:06 PM PDT 24 4763705090 ps
T835 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3174830817 May 07 03:21:54 PM PDT 24 May 07 03:21:58 PM PDT 24 427379160 ps
T836 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4229006793 May 07 03:21:51 PM PDT 24 May 07 03:21:59 PM PDT 24 2459956398 ps
T837 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1558275183 May 07 03:22:04 PM PDT 24 May 07 03:22:07 PM PDT 24 344139383 ps
T114 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2087312990 May 07 03:21:54 PM PDT 24 May 07 03:21:58 PM PDT 24 419751154 ps
T838 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1231333469 May 07 03:22:03 PM PDT 24 May 07 03:22:13 PM PDT 24 5740098667 ps
T839 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3243479686 May 07 03:21:51 PM PDT 24 May 07 03:21:53 PM PDT 24 482824511 ps
T840 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1138552133 May 07 03:22:01 PM PDT 24 May 07 03:22:04 PM PDT 24 403231224 ps
T841 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2855759968 May 07 03:21:52 PM PDT 24 May 07 03:21:55 PM PDT 24 433852663 ps
T842 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1390537588 May 07 03:21:49 PM PDT 24 May 07 03:21:51 PM PDT 24 1466959632 ps
T843 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2518134738 May 07 03:22:02 PM PDT 24 May 07 03:22:05 PM PDT 24 406421803 ps
T844 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2330985516 May 07 03:22:02 PM PDT 24 May 07 03:22:05 PM PDT 24 733486670 ps
T110 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3671587472 May 07 03:21:49 PM PDT 24 May 07 03:21:53 PM PDT 24 1203410269 ps
T845 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3923187397 May 07 03:21:58 PM PDT 24 May 07 03:22:02 PM PDT 24 933815818 ps
T846 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2354849240 May 07 03:22:14 PM PDT 24 May 07 03:22:16 PM PDT 24 553232135 ps
T111 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2347513671 May 07 03:22:01 PM PDT 24 May 07 03:22:05 PM PDT 24 333476805 ps
T847 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2576954687 May 07 03:22:08 PM PDT 24 May 07 03:22:11 PM PDT 24 347925255 ps
T848 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.257518331 May 07 03:22:09 PM PDT 24 May 07 03:22:12 PM PDT 24 337107247 ps
T849 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.716697431 May 07 03:22:00 PM PDT 24 May 07 03:22:05 PM PDT 24 2543834622 ps
T850 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3151329389 May 07 03:22:00 PM PDT 24 May 07 03:22:15 PM PDT 24 3770085073 ps
T112 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2721358425 May 07 03:22:10 PM PDT 24 May 07 03:22:12 PM PDT 24 480555173 ps
T113 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4249322966 May 07 03:22:06 PM PDT 24 May 07 03:22:11 PM PDT 24 505212047 ps
T327 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2006091778 May 07 03:21:59 PM PDT 24 May 07 03:22:07 PM PDT 24 8577666989 ps
T328 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.58565824 May 07 03:22:00 PM PDT 24 May 07 03:22:07 PM PDT 24 9735194952 ps
T851 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3442182850 May 07 03:22:05 PM PDT 24 May 07 03:22:10 PM PDT 24 4628274224 ps
T852 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.954502731 May 07 03:22:03 PM PDT 24 May 07 03:22:16 PM PDT 24 4343795374 ps
T853 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2893092100 May 07 03:22:04 PM PDT 24 May 07 03:22:10 PM PDT 24 4856538745 ps
T115 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1336571141 May 07 03:22:09 PM PDT 24 May 07 03:22:12 PM PDT 24 513675839 ps
T854 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3925034746 May 07 03:21:57 PM PDT 24 May 07 03:22:03 PM PDT 24 4596962106 ps
T855 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3586433937 May 07 03:21:59 PM PDT 24 May 07 03:22:02 PM PDT 24 499550702 ps
T856 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1318444643 May 07 03:22:05 PM PDT 24 May 07 03:22:09 PM PDT 24 458571356 ps
T857 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3455522946 May 07 03:21:53 PM PDT 24 May 07 03:21:58 PM PDT 24 4772494382 ps
T858 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2378298853 May 07 03:21:57 PM PDT 24 May 07 03:22:01 PM PDT 24 378610718 ps
T859 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3776072042 May 07 03:22:00 PM PDT 24 May 07 03:22:03 PM PDT 24 359539092 ps
T860 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3914871374 May 07 03:22:03 PM PDT 24 May 07 03:22:08 PM PDT 24 812962270 ps
T861 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4059680443 May 07 03:22:05 PM PDT 24 May 07 03:22:09 PM PDT 24 520076397 ps
T862 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3454820418 May 07 03:21:59 PM PDT 24 May 07 03:22:07 PM PDT 24 4210331367 ps
T863 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.81228917 May 07 03:22:08 PM PDT 24 May 07 03:22:12 PM PDT 24 454067090 ps
T864 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.596592996 May 07 03:21:57 PM PDT 24 May 07 03:22:00 PM PDT 24 662575152 ps
T119 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1538881854 May 07 03:21:51 PM PDT 24 May 07 03:21:55 PM PDT 24 1117997854 ps
T865 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2573534753 May 07 03:22:08 PM PDT 24 May 07 03:22:10 PM PDT 24 391524250 ps
T866 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1220251211 May 07 03:21:53 PM PDT 24 May 07 03:21:58 PM PDT 24 439509904 ps
T867 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2308069841 May 07 03:22:00 PM PDT 24 May 07 03:22:05 PM PDT 24 689068382 ps
T868 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1877144077 May 07 03:22:03 PM PDT 24 May 07 03:22:07 PM PDT 24 844205824 ps
T869 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2898256352 May 07 03:22:13 PM PDT 24 May 07 03:22:16 PM PDT 24 4283292785 ps
T870 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3623683672 May 07 03:22:05 PM PDT 24 May 07 03:22:09 PM PDT 24 417375935 ps
T871 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2722265115 May 07 03:21:58 PM PDT 24 May 07 03:22:01 PM PDT 24 580107764 ps
T116 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.277901203 May 07 03:22:06 PM PDT 24 May 07 03:22:09 PM PDT 24 552111158 ps
T872 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2531577919 May 07 03:22:06 PM PDT 24 May 07 03:22:10 PM PDT 24 426423336 ps
T873 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.256526343 May 07 03:22:10 PM PDT 24 May 07 03:22:13 PM PDT 24 418188734 ps
T874 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.479743492 May 07 03:22:06 PM PDT 24 May 07 03:22:09 PM PDT 24 372234474 ps
T875 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2097475438 May 07 03:22:09 PM PDT 24 May 07 03:22:12 PM PDT 24 705891276 ps
T876 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.783140541 May 07 03:22:02 PM PDT 24 May 07 03:22:06 PM PDT 24 335515045 ps
T877 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3291287186 May 07 03:21:54 PM PDT 24 May 07 03:21:59 PM PDT 24 870895376 ps
T878 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2511750040 May 07 03:22:05 PM PDT 24 May 07 03:22:08 PM PDT 24 418702826 ps
T879 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1164504056 May 07 03:22:09 PM PDT 24 May 07 03:22:13 PM PDT 24 333121410 ps
T880 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.873003671 May 07 03:21:55 PM PDT 24 May 07 03:21:59 PM PDT 24 1226600357 ps
T881 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2589706257 May 07 03:21:53 PM PDT 24 May 07 03:21:59 PM PDT 24 664622147 ps
T882 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4134397436 May 07 03:22:01 PM PDT 24 May 07 03:22:06 PM PDT 24 4460024369 ps
T883 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3266248563 May 07 03:22:04 PM PDT 24 May 07 03:22:07 PM PDT 24 501600112 ps
T884 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.354222285 May 07 03:22:05 PM PDT 24 May 07 03:22:10 PM PDT 24 607109192 ps
T885 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1065146404 May 07 03:22:05 PM PDT 24 May 07 03:22:09 PM PDT 24 510064227 ps
T886 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.521985670 May 07 03:22:13 PM PDT 24 May 07 03:22:16 PM PDT 24 401267342 ps
T324 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2602995715 May 07 03:22:05 PM PDT 24 May 07 03:22:14 PM PDT 24 7972014490 ps
T117 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3817095007 May 07 03:21:58 PM PDT 24 May 07 03:22:01 PM PDT 24 500853204 ps
T887 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.893056001 May 07 03:22:09 PM PDT 24 May 07 03:22:13 PM PDT 24 398364604 ps
T888 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3866266407 May 07 03:22:00 PM PDT 24 May 07 03:22:03 PM PDT 24 514588900 ps
T118 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1647781703 May 07 03:21:53 PM PDT 24 May 07 03:21:57 PM PDT 24 1328262329 ps
T889 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.274031663 May 07 03:22:07 PM PDT 24 May 07 03:22:11 PM PDT 24 464265979 ps
T890 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1115543735 May 07 03:22:06 PM PDT 24 May 07 03:22:12 PM PDT 24 569322276 ps
T891 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1658911751 May 07 03:22:01 PM PDT 24 May 07 03:22:05 PM PDT 24 505864225 ps
T892 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1069184760 May 07 03:22:08 PM PDT 24 May 07 03:22:12 PM PDT 24 465805655 ps
T893 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.496846721 May 07 03:22:03 PM PDT 24 May 07 03:22:07 PM PDT 24 2894371452 ps
T894 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.7148239 May 07 03:21:52 PM PDT 24 May 07 03:21:54 PM PDT 24 666270834 ps
T895 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3915366259 May 07 03:22:03 PM PDT 24 May 07 03:22:07 PM PDT 24 411504514 ps
T896 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2730308784 May 07 03:21:46 PM PDT 24 May 07 03:21:49 PM PDT 24 437094348 ps
T897 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1030534733 May 07 03:22:05 PM PDT 24 May 07 03:22:08 PM PDT 24 404095969 ps
T898 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2532313485 May 07 03:22:07 PM PDT 24 May 07 03:22:10 PM PDT 24 328994751 ps
T120 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1911080374 May 07 03:22:13 PM PDT 24 May 07 03:22:15 PM PDT 24 466254572 ps
T899 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2257249170 May 07 03:22:03 PM PDT 24 May 07 03:22:07 PM PDT 24 365936546 ps
T900 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2784457176 May 07 03:22:05 PM PDT 24 May 07 03:22:08 PM PDT 24 324240378 ps
T901 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1418442260 May 07 03:22:13 PM PDT 24 May 07 03:22:15 PM PDT 24 559106976 ps
T902 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3464198874 May 07 03:21:55 PM PDT 24 May 07 03:22:00 PM PDT 24 1144133163 ps
T903 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1816154565 May 07 03:21:53 PM PDT 24 May 07 03:21:56 PM PDT 24 1072829677 ps
T904 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2296402874 May 07 03:21:54 PM PDT 24 May 07 03:21:59 PM PDT 24 428880183 ps
T905 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2044140223 May 07 03:21:53 PM PDT 24 May 07 03:21:57 PM PDT 24 403861653 ps
T906 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3247843290 May 07 03:22:08 PM PDT 24 May 07 03:22:12 PM PDT 24 408107581 ps
T907 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2277700218 May 07 03:21:56 PM PDT 24 May 07 03:22:06 PM PDT 24 8936011135 ps
T908 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1446704675 May 07 03:22:00 PM PDT 24 May 07 03:22:04 PM PDT 24 531951074 ps
T909 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3651414430 May 07 03:21:53 PM PDT 24 May 07 03:22:26 PM PDT 24 26736922437 ps
T121 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3914605321 May 07 03:21:57 PM PDT 24 May 07 03:22:21 PM PDT 24 12488191492 ps
T325 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.830848414 May 07 03:22:05 PM PDT 24 May 07 03:22:21 PM PDT 24 8182136651 ps
T910 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2909028245 May 07 03:22:04 PM PDT 24 May 07 03:22:09 PM PDT 24 908381170 ps
T911 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1576636203 May 07 03:22:08 PM PDT 24 May 07 03:22:11 PM PDT 24 351086833 ps
T912 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2152816939 May 07 03:22:08 PM PDT 24 May 07 03:22:17 PM PDT 24 2672752315 ps
T913 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.217719960 May 07 03:22:03 PM PDT 24 May 07 03:22:06 PM PDT 24 811280881 ps
T914 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1967533382 May 07 03:22:03 PM PDT 24 May 07 03:22:08 PM PDT 24 4940832352 ps
T915 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.326362060 May 07 03:22:05 PM PDT 24 May 07 03:22:08 PM PDT 24 453520823 ps
T916 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1649150007 May 07 03:21:51 PM PDT 24 May 07 03:21:54 PM PDT 24 292115544 ps
T917 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3406692870 May 07 03:22:01 PM PDT 24 May 07 03:22:03 PM PDT 24 369533433 ps
T918 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.585377686 May 07 03:21:56 PM PDT 24 May 07 03:21:59 PM PDT 24 301504895 ps
T919 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1861723276 May 07 03:22:04 PM PDT 24 May 07 03:22:19 PM PDT 24 4860857031 ps

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2145889113
Short name T7
Test name
Test status
Simulation time 253789905646 ps
CPU time 152.09 seconds
Started May 07 03:26:23 PM PDT 24
Finished May 07 03:28:56 PM PDT 24
Peak memory 202308 kb
Host smart-66223890-15a9-45e5-b2cd-0b9e5dd7cc8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145889113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2145889113
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3546973367
Short name T33
Test name
Test status
Simulation time 168663265343 ps
CPU time 364.34 seconds
Started May 07 03:25:41 PM PDT 24
Finished May 07 03:31:46 PM PDT 24
Peak memory 218164 kb
Host smart-ff0b367e-feee-410a-98e3-7d0c8003a8ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546973367 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3546973367
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3826849445
Short name T29
Test name
Test status
Simulation time 526222947502 ps
CPU time 151.15 seconds
Started May 07 03:26:24 PM PDT 24
Finished May 07 03:28:56 PM PDT 24
Peak memory 202408 kb
Host smart-de35a61c-6f0e-451b-8ec2-7c4795c5e00c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826849445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3826849445
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.952803090
Short name T136
Test name
Test status
Simulation time 1372636934257 ps
CPU time 1377.93 seconds
Started May 07 03:25:33 PM PDT 24
Finished May 07 03:48:33 PM PDT 24
Peak memory 210864 kb
Host smart-cc6092a0-8016-4c64-b083-4264f296a783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952803090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
952803090
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3882785155
Short name T26
Test name
Test status
Simulation time 503554813332 ps
CPU time 315.04 seconds
Started May 07 03:26:33 PM PDT 24
Finished May 07 03:31:49 PM PDT 24
Peak memory 202320 kb
Host smart-135efeba-8656-40b1-b20b-0a689e146156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882785155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3882785155
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1072480339
Short name T146
Test name
Test status
Simulation time 542088297117 ps
CPU time 539.68 seconds
Started May 07 03:25:06 PM PDT 24
Finished May 07 03:34:07 PM PDT 24
Peak memory 202332 kb
Host smart-acb0cbd5-62f9-4c00-8605-c7c5db614ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072480339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1072480339
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.732145282
Short name T6
Test name
Test status
Simulation time 167967049849 ps
CPU time 402.93 seconds
Started May 07 03:26:44 PM PDT 24
Finished May 07 03:33:28 PM PDT 24
Peak memory 202320 kb
Host smart-168c8a5b-3473-4f52-8fc2-75ee626f65c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732145282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.732145282
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.843459694
Short name T38
Test name
Test status
Simulation time 332902509699 ps
CPU time 267.73 seconds
Started May 07 03:26:49 PM PDT 24
Finished May 07 03:31:18 PM PDT 24
Peak memory 212604 kb
Host smart-b6f6bcf6-ccb9-47fd-85e0-3e529fda91a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843459694 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.843459694
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3704522751
Short name T35
Test name
Test status
Simulation time 1277968719404 ps
CPU time 1236.69 seconds
Started May 07 03:26:05 PM PDT 24
Finished May 07 03:46:42 PM PDT 24
Peak memory 210964 kb
Host smart-f5d7203f-02f3-4789-9dae-c61fffb77788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704522751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3704522751
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1294896144
Short name T14
Test name
Test status
Simulation time 106206230852 ps
CPU time 237.1 seconds
Started May 07 03:25:34 PM PDT 24
Finished May 07 03:29:33 PM PDT 24
Peak memory 210976 kb
Host smart-3e71e5b9-42fd-4bbd-8335-9a2dfd42bf65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294896144 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1294896144
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2570740624
Short name T60
Test name
Test status
Simulation time 394885676 ps
CPU time 3.58 seconds
Started May 07 03:21:51 PM PDT 24
Finished May 07 03:21:56 PM PDT 24
Peak memory 217880 kb
Host smart-8a5d0aca-1d3b-4d45-a3a9-58fc0eb03244
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570740624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2570740624
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2350661070
Short name T57
Test name
Test status
Simulation time 4646378321 ps
CPU time 2.61 seconds
Started May 07 03:24:58 PM PDT 24
Finished May 07 03:25:02 PM PDT 24
Peak memory 217816 kb
Host smart-f6e162cc-fa29-493f-a671-5caedcf7f2e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350661070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2350661070
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.4190741644
Short name T216
Test name
Test status
Simulation time 330892290897 ps
CPU time 361.11 seconds
Started May 07 03:25:32 PM PDT 24
Finished May 07 03:31:34 PM PDT 24
Peak memory 202320 kb
Host smart-6c52ea42-0121-4f7c-9f10-885f4c998196
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190741644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.4190741644
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3205952974
Short name T167
Test name
Test status
Simulation time 490387850859 ps
CPU time 1087.65 seconds
Started May 07 03:25:35 PM PDT 24
Finished May 07 03:43:44 PM PDT 24
Peak memory 202336 kb
Host smart-5da4f437-3778-4801-97fd-b782312913a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205952974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3205952974
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2123562852
Short name T176
Test name
Test status
Simulation time 349786422350 ps
CPU time 232 seconds
Started May 07 03:26:22 PM PDT 24
Finished May 07 03:30:15 PM PDT 24
Peak memory 202304 kb
Host smart-61775833-8765-41ff-b1f9-519c0c15d1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123562852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2123562852
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2902684615
Short name T31
Test name
Test status
Simulation time 590469263064 ps
CPU time 1336.03 seconds
Started May 07 03:27:01 PM PDT 24
Finished May 07 03:49:18 PM PDT 24
Peak memory 202420 kb
Host smart-329ac3a7-987f-4318-8e78-550dd9d3aba3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902684615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2902684615
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.33091608
Short name T76
Test name
Test status
Simulation time 484761269181 ps
CPU time 1078.73 seconds
Started May 07 03:26:30 PM PDT 24
Finished May 07 03:44:30 PM PDT 24
Peak memory 202368 kb
Host smart-35dbfef8-7cef-4c0f-a605-bbe3b859c498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33091608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.33091608
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3046415544
Short name T159
Test name
Test status
Simulation time 498166096134 ps
CPU time 313.12 seconds
Started May 07 03:25:10 PM PDT 24
Finished May 07 03:30:24 PM PDT 24
Peak memory 202412 kb
Host smart-f0aed973-026c-40a3-b312-cffebc6207b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046415544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3046415544
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2285927776
Short name T105
Test name
Test status
Simulation time 26293007283 ps
CPU time 88.37 seconds
Started May 07 03:21:51 PM PDT 24
Finished May 07 03:23:20 PM PDT 24
Peak memory 201508 kb
Host smart-3fbf2cee-0c45-4ae9-b403-ade3474ff74d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285927776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2285927776
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3991453209
Short name T1
Test name
Test status
Simulation time 329960575098 ps
CPU time 710.19 seconds
Started May 07 03:27:00 PM PDT 24
Finished May 07 03:38:51 PM PDT 24
Peak memory 202332 kb
Host smart-a28ad179-6602-4f5e-b28e-c6f0e80a16f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991453209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3991453209
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.35278607
Short name T299
Test name
Test status
Simulation time 521427183279 ps
CPU time 326.95 seconds
Started May 07 03:27:11 PM PDT 24
Finished May 07 03:32:38 PM PDT 24
Peak memory 202324 kb
Host smart-ad472c32-f46e-4355-b3cf-06e3b8ee5200
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35278607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_w
akeup.35278607
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1023335236
Short name T152
Test name
Test status
Simulation time 491147595965 ps
CPU time 1208.72 seconds
Started May 07 03:25:18 PM PDT 24
Finished May 07 03:45:28 PM PDT 24
Peak memory 202332 kb
Host smart-194055b5-e241-4f17-89c7-c5786d34bac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023335236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1023335236
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.4104553714
Short name T169
Test name
Test status
Simulation time 531578787041 ps
CPU time 348.32 seconds
Started May 07 03:28:05 PM PDT 24
Finished May 07 03:33:55 PM PDT 24
Peak memory 202336 kb
Host smart-872a5796-4782-4bfa-9224-c2dcccfa1031
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104553714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.4104553714
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2281680251
Short name T242
Test name
Test status
Simulation time 511885801219 ps
CPU time 1051.91 seconds
Started May 07 03:28:16 PM PDT 24
Finished May 07 03:45:48 PM PDT 24
Peak memory 202428 kb
Host smart-e059fb18-49ea-4409-b27c-2125bf9fa77c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281680251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2281680251
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2796320094
Short name T183
Test name
Test status
Simulation time 491898739283 ps
CPU time 194.71 seconds
Started May 07 03:26:31 PM PDT 24
Finished May 07 03:29:46 PM PDT 24
Peak memory 202380 kb
Host smart-a96bd5ea-07b4-446c-8446-8f41568d726c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796320094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2796320094
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3406193083
Short name T170
Test name
Test status
Simulation time 337290659353 ps
CPU time 183.86 seconds
Started May 07 03:26:36 PM PDT 24
Finished May 07 03:29:42 PM PDT 24
Peak memory 202388 kb
Host smart-b4eddc95-43d2-4952-9fca-9e9310e26fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406193083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3406193083
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3207137061
Short name T20
Test name
Test status
Simulation time 144599593272 ps
CPU time 134.98 seconds
Started May 07 03:27:06 PM PDT 24
Finished May 07 03:29:21 PM PDT 24
Peak memory 211052 kb
Host smart-b08cba29-5f2c-4a39-87d1-727f5f053dd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207137061 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3207137061
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.282887846
Short name T307
Test name
Test status
Simulation time 177346584059 ps
CPU time 168.45 seconds
Started May 07 03:25:06 PM PDT 24
Finished May 07 03:27:56 PM PDT 24
Peak memory 210992 kb
Host smart-e2a46987-e2ec-4b49-842c-f3632eb84719
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282887846 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.282887846
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3009228088
Short name T75
Test name
Test status
Simulation time 492009948872 ps
CPU time 131.17 seconds
Started May 07 03:28:10 PM PDT 24
Finished May 07 03:30:22 PM PDT 24
Peak memory 202268 kb
Host smart-457d602b-55e2-4fb0-b0a7-a0ff36bb7ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009228088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3009228088
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2073523617
Short name T68
Test name
Test status
Simulation time 444117953 ps
CPU time 0.76 seconds
Started May 07 03:25:19 PM PDT 24
Finished May 07 03:25:20 PM PDT 24
Peak memory 201828 kb
Host smart-9132aee3-3aa9-4fe2-b17a-e6b3f25c6fbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073523617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2073523617
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.774752270
Short name T298
Test name
Test status
Simulation time 522390773531 ps
CPU time 596.27 seconds
Started May 07 03:27:23 PM PDT 24
Finished May 07 03:37:20 PM PDT 24
Peak memory 202292 kb
Host smart-446702cc-f63d-4e99-a46c-bd26d0f27a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774752270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.774752270
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2334021401
Short name T53
Test name
Test status
Simulation time 8099736454 ps
CPU time 5.94 seconds
Started May 07 03:22:02 PM PDT 24
Finished May 07 03:22:10 PM PDT 24
Peak memory 201508 kb
Host smart-1122fe5a-d23e-446d-af5a-e62da4e21b26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334021401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2334021401
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.326106998
Short name T157
Test name
Test status
Simulation time 363766573014 ps
CPU time 432.56 seconds
Started May 07 03:25:04 PM PDT 24
Finished May 07 03:32:18 PM PDT 24
Peak memory 202404 kb
Host smart-3ef05df2-0042-4ee6-9403-7670f548b848
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326106998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.326106998
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.4183375192
Short name T226
Test name
Test status
Simulation time 356292902717 ps
CPU time 207.34 seconds
Started May 07 03:28:17 PM PDT 24
Finished May 07 03:31:45 PM PDT 24
Peak memory 202340 kb
Host smart-e2b8fb06-d4e8-4599-9253-10aadb40c045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183375192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.4183375192
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.994773070
Short name T109
Test name
Test status
Simulation time 359554862 ps
CPU time 0.97 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:21:56 PM PDT 24
Peak memory 201296 kb
Host smart-4b052cd0-5937-4d4c-8c99-edea8f949be7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994773070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.994773070
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1971572621
Short name T84
Test name
Test status
Simulation time 188122065125 ps
CPU time 238.32 seconds
Started May 07 03:26:44 PM PDT 24
Finished May 07 03:30:44 PM PDT 24
Peak memory 211060 kb
Host smart-a36b82bc-8c40-4d1f-a19c-6121bff53325
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971572621 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1971572621
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3767981835
Short name T238
Test name
Test status
Simulation time 449487599797 ps
CPU time 236.77 seconds
Started May 07 03:26:38 PM PDT 24
Finished May 07 03:30:37 PM PDT 24
Peak memory 202412 kb
Host smart-9ab03fdc-293f-47df-9d51-95fff8aaaf48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767981835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3767981835
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.4079391243
Short name T246
Test name
Test status
Simulation time 1231942059161 ps
CPU time 858.39 seconds
Started May 07 03:28:17 PM PDT 24
Finished May 07 03:42:36 PM PDT 24
Peak memory 213228 kb
Host smart-78171e1c-7bdd-44a3-b1b6-99c4d5607923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079391243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.4079391243
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.772205811
Short name T263
Test name
Test status
Simulation time 162047737763 ps
CPU time 60.9 seconds
Started May 07 03:25:32 PM PDT 24
Finished May 07 03:26:34 PM PDT 24
Peak memory 202376 kb
Host smart-ba3e4898-92a1-4e13-b73c-fba47cf4b337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772205811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.772205811
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3608040557
Short name T182
Test name
Test status
Simulation time 499405818677 ps
CPU time 193.06 seconds
Started May 07 03:25:45 PM PDT 24
Finished May 07 03:28:59 PM PDT 24
Peak memory 202312 kb
Host smart-2993d87b-cc64-4655-9cc5-64c2849dbe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608040557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3608040557
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3398099691
Short name T218
Test name
Test status
Simulation time 338102805412 ps
CPU time 740.76 seconds
Started May 07 03:25:28 PM PDT 24
Finished May 07 03:37:51 PM PDT 24
Peak memory 202292 kb
Host smart-b3521478-7bf5-44c0-843b-618b8c9369ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398099691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3398099691
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3782105298
Short name T102
Test name
Test status
Simulation time 335118362753 ps
CPU time 384.36 seconds
Started May 07 03:27:54 PM PDT 24
Finished May 07 03:34:19 PM PDT 24
Peak memory 202320 kb
Host smart-72f7873d-ec4c-44e0-94ce-e64ed9f20b5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782105298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3782105298
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1590936018
Short name T278
Test name
Test status
Simulation time 164459806823 ps
CPU time 115.34 seconds
Started May 07 03:25:22 PM PDT 24
Finished May 07 03:27:18 PM PDT 24
Peak memory 202500 kb
Host smart-91cd8eda-5c83-4f97-ad2a-25960dfd13bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590936018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1590936018
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.691190065
Short name T309
Test name
Test status
Simulation time 325782999162 ps
CPU time 635.08 seconds
Started May 07 03:25:29 PM PDT 24
Finished May 07 03:36:06 PM PDT 24
Peak memory 202384 kb
Host smart-845dc5be-a393-4347-81d4-da8bad73e453
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691190065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.691190065
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3413990490
Short name T140
Test name
Test status
Simulation time 408499922980 ps
CPU time 464.73 seconds
Started May 07 03:26:54 PM PDT 24
Finished May 07 03:34:40 PM PDT 24
Peak memory 202396 kb
Host smart-aaa72781-4d25-4d2e-a4a3-a7758c75e187
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413990490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3413990490
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2977562642
Short name T202
Test name
Test status
Simulation time 636790787354 ps
CPU time 723.15 seconds
Started May 07 03:25:12 PM PDT 24
Finished May 07 03:37:16 PM PDT 24
Peak memory 210864 kb
Host smart-2844252f-10b9-46f9-9d80-3cdae30cc574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977562642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2977562642
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.4180302490
Short name T94
Test name
Test status
Simulation time 184538333534 ps
CPU time 137.8 seconds
Started May 07 03:25:35 PM PDT 24
Finished May 07 03:27:54 PM PDT 24
Peak memory 211056 kb
Host smart-32da1ad4-4612-4e4e-91fe-bed10c6d62c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180302490 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.4180302490
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2530750088
Short name T227
Test name
Test status
Simulation time 162977674852 ps
CPU time 392.07 seconds
Started May 07 03:25:41 PM PDT 24
Finished May 07 03:32:13 PM PDT 24
Peak memory 202296 kb
Host smart-a375f443-8b08-47c0-a2e8-935126abed6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530750088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2530750088
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.432236523
Short name T211
Test name
Test status
Simulation time 388002125639 ps
CPU time 156.47 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:28:24 PM PDT 24
Peak memory 202296 kb
Host smart-dc695c15-8526-4ace-8cac-a281b6bf2063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432236523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
432236523
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2889193966
Short name T187
Test name
Test status
Simulation time 494450114488 ps
CPU time 313.3 seconds
Started May 07 03:25:42 PM PDT 24
Finished May 07 03:30:56 PM PDT 24
Peak memory 202296 kb
Host smart-3a1db17d-54b8-4711-87ee-d0fb79bb6703
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889193966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2889193966
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.998424099
Short name T212
Test name
Test status
Simulation time 568293472658 ps
CPU time 702.31 seconds
Started May 07 03:26:24 PM PDT 24
Finished May 07 03:38:08 PM PDT 24
Peak memory 202400 kb
Host smart-b8a3de3e-64b3-4177-b0ad-be4614ce2ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998424099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.998424099
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2331571353
Short name T256
Test name
Test status
Simulation time 342184743570 ps
CPU time 748.12 seconds
Started May 07 03:25:09 PM PDT 24
Finished May 07 03:37:39 PM PDT 24
Peak memory 202324 kb
Host smart-22b5f35c-a882-4691-a8ac-82b9eb1af643
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331571353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2331571353
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1768108550
Short name T266
Test name
Test status
Simulation time 168371491204 ps
CPU time 411.99 seconds
Started May 07 03:25:28 PM PDT 24
Finished May 07 03:32:22 PM PDT 24
Peak memory 202328 kb
Host smart-58b52418-e6d6-4206-898d-b261ba10dec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768108550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1768108550
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1338676993
Short name T230
Test name
Test status
Simulation time 386703398054 ps
CPU time 406.77 seconds
Started May 07 03:24:57 PM PDT 24
Finished May 07 03:31:46 PM PDT 24
Peak memory 202308 kb
Host smart-a8a1db27-1f22-473d-87c4-1b413461830b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338676993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1338676993
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1319639562
Short name T215
Test name
Test status
Simulation time 494532130106 ps
CPU time 1120.38 seconds
Started May 07 03:25:35 PM PDT 24
Finished May 07 03:44:17 PM PDT 24
Peak memory 202408 kb
Host smart-76fed29e-2b5e-4a62-ad6d-c5521aa46c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319639562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1319639562
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1490473411
Short name T275
Test name
Test status
Simulation time 63024747200 ps
CPU time 30.01 seconds
Started May 07 03:26:25 PM PDT 24
Finished May 07 03:26:56 PM PDT 24
Peak memory 210704 kb
Host smart-5c519b6c-f65d-4747-9d5f-6219d9793142
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490473411 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1490473411
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3069196984
Short name T288
Test name
Test status
Simulation time 354763284007 ps
CPU time 204.42 seconds
Started May 07 03:26:47 PM PDT 24
Finished May 07 03:30:12 PM PDT 24
Peak memory 202328 kb
Host smart-527333ed-1ee0-4254-a81d-d47ac891ac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069196984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3069196984
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2856415316
Short name T323
Test name
Test status
Simulation time 328758980847 ps
CPU time 800.22 seconds
Started May 07 03:27:07 PM PDT 24
Finished May 07 03:40:28 PM PDT 24
Peak memory 202304 kb
Host smart-484c00ec-7e50-417b-9e8b-b9a6bda25b1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856415316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2856415316
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.448935836
Short name T69
Test name
Test status
Simulation time 598011895 ps
CPU time 3.02 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:21:59 PM PDT 24
Peak memory 201520 kb
Host smart-2647764c-430a-4c4f-a8ed-2a83b6a64070
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448935836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.448935836
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3794348059
Short name T207
Test name
Test status
Simulation time 107103349117 ps
CPU time 378.22 seconds
Started May 07 03:24:50 PM PDT 24
Finished May 07 03:31:10 PM PDT 24
Peak memory 202792 kb
Host smart-848ddad2-1c14-48d6-9b35-39c952bbcfec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794348059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3794348059
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2280758936
Short name T22
Test name
Test status
Simulation time 66103538630 ps
CPU time 37.34 seconds
Started May 07 03:25:14 PM PDT 24
Finished May 07 03:25:52 PM PDT 24
Peak memory 202612 kb
Host smart-09845f98-1c24-4268-a01e-5e6334188e41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280758936 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2280758936
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.4272725890
Short name T204
Test name
Test status
Simulation time 272019056350 ps
CPU time 414.16 seconds
Started May 07 03:25:30 PM PDT 24
Finished May 07 03:32:26 PM PDT 24
Peak memory 202740 kb
Host smart-4ee32b9a-0ad1-4a2a-9df4-b417271e645a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272725890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.4272725890
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1887373937
Short name T258
Test name
Test status
Simulation time 329163128883 ps
CPU time 681.42 seconds
Started May 07 03:26:23 PM PDT 24
Finished May 07 03:37:46 PM PDT 24
Peak memory 202380 kb
Host smart-8e936973-af5a-4f7b-8c2a-4d592d676d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887373937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1887373937
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.4221134437
Short name T21
Test name
Test status
Simulation time 66089536922 ps
CPU time 79.17 seconds
Started May 07 03:27:03 PM PDT 24
Finished May 07 03:28:23 PM PDT 24
Peak memory 210692 kb
Host smart-2008c6f1-3ca0-43b8-8ad1-28a9f4f93f48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221134437 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.4221134437
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1164345666
Short name T95
Test name
Test status
Simulation time 579196508746 ps
CPU time 566.44 seconds
Started May 07 03:27:16 PM PDT 24
Finished May 07 03:36:43 PM PDT 24
Peak memory 202344 kb
Host smart-c911527b-c8ac-4f54-b540-f15be9f3140c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164345666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1164345666
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.429346453
Short name T284
Test name
Test status
Simulation time 320922852110 ps
CPU time 676.64 seconds
Started May 07 03:27:43 PM PDT 24
Finished May 07 03:39:01 PM PDT 24
Peak memory 202412 kb
Host smart-7aeedc12-da1b-4ea4-b01c-748479beb92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429346453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.429346453
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2702246867
Short name T254
Test name
Test status
Simulation time 287742443686 ps
CPU time 179.74 seconds
Started May 07 03:28:25 PM PDT 24
Finished May 07 03:31:25 PM PDT 24
Peak memory 210628 kb
Host smart-aa2a2b4e-2eff-4d53-a6e8-3c8be7134748
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702246867 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2702246867
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2696346480
Short name T326
Test name
Test status
Simulation time 4574879798 ps
CPU time 3.84 seconds
Started May 07 03:21:51 PM PDT 24
Finished May 07 03:21:55 PM PDT 24
Peak memory 201504 kb
Host smart-8b475ef7-28d0-4f1c-a23d-f55dc00b97ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696346480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2696346480
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1565751644
Short name T252
Test name
Test status
Simulation time 548383313741 ps
CPU time 655.63 seconds
Started May 07 03:25:25 PM PDT 24
Finished May 07 03:36:22 PM PDT 24
Peak memory 202424 kb
Host smart-914365e5-9837-41f1-8b21-89e668b83e10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565751644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1565751644
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.321540966
Short name T296
Test name
Test status
Simulation time 525221552599 ps
CPU time 642.12 seconds
Started May 07 03:25:31 PM PDT 24
Finished May 07 03:36:14 PM PDT 24
Peak memory 202340 kb
Host smart-324f252a-9aaf-4d77-9e1a-9840d85fed82
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321540966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.321540966
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2701601346
Short name T268
Test name
Test status
Simulation time 327136924073 ps
CPU time 215.79 seconds
Started May 07 03:25:04 PM PDT 24
Finished May 07 03:28:41 PM PDT 24
Peak memory 202320 kb
Host smart-977c96f6-e923-4d0b-a1b1-4d707192994b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701601346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2701601346
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.4108374936
Short name T34
Test name
Test status
Simulation time 344927345470 ps
CPU time 542 seconds
Started May 07 03:25:07 PM PDT 24
Finished May 07 03:34:10 PM PDT 24
Peak memory 210916 kb
Host smart-861a48a4-a653-4e1f-b0c7-bed1281667ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108374936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
4108374936
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2408883727
Short name T301
Test name
Test status
Simulation time 322829314906 ps
CPU time 181.34 seconds
Started May 07 03:27:06 PM PDT 24
Finished May 07 03:30:08 PM PDT 24
Peak memory 202360 kb
Host smart-3db40678-4a9f-469a-ac5c-52407f5f0d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408883727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2408883727
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3538392379
Short name T331
Test name
Test status
Simulation time 137678655820 ps
CPU time 658.07 seconds
Started May 07 03:28:06 PM PDT 24
Finished May 07 03:39:06 PM PDT 24
Peak memory 202684 kb
Host smart-d9610f06-97fc-4627-95e8-fca47c2ed45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538392379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3538392379
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.522267460
Short name T265
Test name
Test status
Simulation time 483669429698 ps
CPU time 1044.5 seconds
Started May 07 03:25:08 PM PDT 24
Finished May 07 03:42:34 PM PDT 24
Peak memory 202304 kb
Host smart-22585f22-22d1-48ac-90fb-d479989f6f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522267460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.522267460
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.61586026
Short name T142
Test name
Test status
Simulation time 328998688384 ps
CPU time 510.58 seconds
Started May 07 03:25:13 PM PDT 24
Finished May 07 03:33:45 PM PDT 24
Peak memory 202396 kb
Host smart-06a04435-6806-470e-8e95-9d4bb177682b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61586026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.61586026
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2918295059
Short name T335
Test name
Test status
Simulation time 262387565563 ps
CPU time 450.5 seconds
Started May 07 03:25:18 PM PDT 24
Finished May 07 03:32:50 PM PDT 24
Peak memory 210952 kb
Host smart-25c91ba3-0af6-47af-83d6-1c5ec67160be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918295059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2918295059
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3827637769
Short name T45
Test name
Test status
Simulation time 123458939435 ps
CPU time 454.61 seconds
Started May 07 03:25:26 PM PDT 24
Finished May 07 03:33:03 PM PDT 24
Peak memory 202764 kb
Host smart-4aca29c3-f709-4e0c-99b5-5938b2adb80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827637769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3827637769
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.896940465
Short name T158
Test name
Test status
Simulation time 527630375708 ps
CPU time 638.13 seconds
Started May 07 03:25:29 PM PDT 24
Finished May 07 03:36:10 PM PDT 24
Peak memory 202336 kb
Host smart-5e4a966f-f498-4a00-8ff7-3f785ca453bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896940465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.896940465
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1067608002
Short name T292
Test name
Test status
Simulation time 269609287093 ps
CPU time 168.01 seconds
Started May 07 03:25:50 PM PDT 24
Finished May 07 03:28:39 PM PDT 24
Peak memory 202260 kb
Host smart-d42760c5-df93-4eab-9032-451e1f11db8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067608002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1067608002
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3642772644
Short name T317
Test name
Test status
Simulation time 644801975186 ps
CPU time 1619.12 seconds
Started May 07 03:26:06 PM PDT 24
Finished May 07 03:53:06 PM PDT 24
Peak memory 202432 kb
Host smart-403f90ca-3ade-4a8c-bbd0-5d30e4b7cad6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642772644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3642772644
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.686502451
Short name T297
Test name
Test status
Simulation time 332696798429 ps
CPU time 202.86 seconds
Started May 07 03:25:05 PM PDT 24
Finished May 07 03:28:29 PM PDT 24
Peak memory 202284 kb
Host smart-ac03110b-8b94-4cbd-acea-ed67272ef3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686502451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.686502451
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.119615176
Short name T262
Test name
Test status
Simulation time 523942960955 ps
CPU time 578.93 seconds
Started May 07 03:26:26 PM PDT 24
Finished May 07 03:36:06 PM PDT 24
Peak memory 202300 kb
Host smart-bebe04c4-7179-43e2-ac19-09534a1778dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119615176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.119615176
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.665036379
Short name T267
Test name
Test status
Simulation time 167613475904 ps
CPU time 403.36 seconds
Started May 07 03:26:58 PM PDT 24
Finished May 07 03:33:42 PM PDT 24
Peak memory 202244 kb
Host smart-0e6cef84-a1ce-4e74-8a0b-0a679ba37567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665036379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.665036379
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2171389324
Short name T181
Test name
Test status
Simulation time 511894975630 ps
CPU time 730.62 seconds
Started May 07 03:28:02 PM PDT 24
Finished May 07 03:40:13 PM PDT 24
Peak memory 211012 kb
Host smart-d9401864-b4f6-46d9-90f8-1c2f78e0ff64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171389324 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2171389324
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2155329905
Short name T98
Test name
Test status
Simulation time 122791675351 ps
CPU time 479.28 seconds
Started May 07 03:25:10 PM PDT 24
Finished May 07 03:33:11 PM PDT 24
Peak memory 202756 kb
Host smart-f9c90eff-6c4c-41e9-8bc8-e405e4d31a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155329905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2155329905
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2008559501
Short name T334
Test name
Test status
Simulation time 107161899549 ps
CPU time 537.77 seconds
Started May 07 03:25:16 PM PDT 24
Finished May 07 03:34:15 PM PDT 24
Peak memory 202680 kb
Host smart-7d9af571-97ff-4a2f-b33e-cf02693bb20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008559501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2008559501
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3671587472
Short name T110
Test name
Test status
Simulation time 1203410269 ps
CPU time 3.02 seconds
Started May 07 03:21:49 PM PDT 24
Finished May 07 03:21:53 PM PDT 24
Peak memory 201432 kb
Host smart-d4d7fbeb-a629-4f55-8f41-66d07d93e920
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671587472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3671587472
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1593093508
Short name T129
Test name
Test status
Simulation time 26658140731 ps
CPU time 19.54 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:22:15 PM PDT 24
Peak memory 201552 kb
Host smart-0ea30051-213c-4965-97a2-4debb7933be1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593093508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1593093508
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1816154565
Short name T903
Test name
Test status
Simulation time 1072829677 ps
CPU time 1.36 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:21:56 PM PDT 24
Peak memory 201260 kb
Host smart-beecc993-8f28-44ae-aa89-e85175f26268
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816154565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1816154565
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2730308784
Short name T896
Test name
Test status
Simulation time 437094348 ps
CPU time 1.03 seconds
Started May 07 03:21:46 PM PDT 24
Finished May 07 03:21:49 PM PDT 24
Peak memory 201308 kb
Host smart-048ab062-2a73-40af-b136-36c636b3d4a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730308784 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2730308784
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1033862023
Short name T808
Test name
Test status
Simulation time 375796356 ps
CPU time 1.45 seconds
Started May 07 03:21:49 PM PDT 24
Finished May 07 03:21:52 PM PDT 24
Peak memory 201256 kb
Host smart-b4f535eb-f0bb-45c3-949f-27b6bfa803fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033862023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1033862023
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2701689164
Short name T122
Test name
Test status
Simulation time 2699247110 ps
CPU time 3.62 seconds
Started May 07 03:21:50 PM PDT 24
Finished May 07 03:21:54 PM PDT 24
Peak memory 201280 kb
Host smart-8278a698-9210-4ecf-9e47-8f7f28dcaf44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701689164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2701689164
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2277700218
Short name T907
Test name
Test status
Simulation time 8936011135 ps
CPU time 7.78 seconds
Started May 07 03:21:56 PM PDT 24
Finished May 07 03:22:06 PM PDT 24
Peak memory 201516 kb
Host smart-6a2320fd-2df9-4490-a7a4-aee73358ba09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277700218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2277700218
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2289716145
Short name T106
Test name
Test status
Simulation time 1371756437 ps
CPU time 2.81 seconds
Started May 07 03:21:52 PM PDT 24
Finished May 07 03:21:56 PM PDT 24
Peak memory 201456 kb
Host smart-41a10baf-93a7-4b17-8c45-0d6e67a14e81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289716145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2289716145
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1390537588
Short name T842
Test name
Test status
Simulation time 1466959632 ps
CPU time 1.04 seconds
Started May 07 03:21:49 PM PDT 24
Finished May 07 03:21:51 PM PDT 24
Peak memory 201324 kb
Host smart-5e388a7a-5fd9-4384-b3ec-993dc6ce428c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390537588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1390537588
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2044140223
Short name T905
Test name
Test status
Simulation time 403861653 ps
CPU time 1.42 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:21:57 PM PDT 24
Peak memory 201352 kb
Host smart-17278492-7748-4ef9-aa7c-ae8c04612693
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044140223 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2044140223
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2855759968
Short name T841
Test name
Test status
Simulation time 433852663 ps
CPU time 1.13 seconds
Started May 07 03:21:52 PM PDT 24
Finished May 07 03:21:55 PM PDT 24
Peak memory 201240 kb
Host smart-ec8a4ccb-76be-4d32-82c5-60ba6addb14d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855759968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2855759968
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3243479686
Short name T839
Test name
Test status
Simulation time 482824511 ps
CPU time 1.21 seconds
Started May 07 03:21:51 PM PDT 24
Finished May 07 03:21:53 PM PDT 24
Peak memory 201248 kb
Host smart-b08af7fd-6014-4923-a915-cd9a89a89022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243479686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3243479686
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.128649063
Short name T126
Test name
Test status
Simulation time 3607047142 ps
CPU time 5.89 seconds
Started May 07 03:21:48 PM PDT 24
Finished May 07 03:21:55 PM PDT 24
Peak memory 201464 kb
Host smart-edb86ac0-b268-4dae-8b4e-3554c2ab7520
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128649063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.128649063
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3264357315
Short name T83
Test name
Test status
Simulation time 464322319 ps
CPU time 1.92 seconds
Started May 07 03:22:09 PM PDT 24
Finished May 07 03:22:13 PM PDT 24
Peak memory 200728 kb
Host smart-3f06a6ed-261c-49be-8327-80b6525758d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264357315 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3264357315
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3817095007
Short name T117
Test name
Test status
Simulation time 500853204 ps
CPU time 1.17 seconds
Started May 07 03:21:58 PM PDT 24
Finished May 07 03:22:01 PM PDT 24
Peak memory 201220 kb
Host smart-6918e180-b4d3-4d97-897e-a2c7abfcc77f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817095007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3817095007
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.802608583
Short name T814
Test name
Test status
Simulation time 354975981 ps
CPU time 0.88 seconds
Started May 07 03:21:58 PM PDT 24
Finished May 07 03:22:02 PM PDT 24
Peak memory 201220 kb
Host smart-bc4f2847-ebbe-4e7f-9762-2cf0b75eb346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802608583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.802608583
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3925034746
Short name T854
Test name
Test status
Simulation time 4596962106 ps
CPU time 3.64 seconds
Started May 07 03:21:57 PM PDT 24
Finished May 07 03:22:03 PM PDT 24
Peak memory 201560 kb
Host smart-5c5521a5-5605-4136-b743-4116faa38b88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925034746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3925034746
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3914871374
Short name T860
Test name
Test status
Simulation time 812962270 ps
CPU time 2.39 seconds
Started May 07 03:22:03 PM PDT 24
Finished May 07 03:22:08 PM PDT 24
Peak memory 209692 kb
Host smart-0a1f5a05-91b0-4b29-b6cb-0b90dcca0dbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914871374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3914871374
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.830848414
Short name T325
Test name
Test status
Simulation time 8182136651 ps
CPU time 13.1 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:21 PM PDT 24
Peak memory 201496 kb
Host smart-43ef1166-7a23-4969-ac94-ecca6baa8393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830848414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.830848414
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2378298853
Short name T858
Test name
Test status
Simulation time 378610718 ps
CPU time 1.69 seconds
Started May 07 03:21:57 PM PDT 24
Finished May 07 03:22:01 PM PDT 24
Peak memory 201292 kb
Host smart-e1146fc1-738e-492b-bd26-31d72d4a51e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378298853 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2378298853
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4249322966
Short name T113
Test name
Test status
Simulation time 505212047 ps
CPU time 2.04 seconds
Started May 07 03:22:06 PM PDT 24
Finished May 07 03:22:11 PM PDT 24
Peak memory 201184 kb
Host smart-f4a0c60d-1613-4dd1-9635-b5936839e394
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249322966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.4249322966
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3659397318
Short name T830
Test name
Test status
Simulation time 368931797 ps
CPU time 1.03 seconds
Started May 07 03:21:58 PM PDT 24
Finished May 07 03:22:01 PM PDT 24
Peak memory 201220 kb
Host smart-34ae16d1-2db4-438e-80c5-eb44e3e77fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659397318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3659397318
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3151329389
Short name T850
Test name
Test status
Simulation time 3770085073 ps
CPU time 12.94 seconds
Started May 07 03:22:00 PM PDT 24
Finished May 07 03:22:15 PM PDT 24
Peak memory 201508 kb
Host smart-521fe9ce-d8c6-4e4c-8125-48c4891b002b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151329389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3151329389
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2308069841
Short name T867
Test name
Test status
Simulation time 689068382 ps
CPU time 2.71 seconds
Started May 07 03:22:00 PM PDT 24
Finished May 07 03:22:05 PM PDT 24
Peak memory 201500 kb
Host smart-fce02689-1e1b-4281-8a30-6a1f613d60ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308069841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2308069841
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4134397436
Short name T882
Test name
Test status
Simulation time 4460024369 ps
CPU time 3.43 seconds
Started May 07 03:22:01 PM PDT 24
Finished May 07 03:22:06 PM PDT 24
Peak memory 201560 kb
Host smart-fd1a5184-5d4d-4906-baa1-b88d48eb785f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134397436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.4134397436
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2319827522
Short name T822
Test name
Test status
Simulation time 562121338 ps
CPU time 1.41 seconds
Started May 07 03:21:58 PM PDT 24
Finished May 07 03:22:01 PM PDT 24
Peak memory 201256 kb
Host smart-35a64b70-66e4-46b8-aab1-d0f7316c8b2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319827522 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2319827522
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1138552133
Short name T840
Test name
Test status
Simulation time 403231224 ps
CPU time 1.16 seconds
Started May 07 03:22:01 PM PDT 24
Finished May 07 03:22:04 PM PDT 24
Peak memory 201212 kb
Host smart-ba2dd9e1-4085-4e75-ab29-35404b65ee0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138552133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1138552133
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3811541552
Short name T825
Test name
Test status
Simulation time 474695497 ps
CPU time 0.88 seconds
Started May 07 03:22:00 PM PDT 24
Finished May 07 03:22:03 PM PDT 24
Peak memory 201264 kb
Host smart-26d32378-9518-4cd1-aa62-6c82db30965e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811541552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3811541552
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3157808180
Short name T124
Test name
Test status
Simulation time 2383083846 ps
CPU time 9.69 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:17 PM PDT 24
Peak memory 201196 kb
Host smart-26230518-bb74-458a-a36c-f05a7923694c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157808180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3157808180
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3015245099
Short name T821
Test name
Test status
Simulation time 622813309 ps
CPU time 3.58 seconds
Started May 07 03:22:01 PM PDT 24
Finished May 07 03:22:07 PM PDT 24
Peak memory 217612 kb
Host smart-2f2d308e-de52-4d77-96b9-6cd86d56e831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015245099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3015245099
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1967533382
Short name T914
Test name
Test status
Simulation time 4940832352 ps
CPU time 2.94 seconds
Started May 07 03:22:03 PM PDT 24
Finished May 07 03:22:08 PM PDT 24
Peak memory 201572 kb
Host smart-1b54c653-248d-4c2a-8993-c561f3d3a5cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967533382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1967533382
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.893056001
Short name T887
Test name
Test status
Simulation time 398364604 ps
CPU time 1.91 seconds
Started May 07 03:22:09 PM PDT 24
Finished May 07 03:22:13 PM PDT 24
Peak memory 201292 kb
Host smart-30cac8de-9b82-4f98-aa74-ac1c67372aff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893056001 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.893056001
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1336571141
Short name T115
Test name
Test status
Simulation time 513675839 ps
CPU time 0.99 seconds
Started May 07 03:22:09 PM PDT 24
Finished May 07 03:22:12 PM PDT 24
Peak memory 200696 kb
Host smart-cb979a3e-a272-44dd-ad9f-75542a065a99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336571141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1336571141
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3915366259
Short name T895
Test name
Test status
Simulation time 411504514 ps
CPU time 1.53 seconds
Started May 07 03:22:03 PM PDT 24
Finished May 07 03:22:07 PM PDT 24
Peak memory 201248 kb
Host smart-c645987f-12d6-40ef-b069-fddded402d0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915366259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3915366259
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3818623510
Short name T49
Test name
Test status
Simulation time 5189880753 ps
CPU time 6.93 seconds
Started May 07 03:22:01 PM PDT 24
Finished May 07 03:22:10 PM PDT 24
Peak memory 201496 kb
Host smart-6e3f3c72-bbeb-4291-ba16-30adffc1f5d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818623510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3818623510
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2909028245
Short name T910
Test name
Test status
Simulation time 908381170 ps
CPU time 2.95 seconds
Started May 07 03:22:04 PM PDT 24
Finished May 07 03:22:09 PM PDT 24
Peak memory 201496 kb
Host smart-5443a161-7faa-4b6a-bb59-d310c02ea544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909028245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2909028245
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.954502731
Short name T852
Test name
Test status
Simulation time 4343795374 ps
CPU time 11.46 seconds
Started May 07 03:22:03 PM PDT 24
Finished May 07 03:22:16 PM PDT 24
Peak memory 201496 kb
Host smart-70915544-fb4a-4322-9134-64bac760da07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954502731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.954502731
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1773311610
Short name T820
Test name
Test status
Simulation time 641271187 ps
CPU time 1.3 seconds
Started May 07 03:22:03 PM PDT 24
Finished May 07 03:22:06 PM PDT 24
Peak memory 201292 kb
Host smart-92fa6468-8fbe-44bc-b13a-17e6a27fc3ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773311610 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1773311610
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.368859113
Short name T127
Test name
Test status
Simulation time 579137999 ps
CPU time 1.08 seconds
Started May 07 03:22:00 PM PDT 24
Finished May 07 03:22:03 PM PDT 24
Peak memory 201240 kb
Host smart-31f82240-f63a-4981-ba13-5f845fa4a72a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368859113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.368859113
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3776072042
Short name T859
Test name
Test status
Simulation time 359539092 ps
CPU time 0.96 seconds
Started May 07 03:22:00 PM PDT 24
Finished May 07 03:22:03 PM PDT 24
Peak memory 201196 kb
Host smart-cc8e8c7c-cc78-4736-9a2b-d86c916e30d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776072042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3776072042
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1598439913
Short name T834
Test name
Test status
Simulation time 4763705090 ps
CPU time 5.21 seconds
Started May 07 03:21:59 PM PDT 24
Finished May 07 03:22:06 PM PDT 24
Peak memory 201508 kb
Host smart-18003127-bc9b-4525-aa65-c5076425c4f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598439913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1598439913
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.354222285
Short name T884
Test name
Test status
Simulation time 607109192 ps
CPU time 2.37 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:10 PM PDT 24
Peak memory 209572 kb
Host smart-639b1199-29f1-4801-a3c0-f7fa910de392
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354222285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.354222285
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1631762656
Short name T54
Test name
Test status
Simulation time 9366453925 ps
CPU time 5.06 seconds
Started May 07 03:21:57 PM PDT 24
Finished May 07 03:22:04 PM PDT 24
Peak memory 201468 kb
Host smart-d12ddce5-8baa-47fa-964e-eaac6288c29e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631762656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1631762656
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2097475438
Short name T875
Test name
Test status
Simulation time 705891276 ps
CPU time 1.29 seconds
Started May 07 03:22:09 PM PDT 24
Finished May 07 03:22:12 PM PDT 24
Peak memory 201276 kb
Host smart-1c8a7384-7198-437d-ae8c-91e90f8f62d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097475438 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2097475438
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3254581557
Short name T125
Test name
Test status
Simulation time 462528513 ps
CPU time 1.07 seconds
Started May 07 03:22:00 PM PDT 24
Finished May 07 03:22:03 PM PDT 24
Peak memory 201232 kb
Host smart-b643a4c2-849b-48ad-a776-1840c5769393
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254581557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3254581557
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3406692870
Short name T917
Test name
Test status
Simulation time 369533433 ps
CPU time 0.87 seconds
Started May 07 03:22:01 PM PDT 24
Finished May 07 03:22:03 PM PDT 24
Peak memory 201244 kb
Host smart-d6203577-483d-445f-832d-38255bd994f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406692870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3406692870
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3442182850
Short name T851
Test name
Test status
Simulation time 4628274224 ps
CPU time 2.38 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:10 PM PDT 24
Peak memory 201572 kb
Host smart-a9afa9d3-1e9e-407c-af0f-aac7eb3f9d25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442182850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3442182850
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1348140876
Short name T832
Test name
Test status
Simulation time 519473376 ps
CPU time 1.65 seconds
Started May 07 03:22:02 PM PDT 24
Finished May 07 03:22:06 PM PDT 24
Peak memory 201528 kb
Host smart-b2c286cf-5344-4927-948b-b059e768dd79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348140876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1348140876
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.852253369
Short name T71
Test name
Test status
Simulation time 4268814051 ps
CPU time 12.45 seconds
Started May 07 03:22:06 PM PDT 24
Finished May 07 03:22:21 PM PDT 24
Peak memory 201500 kb
Host smart-dba38d15-2c07-4f32-9f6a-07e76c9b5dc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852253369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.852253369
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2511750040
Short name T878
Test name
Test status
Simulation time 418702826 ps
CPU time 1.02 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:08 PM PDT 24
Peak memory 201308 kb
Host smart-ec0526a1-a792-4e6e-9fce-2979a7f1212d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511750040 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2511750040
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1418442260
Short name T901
Test name
Test status
Simulation time 559106976 ps
CPU time 1.14 seconds
Started May 07 03:22:13 PM PDT 24
Finished May 07 03:22:15 PM PDT 24
Peak memory 201392 kb
Host smart-e957ad27-9c0f-4838-9606-2459222bc3e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418442260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1418442260
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3260408320
Short name T833
Test name
Test status
Simulation time 418470996 ps
CPU time 0.69 seconds
Started May 07 03:22:04 PM PDT 24
Finished May 07 03:22:07 PM PDT 24
Peak memory 201224 kb
Host smart-a7f78cf3-90a9-41b5-aa6c-1695f2262460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260408320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3260408320
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2898256352
Short name T869
Test name
Test status
Simulation time 4283292785 ps
CPU time 2.49 seconds
Started May 07 03:22:13 PM PDT 24
Finished May 07 03:22:16 PM PDT 24
Peak memory 201648 kb
Host smart-c3020f00-a177-49c6-b325-f21c4289ab53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898256352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2898256352
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.530940716
Short name T59
Test name
Test status
Simulation time 527565158 ps
CPU time 2.92 seconds
Started May 07 03:22:08 PM PDT 24
Finished May 07 03:22:14 PM PDT 24
Peak memory 201500 kb
Host smart-3a377355-6345-43d5-8d52-3119e611ded9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530940716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.530940716
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2006091778
Short name T327
Test name
Test status
Simulation time 8577666989 ps
CPU time 5.69 seconds
Started May 07 03:21:59 PM PDT 24
Finished May 07 03:22:07 PM PDT 24
Peak memory 201516 kb
Host smart-422adf9a-d19d-43c0-bbe5-38b8d0bae338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006091778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2006091778
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.952386498
Short name T61
Test name
Test status
Simulation time 598642015 ps
CPU time 2.27 seconds
Started May 07 03:22:07 PM PDT 24
Finished May 07 03:22:11 PM PDT 24
Peak memory 201312 kb
Host smart-abbe1150-9527-46f9-a913-db40a4f3caf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952386498 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.952386498
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1911080374
Short name T120
Test name
Test status
Simulation time 466254572 ps
CPU time 0.97 seconds
Started May 07 03:22:13 PM PDT 24
Finished May 07 03:22:15 PM PDT 24
Peak memory 201360 kb
Host smart-278c9f58-2956-48a5-8e52-97991b12599f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911080374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1911080374
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1558275183
Short name T837
Test name
Test status
Simulation time 344139383 ps
CPU time 0.86 seconds
Started May 07 03:22:04 PM PDT 24
Finished May 07 03:22:07 PM PDT 24
Peak memory 201224 kb
Host smart-224af515-b345-49c6-b0f9-c45c623a5b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558275183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1558275183
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1861723276
Short name T919
Test name
Test status
Simulation time 4860857031 ps
CPU time 12.47 seconds
Started May 07 03:22:04 PM PDT 24
Finished May 07 03:22:19 PM PDT 24
Peak memory 201432 kb
Host smart-c6efccad-b2fc-4e0e-b42d-fefd6c62d847
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861723276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1861723276
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3623683672
Short name T870
Test name
Test status
Simulation time 417375935 ps
CPU time 1.87 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:09 PM PDT 24
Peak memory 217848 kb
Host smart-ffeefd94-ba0f-4b9b-ba8e-f0d1d6807b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623683672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3623683672
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2086119438
Short name T55
Test name
Test status
Simulation time 3899763314 ps
CPU time 4.15 seconds
Started May 07 03:22:03 PM PDT 24
Finished May 07 03:22:10 PM PDT 24
Peak memory 201472 kb
Host smart-75170394-7054-4d24-8993-6c832c483614
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086119438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2086119438
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4059680443
Short name T861
Test name
Test status
Simulation time 520076397 ps
CPU time 1.52 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:09 PM PDT 24
Peak memory 201288 kb
Host smart-292b0476-5b5c-4716-b5d0-16d3c4881bd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059680443 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.4059680443
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.277901203
Short name T116
Test name
Test status
Simulation time 552111158 ps
CPU time 1.18 seconds
Started May 07 03:22:06 PM PDT 24
Finished May 07 03:22:09 PM PDT 24
Peak memory 201264 kb
Host smart-cfde7895-dc71-4d1c-accf-c8817e24f5a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277901203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.277901203
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.81228917
Short name T863
Test name
Test status
Simulation time 454067090 ps
CPU time 1.51 seconds
Started May 07 03:22:08 PM PDT 24
Finished May 07 03:22:12 PM PDT 24
Peak memory 201212 kb
Host smart-dd9129fd-da38-405e-94d6-5e1fba2f2dd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81228917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.81228917
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2036759428
Short name T123
Test name
Test status
Simulation time 2040556422 ps
CPU time 7.91 seconds
Started May 07 03:22:06 PM PDT 24
Finished May 07 03:22:16 PM PDT 24
Peak memory 201248 kb
Host smart-311317be-9236-4df4-baf2-a036dbb4de0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036759428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2036759428
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1318444643
Short name T856
Test name
Test status
Simulation time 458571356 ps
CPU time 2.21 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:09 PM PDT 24
Peak memory 201548 kb
Host smart-c13623b0-9cd9-4842-bdc8-142dc5828bba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318444643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1318444643
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3741509334
Short name T828
Test name
Test status
Simulation time 8536944173 ps
CPU time 21.82 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:29 PM PDT 24
Peak memory 201520 kb
Host smart-9b0cd3c9-eb1b-42c0-b63f-555d0471b2ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741509334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3741509334
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.521985670
Short name T886
Test name
Test status
Simulation time 401267342 ps
CPU time 1.73 seconds
Started May 07 03:22:13 PM PDT 24
Finished May 07 03:22:16 PM PDT 24
Peak memory 201468 kb
Host smart-9831448c-bd5b-4353-93e1-12410d4e0864
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521985670 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.521985670
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2257249170
Short name T899
Test name
Test status
Simulation time 365936546 ps
CPU time 1.46 seconds
Started May 07 03:22:03 PM PDT 24
Finished May 07 03:22:07 PM PDT 24
Peak memory 201240 kb
Host smart-a2a6ec36-132e-4b40-8cef-442cada8d4d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257249170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2257249170
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.921400118
Short name T818
Test name
Test status
Simulation time 521761530 ps
CPU time 0.97 seconds
Started May 07 03:22:02 PM PDT 24
Finished May 07 03:22:05 PM PDT 24
Peak memory 201252 kb
Host smart-7ecedb2a-95fa-4262-aed1-36033669869c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921400118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.921400118
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2152816939
Short name T912
Test name
Test status
Simulation time 2672752315 ps
CPU time 7.1 seconds
Started May 07 03:22:08 PM PDT 24
Finished May 07 03:22:17 PM PDT 24
Peak memory 201316 kb
Host smart-49a02038-9af3-4a74-8550-302449932843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152816939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2152816939
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1115543735
Short name T890
Test name
Test status
Simulation time 569322276 ps
CPU time 3.58 seconds
Started May 07 03:22:06 PM PDT 24
Finished May 07 03:22:12 PM PDT 24
Peak memory 217308 kb
Host smart-7386ed29-f945-4901-92e3-ff317959a5a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115543735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1115543735
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2602995715
Short name T324
Test name
Test status
Simulation time 7972014490 ps
CPU time 6.66 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:14 PM PDT 24
Peak memory 201544 kb
Host smart-a8aa5f37-e086-4626-9a4b-d0c2f0b278d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602995715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2602995715
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.686006375
Short name T108
Test name
Test status
Simulation time 943549579 ps
CPU time 1.98 seconds
Started May 07 03:21:55 PM PDT 24
Finished May 07 03:21:59 PM PDT 24
Peak memory 201428 kb
Host smart-3d77bcaa-b03c-46ee-88c8-c3df6ebadc29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686006375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.686006375
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3914605321
Short name T121
Test name
Test status
Simulation time 12488191492 ps
CPU time 22.54 seconds
Started May 07 03:21:57 PM PDT 24
Finished May 07 03:22:21 PM PDT 24
Peak memory 201472 kb
Host smart-a2d515c2-b2c0-42b0-8cac-be7bf826eb36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914605321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3914605321
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1647781703
Short name T118
Test name
Test status
Simulation time 1328262329 ps
CPU time 1.58 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:21:57 PM PDT 24
Peak memory 201296 kb
Host smart-ea5ad6af-d88a-4411-b2e1-9bb53644eba5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647781703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1647781703
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4172690014
Short name T831
Test name
Test status
Simulation time 449208452 ps
CPU time 1.07 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:21:57 PM PDT 24
Peak memory 201296 kb
Host smart-29a7535e-8be3-4a96-96b9-4b2fc68b0c1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172690014 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.4172690014
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.797879673
Short name T104
Test name
Test status
Simulation time 569704706 ps
CPU time 1.33 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:21:56 PM PDT 24
Peak memory 201264 kb
Host smart-6c67c5a6-3688-42fb-ad44-4d9f63e661a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797879673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.797879673
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1649150007
Short name T916
Test name
Test status
Simulation time 292115544 ps
CPU time 1.38 seconds
Started May 07 03:21:51 PM PDT 24
Finished May 07 03:21:54 PM PDT 24
Peak memory 201260 kb
Host smart-ae2cff9a-ff7b-4e12-b5a3-f90a0b6c6b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649150007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1649150007
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3847353179
Short name T51
Test name
Test status
Simulation time 4241957366 ps
CPU time 18.47 seconds
Started May 07 03:22:00 PM PDT 24
Finished May 07 03:22:20 PM PDT 24
Peak memory 201500 kb
Host smart-2eac10e6-6490-4b0a-ba6f-6ca7c2a723d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847353179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3847353179
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2589706257
Short name T881
Test name
Test status
Simulation time 664622147 ps
CPU time 3.11 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:21:59 PM PDT 24
Peak memory 217368 kb
Host smart-2832261f-b69f-4c0f-b6ad-8f7f85fbf57d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589706257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2589706257
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3285948766
Short name T70
Test name
Test status
Simulation time 9127155094 ps
CPU time 7.12 seconds
Started May 07 03:21:55 PM PDT 24
Finished May 07 03:22:05 PM PDT 24
Peak memory 201512 kb
Host smart-00eec055-0567-4f94-8486-9cfacb4786ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285948766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3285948766
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2531577919
Short name T872
Test name
Test status
Simulation time 426423336 ps
CPU time 1.61 seconds
Started May 07 03:22:06 PM PDT 24
Finished May 07 03:22:10 PM PDT 24
Peak memory 201248 kb
Host smart-d10006d3-7d37-4f42-9f78-cc66b6c4feb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531577919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2531577919
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2820437554
Short name T817
Test name
Test status
Simulation time 334490076 ps
CPU time 1.05 seconds
Started May 07 03:22:06 PM PDT 24
Finished May 07 03:22:09 PM PDT 24
Peak memory 201252 kb
Host smart-a4400266-1826-4318-8b8d-f79200cfcae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820437554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2820437554
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2047567514
Short name T811
Test name
Test status
Simulation time 320480490 ps
CPU time 1.36 seconds
Started May 07 03:22:06 PM PDT 24
Finished May 07 03:22:10 PM PDT 24
Peak memory 201248 kb
Host smart-6a3793b7-10d3-42c6-8e55-971dfdf6387a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047567514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2047567514
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3919151172
Short name T815
Test name
Test status
Simulation time 509414924 ps
CPU time 1.86 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:09 PM PDT 24
Peak memory 201236 kb
Host smart-a23c7e73-ad5c-43ac-8d3e-07a77c4badb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919151172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3919151172
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1359251394
Short name T810
Test name
Test status
Simulation time 489120819 ps
CPU time 0.92 seconds
Started May 07 03:22:03 PM PDT 24
Finished May 07 03:22:07 PM PDT 24
Peak memory 201236 kb
Host smart-00b7dea9-e38c-4693-9a4f-bd3fe1e4631b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359251394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1359251394
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2369059210
Short name T804
Test name
Test status
Simulation time 371618884 ps
CPU time 1.51 seconds
Started May 07 03:22:01 PM PDT 24
Finished May 07 03:22:05 PM PDT 24
Peak memory 201220 kb
Host smart-c43ace32-ed76-49b6-88d7-6c40c3223bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369059210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2369059210
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.768950466
Short name T806
Test name
Test status
Simulation time 464680706 ps
CPU time 1.65 seconds
Started May 07 03:22:08 PM PDT 24
Finished May 07 03:22:11 PM PDT 24
Peak memory 201244 kb
Host smart-7ad35521-3299-4d30-a042-658be11b1157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768950466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.768950466
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3878437899
Short name T829
Test name
Test status
Simulation time 319208126 ps
CPU time 0.78 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:08 PM PDT 24
Peak memory 201180 kb
Host smart-16d30f3e-a0bf-416d-b370-f17b691b8229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878437899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3878437899
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3247843290
Short name T906
Test name
Test status
Simulation time 408107581 ps
CPU time 1.58 seconds
Started May 07 03:22:08 PM PDT 24
Finished May 07 03:22:12 PM PDT 24
Peak memory 201236 kb
Host smart-f2706089-4b7e-4477-acd5-c515ad913c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247843290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3247843290
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4148409283
Short name T826
Test name
Test status
Simulation time 494385448 ps
CPU time 1.18 seconds
Started May 07 03:22:13 PM PDT 24
Finished May 07 03:22:15 PM PDT 24
Peak memory 201392 kb
Host smart-aa8af9f2-4344-422c-a6a4-9ac4c39becde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148409283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4148409283
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2100154466
Short name T819
Test name
Test status
Simulation time 820478635 ps
CPU time 1.95 seconds
Started May 07 03:21:59 PM PDT 24
Finished May 07 03:22:04 PM PDT 24
Peak memory 201412 kb
Host smart-8ba14f13-8736-478c-a89d-9fac5c2c4505
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100154466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2100154466
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3651414430
Short name T909
Test name
Test status
Simulation time 26736922437 ps
CPU time 30.96 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:22:26 PM PDT 24
Peak memory 201424 kb
Host smart-283e32be-1b97-4f9f-9b47-072302df2344
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651414430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3651414430
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1538881854
Short name T119
Test name
Test status
Simulation time 1117997854 ps
CPU time 2.13 seconds
Started May 07 03:21:51 PM PDT 24
Finished May 07 03:21:55 PM PDT 24
Peak memory 201244 kb
Host smart-a6f95ec8-6035-47ac-994b-cf1e8dc59baf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538881854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1538881854
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.596592996
Short name T864
Test name
Test status
Simulation time 662575152 ps
CPU time 1.19 seconds
Started May 07 03:21:57 PM PDT 24
Finished May 07 03:22:00 PM PDT 24
Peak memory 201276 kb
Host smart-53a98d47-7339-43fd-9c6c-d421641616f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596592996 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.596592996
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3174830817
Short name T835
Test name
Test status
Simulation time 427379160 ps
CPU time 1.74 seconds
Started May 07 03:21:54 PM PDT 24
Finished May 07 03:21:58 PM PDT 24
Peak memory 201252 kb
Host smart-325dcb65-5978-4182-90c8-52da1b7fb69e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174830817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3174830817
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1446704675
Short name T908
Test name
Test status
Simulation time 531951074 ps
CPU time 1.8 seconds
Started May 07 03:22:00 PM PDT 24
Finished May 07 03:22:04 PM PDT 24
Peak memory 201172 kb
Host smart-4f75599e-4907-445b-9c59-36e23533b5d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446704675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1446704675
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3362156985
Short name T50
Test name
Test status
Simulation time 2936663199 ps
CPU time 3.28 seconds
Started May 07 03:21:55 PM PDT 24
Finished May 07 03:22:00 PM PDT 24
Peak memory 201316 kb
Host smart-2415a383-765f-4c22-99da-e1523322375a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362156985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3362156985
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3291287186
Short name T877
Test name
Test status
Simulation time 870895376 ps
CPU time 2.55 seconds
Started May 07 03:21:54 PM PDT 24
Finished May 07 03:21:59 PM PDT 24
Peak memory 201516 kb
Host smart-151886c9-81b6-42b4-ab63-b4eeb0e784ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291287186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3291287186
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.283433933
Short name T52
Test name
Test status
Simulation time 4355778599 ps
CPU time 12.09 seconds
Started May 07 03:21:52 PM PDT 24
Finished May 07 03:22:06 PM PDT 24
Peak memory 201524 kb
Host smart-56d027f2-ddb4-4942-9e3e-fc1a6c0824a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283433933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.283433933
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.274031663
Short name T889
Test name
Test status
Simulation time 464265979 ps
CPU time 1.77 seconds
Started May 07 03:22:07 PM PDT 24
Finished May 07 03:22:11 PM PDT 24
Peak memory 201212 kb
Host smart-10f161ee-1798-4793-92c5-b083ddc8e6f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274031663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.274031663
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3266248563
Short name T883
Test name
Test status
Simulation time 501600112 ps
CPU time 0.85 seconds
Started May 07 03:22:04 PM PDT 24
Finished May 07 03:22:07 PM PDT 24
Peak memory 201240 kb
Host smart-cb9b26d3-3a83-458a-a830-fd2561fddaa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266248563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3266248563
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.783140541
Short name T876
Test name
Test status
Simulation time 335515045 ps
CPU time 1.1 seconds
Started May 07 03:22:02 PM PDT 24
Finished May 07 03:22:06 PM PDT 24
Peak memory 201232 kb
Host smart-af210d0a-dd89-4741-9625-302d82dc5c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783140541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.783140541
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1065146404
Short name T885
Test name
Test status
Simulation time 510064227 ps
CPU time 1.81 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:09 PM PDT 24
Peak memory 201248 kb
Host smart-c74a96d5-c14b-4971-8cc3-b74ebd5ffb7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065146404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1065146404
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2455873251
Short name T809
Test name
Test status
Simulation time 482429378 ps
CPU time 0.82 seconds
Started May 07 03:22:06 PM PDT 24
Finished May 07 03:22:09 PM PDT 24
Peak memory 201192 kb
Host smart-997af7e7-c322-4a66-9a33-a172607f605f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455873251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2455873251
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2784457176
Short name T900
Test name
Test status
Simulation time 324240378 ps
CPU time 0.83 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:08 PM PDT 24
Peak memory 201248 kb
Host smart-f9423da1-7d12-4214-9bed-771ecc3c641b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784457176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2784457176
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1069184760
Short name T892
Test name
Test status
Simulation time 465805655 ps
CPU time 1.68 seconds
Started May 07 03:22:08 PM PDT 24
Finished May 07 03:22:12 PM PDT 24
Peak memory 201224 kb
Host smart-0770121a-05ac-4f4a-9cd2-0096d3b332a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069184760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1069184760
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.479743492
Short name T874
Test name
Test status
Simulation time 372234474 ps
CPU time 0.86 seconds
Started May 07 03:22:06 PM PDT 24
Finished May 07 03:22:09 PM PDT 24
Peak memory 201240 kb
Host smart-12787349-a213-4061-8e11-055f633a2eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479743492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.479743492
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1030534733
Short name T897
Test name
Test status
Simulation time 404095969 ps
CPU time 1.07 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:08 PM PDT 24
Peak memory 201240 kb
Host smart-d23c1324-1fd0-477b-b807-097844ef1a49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030534733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1030534733
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3804612483
Short name T812
Test name
Test status
Simulation time 329546357 ps
CPU time 0.92 seconds
Started May 07 03:22:06 PM PDT 24
Finished May 07 03:22:10 PM PDT 24
Peak memory 201252 kb
Host smart-91ffe5e5-6771-4dd0-b06f-40aaea786789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804612483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3804612483
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3923187397
Short name T845
Test name
Test status
Simulation time 933815818 ps
CPU time 3.01 seconds
Started May 07 03:21:58 PM PDT 24
Finished May 07 03:22:02 PM PDT 24
Peak memory 201496 kb
Host smart-a9e81db0-ecca-4804-a2c4-b80d92bb2fd7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923187397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3923187397
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4240907107
Short name T128
Test name
Test status
Simulation time 53320421297 ps
CPU time 46.33 seconds
Started May 07 03:21:54 PM PDT 24
Finished May 07 03:22:42 PM PDT 24
Peak memory 201528 kb
Host smart-4130f55f-a701-49c3-b680-a32821a0d72b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240907107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.4240907107
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.873003671
Short name T880
Test name
Test status
Simulation time 1226600357 ps
CPU time 1.38 seconds
Started May 07 03:21:55 PM PDT 24
Finished May 07 03:21:59 PM PDT 24
Peak memory 201232 kb
Host smart-86c222fc-d5c6-41e3-9a7f-531fe48cc18a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873003671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.873003671
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2296402874
Short name T904
Test name
Test status
Simulation time 428880183 ps
CPU time 1.89 seconds
Started May 07 03:21:54 PM PDT 24
Finished May 07 03:21:59 PM PDT 24
Peak memory 201304 kb
Host smart-8f52f022-4d7d-42fd-9025-ffca4f3bb57e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296402874 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2296402874
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2087312990
Short name T114
Test name
Test status
Simulation time 419751154 ps
CPU time 1.89 seconds
Started May 07 03:21:54 PM PDT 24
Finished May 07 03:21:58 PM PDT 24
Peak memory 201236 kb
Host smart-44ca5a41-76a9-4dcc-9f08-1864ea2122e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087312990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2087312990
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2518134738
Short name T843
Test name
Test status
Simulation time 406421803 ps
CPU time 1.06 seconds
Started May 07 03:22:02 PM PDT 24
Finished May 07 03:22:05 PM PDT 24
Peak memory 201252 kb
Host smart-15f5ad90-0ef4-4108-aa86-fcbb81fc3e28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518134738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2518134738
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3454820418
Short name T862
Test name
Test status
Simulation time 4210331367 ps
CPU time 5.14 seconds
Started May 07 03:21:59 PM PDT 24
Finished May 07 03:22:07 PM PDT 24
Peak memory 201520 kb
Host smart-dbcbfc69-6f84-4f16-9b02-0f11a3c4aaa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454820418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3454820418
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2761673641
Short name T65
Test name
Test status
Simulation time 457604517 ps
CPU time 2.08 seconds
Started May 07 03:22:02 PM PDT 24
Finished May 07 03:22:06 PM PDT 24
Peak memory 201528 kb
Host smart-4a35eb66-fed3-4de3-968f-a37a83442504
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761673641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2761673641
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3455522946
Short name T857
Test name
Test status
Simulation time 4772494382 ps
CPU time 2.75 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:21:58 PM PDT 24
Peak memory 201484 kb
Host smart-30604b27-7039-483c-8453-3d1db1990e38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455522946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3455522946
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1576636203
Short name T911
Test name
Test status
Simulation time 351086833 ps
CPU time 0.86 seconds
Started May 07 03:22:08 PM PDT 24
Finished May 07 03:22:11 PM PDT 24
Peak memory 200864 kb
Host smart-27cf0f89-82c5-479e-9b75-d189cedf61a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576636203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1576636203
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.41581971
Short name T807
Test name
Test status
Simulation time 443961475 ps
CPU time 1.64 seconds
Started May 07 03:22:08 PM PDT 24
Finished May 07 03:22:11 PM PDT 24
Peak memory 201224 kb
Host smart-40d0797c-8b67-467a-905f-8d943c8a8d1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41581971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.41581971
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1521930708
Short name T813
Test name
Test status
Simulation time 373391227 ps
CPU time 1.37 seconds
Started May 07 03:22:06 PM PDT 24
Finished May 07 03:22:10 PM PDT 24
Peak memory 201256 kb
Host smart-c39d7d9b-01e9-4f31-8caa-c3d2126b6694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521930708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1521930708
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.257518331
Short name T848
Test name
Test status
Simulation time 337107247 ps
CPU time 1.13 seconds
Started May 07 03:22:09 PM PDT 24
Finished May 07 03:22:12 PM PDT 24
Peak memory 200864 kb
Host smart-ed7ec00b-a545-4a7e-9b54-7c1006334140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257518331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.257518331
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2573534753
Short name T865
Test name
Test status
Simulation time 391524250 ps
CPU time 0.84 seconds
Started May 07 03:22:08 PM PDT 24
Finished May 07 03:22:10 PM PDT 24
Peak memory 201248 kb
Host smart-e4e77a0a-ae5e-43a1-bb7f-5003c4f86f67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573534753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2573534753
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2576954687
Short name T847
Test name
Test status
Simulation time 347925255 ps
CPU time 0.88 seconds
Started May 07 03:22:08 PM PDT 24
Finished May 07 03:22:11 PM PDT 24
Peak memory 201244 kb
Host smart-f412b082-809e-4a8e-b4e9-d4c886b34d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576954687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2576954687
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3639662022
Short name T805
Test name
Test status
Simulation time 490360027 ps
CPU time 0.98 seconds
Started May 07 03:22:08 PM PDT 24
Finished May 07 03:22:12 PM PDT 24
Peak memory 201240 kb
Host smart-121b2233-2659-4077-8c48-c4bf60a09582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639662022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3639662022
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1164504056
Short name T879
Test name
Test status
Simulation time 333121410 ps
CPU time 1.4 seconds
Started May 07 03:22:09 PM PDT 24
Finished May 07 03:22:13 PM PDT 24
Peak memory 201268 kb
Host smart-62a12a7b-5b57-4a2c-a09f-1680d5523e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164504056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1164504056
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2354849240
Short name T846
Test name
Test status
Simulation time 553232135 ps
CPU time 0.98 seconds
Started May 07 03:22:14 PM PDT 24
Finished May 07 03:22:16 PM PDT 24
Peak memory 201204 kb
Host smart-2ebde0af-3d28-487f-b0e0-3e57f68daca3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354849240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2354849240
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.256526343
Short name T873
Test name
Test status
Simulation time 418188734 ps
CPU time 1.2 seconds
Started May 07 03:22:10 PM PDT 24
Finished May 07 03:22:13 PM PDT 24
Peak memory 201232 kb
Host smart-4f4396a0-3edc-4abe-901d-757265601198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256526343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.256526343
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.7148239
Short name T894
Test name
Test status
Simulation time 666270834 ps
CPU time 1.17 seconds
Started May 07 03:21:52 PM PDT 24
Finished May 07 03:21:54 PM PDT 24
Peak memory 201288 kb
Host smart-2563cfee-247e-44cb-af10-443eec19797b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7148239 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.7148239
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.585377686
Short name T918
Test name
Test status
Simulation time 301504895 ps
CPU time 1.22 seconds
Started May 07 03:21:56 PM PDT 24
Finished May 07 03:21:59 PM PDT 24
Peak memory 201236 kb
Host smart-9d447597-b9c4-43d1-8399-de1b3982dc2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585377686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.585377686
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1220251211
Short name T866
Test name
Test status
Simulation time 439509904 ps
CPU time 1.61 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:21:58 PM PDT 24
Peak memory 201220 kb
Host smart-a421c7b2-5dce-4a38-93ac-c069af40b761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220251211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1220251211
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4229006793
Short name T836
Test name
Test status
Simulation time 2459956398 ps
CPU time 6.91 seconds
Started May 07 03:21:51 PM PDT 24
Finished May 07 03:21:59 PM PDT 24
Peak memory 201288 kb
Host smart-74e3294d-b133-43bf-83bf-bf66db0daa63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229006793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.4229006793
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.868366661
Short name T63
Test name
Test status
Simulation time 426088488 ps
CPU time 3.83 seconds
Started May 07 03:21:55 PM PDT 24
Finished May 07 03:22:01 PM PDT 24
Peak memory 210724 kb
Host smart-8e36c477-3bb0-46e2-b4a2-16ab5a64c7a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868366661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.868366661
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2029115273
Short name T823
Test name
Test status
Simulation time 4385941156 ps
CPU time 12.56 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:22:08 PM PDT 24
Peak memory 201424 kb
Host smart-ff0df899-5a34-4d7c-923d-30285d63b9bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029115273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2029115273
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.217719960
Short name T913
Test name
Test status
Simulation time 811280881 ps
CPU time 1.15 seconds
Started May 07 03:22:03 PM PDT 24
Finished May 07 03:22:06 PM PDT 24
Peak memory 201280 kb
Host smart-2c8e585a-d9bb-490f-9d58-3241bd98f182
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217719960 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.217719960
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3562539607
Short name T107
Test name
Test status
Simulation time 453030315 ps
CPU time 1.23 seconds
Started May 07 03:21:59 PM PDT 24
Finished May 07 03:22:03 PM PDT 24
Peak memory 201248 kb
Host smart-56596c05-8bc0-47f5-9086-e89959d8ba47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562539607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3562539607
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3866266407
Short name T888
Test name
Test status
Simulation time 514588900 ps
CPU time 0.97 seconds
Started May 07 03:22:00 PM PDT 24
Finished May 07 03:22:03 PM PDT 24
Peak memory 201232 kb
Host smart-c2964f32-80a0-436c-bfab-432d4cfb945b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866266407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3866266407
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2893092100
Short name T853
Test name
Test status
Simulation time 4856538745 ps
CPU time 4.06 seconds
Started May 07 03:22:04 PM PDT 24
Finished May 07 03:22:10 PM PDT 24
Peak memory 201572 kb
Host smart-eb91f68f-4be6-4bbb-927c-a51e7e62884e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893092100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2893092100
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3464198874
Short name T902
Test name
Test status
Simulation time 1144133163 ps
CPU time 2.73 seconds
Started May 07 03:21:55 PM PDT 24
Finished May 07 03:22:00 PM PDT 24
Peak memory 201608 kb
Host smart-2f2385e9-ae00-40d0-b9f7-103f844c7f46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464198874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3464198874
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4291636987
Short name T816
Test name
Test status
Simulation time 8632623424 ps
CPU time 7.63 seconds
Started May 07 03:21:52 PM PDT 24
Finished May 07 03:22:01 PM PDT 24
Peak memory 201532 kb
Host smart-cc8488da-3d1e-4da8-b2f4-7b1d47e1f876
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291636987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.4291636987
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2532313485
Short name T898
Test name
Test status
Simulation time 328994751 ps
CPU time 1.56 seconds
Started May 07 03:22:07 PM PDT 24
Finished May 07 03:22:10 PM PDT 24
Peak memory 201288 kb
Host smart-f76d02a7-286e-469f-bbbd-49a0deaa011f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532313485 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2532313485
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1658911751
Short name T891
Test name
Test status
Simulation time 505864225 ps
CPU time 2.1 seconds
Started May 07 03:22:01 PM PDT 24
Finished May 07 03:22:05 PM PDT 24
Peak memory 201260 kb
Host smart-f40dbd97-4fc4-4258-a62b-5a6d24a86fa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658911751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1658911751
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1619712965
Short name T827
Test name
Test status
Simulation time 480329755 ps
CPU time 0.94 seconds
Started May 07 03:21:59 PM PDT 24
Finished May 07 03:22:03 PM PDT 24
Peak memory 201252 kb
Host smart-fae9d3d2-0828-44ae-aa39-f875f35e67b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619712965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1619712965
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1231333469
Short name T838
Test name
Test status
Simulation time 5740098667 ps
CPU time 7.8 seconds
Started May 07 03:22:03 PM PDT 24
Finished May 07 03:22:13 PM PDT 24
Peak memory 201484 kb
Host smart-31ff4bf7-8c2b-4087-9738-5b81abaf9469
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231333469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1231333469
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.625088272
Short name T64
Test name
Test status
Simulation time 527170282 ps
CPU time 2.77 seconds
Started May 07 03:22:00 PM PDT 24
Finished May 07 03:22:05 PM PDT 24
Peak memory 217936 kb
Host smart-91d3fb45-e1b5-4361-b8c3-eb7fe51f5024
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625088272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.625088272
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.610935925
Short name T824
Test name
Test status
Simulation time 681382180 ps
CPU time 1.45 seconds
Started May 07 03:21:57 PM PDT 24
Finished May 07 03:22:01 PM PDT 24
Peak memory 201268 kb
Host smart-96aa8190-2a88-4cd8-8f30-127c04bf2aa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610935925 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.610935925
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2721358425
Short name T112
Test name
Test status
Simulation time 480555173 ps
CPU time 0.82 seconds
Started May 07 03:22:10 PM PDT 24
Finished May 07 03:22:12 PM PDT 24
Peak memory 201244 kb
Host smart-69f2d298-e514-4ac1-8e7c-58f64aedab92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721358425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2721358425
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3586433937
Short name T855
Test name
Test status
Simulation time 499550702 ps
CPU time 0.94 seconds
Started May 07 03:21:59 PM PDT 24
Finished May 07 03:22:02 PM PDT 24
Peak memory 201272 kb
Host smart-27c3ffcb-a9b1-41fb-9666-c963736afc68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586433937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3586433937
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.496846721
Short name T893
Test name
Test status
Simulation time 2894371452 ps
CPU time 2.86 seconds
Started May 07 03:22:03 PM PDT 24
Finished May 07 03:22:07 PM PDT 24
Peak memory 201296 kb
Host smart-4f61bc08-0199-4b55-b71c-8f3c26babe30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496846721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.496846721
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2722265115
Short name T871
Test name
Test status
Simulation time 580107764 ps
CPU time 1.57 seconds
Started May 07 03:21:58 PM PDT 24
Finished May 07 03:22:01 PM PDT 24
Peak memory 201480 kb
Host smart-4f57d1bb-2965-4e80-86cd-a607d14b8f59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722265115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2722265115
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1754648066
Short name T62
Test name
Test status
Simulation time 3994748013 ps
CPU time 10.28 seconds
Started May 07 03:21:58 PM PDT 24
Finished May 07 03:22:10 PM PDT 24
Peak memory 201504 kb
Host smart-936070f3-2e33-4df1-8dbf-e369a6e7b520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754648066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1754648066
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2330985516
Short name T844
Test name
Test status
Simulation time 733486670 ps
CPU time 1.03 seconds
Started May 07 03:22:02 PM PDT 24
Finished May 07 03:22:05 PM PDT 24
Peak memory 201296 kb
Host smart-26faac95-6e0a-42a4-af98-cac7477b013c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330985516 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2330985516
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2347513671
Short name T111
Test name
Test status
Simulation time 333476805 ps
CPU time 1.46 seconds
Started May 07 03:22:01 PM PDT 24
Finished May 07 03:22:05 PM PDT 24
Peak memory 201276 kb
Host smart-119a196e-269b-44a6-ad1e-64fb22e3049a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347513671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2347513671
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.326362060
Short name T915
Test name
Test status
Simulation time 453520823 ps
CPU time 0.94 seconds
Started May 07 03:22:05 PM PDT 24
Finished May 07 03:22:08 PM PDT 24
Peak memory 201176 kb
Host smart-932bbb7f-d7a6-4499-a003-dd5f269d9481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326362060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.326362060
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.716697431
Short name T849
Test name
Test status
Simulation time 2543834622 ps
CPU time 2.37 seconds
Started May 07 03:22:00 PM PDT 24
Finished May 07 03:22:05 PM PDT 24
Peak memory 201316 kb
Host smart-ac06ba67-b2fb-4381-9ef8-2d9fa19709a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716697431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.716697431
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1877144077
Short name T868
Test name
Test status
Simulation time 844205824 ps
CPU time 1.8 seconds
Started May 07 03:22:03 PM PDT 24
Finished May 07 03:22:07 PM PDT 24
Peak memory 201564 kb
Host smart-f9cc7190-83d5-4924-88ca-309d63e6f4ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877144077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1877144077
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.58565824
Short name T328
Test name
Test status
Simulation time 9735194952 ps
CPU time 4.74 seconds
Started May 07 03:22:00 PM PDT 24
Finished May 07 03:22:07 PM PDT 24
Peak memory 201564 kb
Host smart-4ce4b752-1052-44ed-bdf5-b28b259dc7a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58565824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg
_err.58565824
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1371536558
Short name T504
Test name
Test status
Simulation time 535009808 ps
CPU time 1.32 seconds
Started May 07 03:24:56 PM PDT 24
Finished May 07 03:24:59 PM PDT 24
Peak memory 202012 kb
Host smart-8abf2e03-8dc3-49ac-a3fc-027ed41b4341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371536558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1371536558
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.625093761
Short name T221
Test name
Test status
Simulation time 347707226234 ps
CPU time 198.36 seconds
Started May 07 03:24:54 PM PDT 24
Finished May 07 03:28:14 PM PDT 24
Peak memory 202304 kb
Host smart-7359b6df-ef6c-47e7-bad2-e426aefca5b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625093761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.625093761
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3079835331
Short name T507
Test name
Test status
Simulation time 164591779423 ps
CPU time 403.88 seconds
Started May 07 03:24:53 PM PDT 24
Finished May 07 03:31:39 PM PDT 24
Peak memory 202432 kb
Host smart-2fd6b8a0-dd76-4f30-805a-85f2e346ce46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079835331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3079835331
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3666411801
Short name T28
Test name
Test status
Simulation time 166865151242 ps
CPU time 415.73 seconds
Started May 07 03:24:51 PM PDT 24
Finished May 07 03:31:48 PM PDT 24
Peak memory 202352 kb
Host smart-38ed7cac-e44f-40d4-92a4-54176cd12994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666411801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3666411801
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.4243559425
Short name T352
Test name
Test status
Simulation time 323940235988 ps
CPU time 641.11 seconds
Started May 07 03:24:56 PM PDT 24
Finished May 07 03:35:39 PM PDT 24
Peak memory 202284 kb
Host smart-65d4ba68-e946-474a-b1cf-9fb1f9599cb0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243559425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.4243559425
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1761456657
Short name T175
Test name
Test status
Simulation time 330688773871 ps
CPU time 405.53 seconds
Started May 07 03:24:58 PM PDT 24
Finished May 07 03:31:45 PM PDT 24
Peak memory 202500 kb
Host smart-b1e9bed6-0d88-49ea-9a4a-37f591cd6b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761456657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1761456657
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3071458582
Short name T438
Test name
Test status
Simulation time 327219590377 ps
CPU time 198.99 seconds
Started May 07 03:24:52 PM PDT 24
Finished May 07 03:28:12 PM PDT 24
Peak memory 202320 kb
Host smart-714eb545-4d7a-4e99-9beb-3cc8d180383d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071458582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3071458582
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1889670922
Short name T232
Test name
Test status
Simulation time 184189571898 ps
CPU time 99.13 seconds
Started May 07 03:24:54 PM PDT 24
Finished May 07 03:26:35 PM PDT 24
Peak memory 202344 kb
Host smart-636e6248-d5a0-49ee-afdc-7061e74712f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889670922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1889670922
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.451286462
Short name T499
Test name
Test status
Simulation time 396681377176 ps
CPU time 840.81 seconds
Started May 07 03:24:53 PM PDT 24
Finished May 07 03:38:56 PM PDT 24
Peak memory 202336 kb
Host smart-a0a7d970-0eab-4fec-ab12-47f108db996d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451286462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.451286462
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.142158525
Short name T462
Test name
Test status
Simulation time 96034169750 ps
CPU time 395.15 seconds
Started May 07 03:24:54 PM PDT 24
Finished May 07 03:31:30 PM PDT 24
Peak memory 202784 kb
Host smart-2d8619e7-d188-49b9-a0fa-0c5c2b8fb94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142158525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.142158525
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1099698857
Short name T766
Test name
Test status
Simulation time 42408580755 ps
CPU time 21.62 seconds
Started May 07 03:24:54 PM PDT 24
Finished May 07 03:25:17 PM PDT 24
Peak memory 202152 kb
Host smart-2cf3adf8-ad12-49f6-b271-32bc225a93a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099698857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1099698857
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3972650164
Short name T606
Test name
Test status
Simulation time 3811955148 ps
CPU time 4.56 seconds
Started May 07 03:24:55 PM PDT 24
Finished May 07 03:25:01 PM PDT 24
Peak memory 202164 kb
Host smart-acb7b185-5203-4d34-8a02-f465adc64ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972650164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3972650164
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1888626650
Short name T58
Test name
Test status
Simulation time 3715639734 ps
CPU time 5.68 seconds
Started May 07 03:24:51 PM PDT 24
Finished May 07 03:24:58 PM PDT 24
Peak memory 217784 kb
Host smart-7bf42aca-919a-48ab-b246-50757a250240
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888626650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1888626650
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.4128656952
Short name T708
Test name
Test status
Simulation time 5728467253 ps
CPU time 2.78 seconds
Started May 07 03:24:54 PM PDT 24
Finished May 07 03:24:58 PM PDT 24
Peak memory 202132 kb
Host smart-edd7de4c-d633-4e5a-b4f8-0a52a898dd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128656952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.4128656952
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1114580558
Short name T39
Test name
Test status
Simulation time 1886557126061 ps
CPU time 706.26 seconds
Started May 07 03:24:56 PM PDT 24
Finished May 07 03:36:44 PM PDT 24
Peak memory 210624 kb
Host smart-36136f32-f39c-4e16-b6ff-b3e05b5320ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114580558 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1114580558
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2939910167
Short name T626
Test name
Test status
Simulation time 338636485 ps
CPU time 1.33 seconds
Started May 07 03:24:56 PM PDT 24
Finished May 07 03:24:59 PM PDT 24
Peak memory 202012 kb
Host smart-3ec29c63-dd8a-4a0f-b629-83fff78bc33f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939910167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2939910167
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.83803954
Short name T306
Test name
Test status
Simulation time 335531226742 ps
CPU time 86.4 seconds
Started May 07 03:24:55 PM PDT 24
Finished May 07 03:26:23 PM PDT 24
Peak memory 202324 kb
Host smart-efbbdd24-7d25-48e9-b90f-b6ae342703b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83803954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating
.83803954
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.648468470
Short name T769
Test name
Test status
Simulation time 529111909944 ps
CPU time 1350.49 seconds
Started May 07 03:24:57 PM PDT 24
Finished May 07 03:47:30 PM PDT 24
Peak memory 202488 kb
Host smart-1bd56289-9574-4d81-a89e-ce5c70bd9203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648468470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.648468470
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2927989197
Short name T787
Test name
Test status
Simulation time 163065814094 ps
CPU time 186.19 seconds
Started May 07 03:24:52 PM PDT 24
Finished May 07 03:28:00 PM PDT 24
Peak memory 202320 kb
Host smart-7f2ffe88-50c1-44bd-b20e-35d2898cac06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927989197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2927989197
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.728985330
Short name T501
Test name
Test status
Simulation time 325969527839 ps
CPU time 107.54 seconds
Started May 07 03:24:57 PM PDT 24
Finished May 07 03:26:46 PM PDT 24
Peak memory 202332 kb
Host smart-ff1733df-bd0d-4c5d-9301-b922ded2d9ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=728985330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.728985330
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.4128202157
Short name T217
Test name
Test status
Simulation time 325642760579 ps
CPU time 738.63 seconds
Started May 07 03:24:50 PM PDT 24
Finished May 07 03:37:10 PM PDT 24
Peak memory 201788 kb
Host smart-763be6d5-5922-48d2-9ebf-5d423e685e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128202157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.4128202157
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3407033981
Short name T550
Test name
Test status
Simulation time 479644116156 ps
CPU time 544.4 seconds
Started May 07 03:24:51 PM PDT 24
Finished May 07 03:33:57 PM PDT 24
Peak memory 202388 kb
Host smart-d9744550-8d83-49ef-bb49-4df61246990c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407033981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3407033981
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3549689026
Short name T721
Test name
Test status
Simulation time 168041626034 ps
CPU time 318.47 seconds
Started May 07 03:24:58 PM PDT 24
Finished May 07 03:30:18 PM PDT 24
Peak memory 202408 kb
Host smart-8cb93e22-df5e-4c41-ac38-88d9460b523c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549689026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3549689026
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3515303644
Short name T201
Test name
Test status
Simulation time 95059046649 ps
CPU time 476.08 seconds
Started May 07 03:25:04 PM PDT 24
Finished May 07 03:33:01 PM PDT 24
Peak memory 202632 kb
Host smart-aaabf681-7e9f-44c9-98df-46cb2851b921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515303644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3515303644
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2498031816
Short name T420
Test name
Test status
Simulation time 33831643630 ps
CPU time 36.49 seconds
Started May 07 03:24:56 PM PDT 24
Finished May 07 03:25:34 PM PDT 24
Peak memory 202140 kb
Host smart-e87e92dd-5f69-416c-90fc-fbe23701cc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498031816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2498031816
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.751514262
Short name T85
Test name
Test status
Simulation time 3862899703 ps
CPU time 5.24 seconds
Started May 07 03:25:07 PM PDT 24
Finished May 07 03:25:14 PM PDT 24
Peak memory 202076 kb
Host smart-e54cbe27-f8b4-4d50-b22e-4a5702b266c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751514262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.751514262
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2386148186
Short name T433
Test name
Test status
Simulation time 5983044272 ps
CPU time 9.73 seconds
Started May 07 03:24:53 PM PDT 24
Finished May 07 03:25:04 PM PDT 24
Peak memory 202160 kb
Host smart-522a03b8-efa2-4a8c-9c8a-024e09fee92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386148186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2386148186
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1630510563
Short name T208
Test name
Test status
Simulation time 264674848855 ps
CPU time 594.2 seconds
Started May 07 03:24:55 PM PDT 24
Finished May 07 03:34:51 PM PDT 24
Peak memory 202688 kb
Host smart-6650bffc-7c05-480d-9daa-f2bdb3dcc34b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630510563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1630510563
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.108814281
Short name T546
Test name
Test status
Simulation time 71858730138 ps
CPU time 153.17 seconds
Started May 07 03:24:57 PM PDT 24
Finished May 07 03:27:32 PM PDT 24
Peak memory 213456 kb
Host smart-bf1ca82d-1cf6-4d1c-bb83-8df1c52adf05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108814281 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.108814281
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3280907110
Short name T228
Test name
Test status
Simulation time 359473361532 ps
CPU time 740.46 seconds
Started May 07 03:25:16 PM PDT 24
Finished May 07 03:37:37 PM PDT 24
Peak memory 202344 kb
Host smart-3fe0daf0-6f15-41d4-9f93-000d493cfae1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280907110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3280907110
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1931456985
Short name T289
Test name
Test status
Simulation time 498071713685 ps
CPU time 521.29 seconds
Started May 07 03:25:13 PM PDT 24
Finished May 07 03:33:56 PM PDT 24
Peak memory 202284 kb
Host smart-6a4623ca-7c53-4425-b51e-c7936162c5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931456985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1931456985
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4144209370
Short name T803
Test name
Test status
Simulation time 162272750295 ps
CPU time 376.75 seconds
Started May 07 03:25:20 PM PDT 24
Finished May 07 03:31:38 PM PDT 24
Peak memory 202332 kb
Host smart-00606958-8e55-4ed2-ad94-5015a9c844b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144209370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.4144209370
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.167174122
Short name T791
Test name
Test status
Simulation time 328172615644 ps
CPU time 187.52 seconds
Started May 07 03:25:14 PM PDT 24
Finished May 07 03:28:23 PM PDT 24
Peak memory 202308 kb
Host smart-0daf980d-c290-4df9-9aaa-79b058037826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167174122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.167174122
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.56994324
Short name T676
Test name
Test status
Simulation time 323907343963 ps
CPU time 763.43 seconds
Started May 07 03:25:16 PM PDT 24
Finished May 07 03:38:00 PM PDT 24
Peak memory 202400 kb
Host smart-f9b3e55d-7443-433f-8155-302e142fc922
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=56994324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed
.56994324
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1175862034
Short name T718
Test name
Test status
Simulation time 183479324809 ps
CPU time 109.4 seconds
Started May 07 03:25:16 PM PDT 24
Finished May 07 03:27:07 PM PDT 24
Peak memory 202348 kb
Host smart-627cef12-88ab-4744-a402-0e5011c05c6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175862034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1175862034
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2345926827
Short name T663
Test name
Test status
Simulation time 204239681164 ps
CPU time 477.74 seconds
Started May 07 03:25:20 PM PDT 24
Finished May 07 03:33:18 PM PDT 24
Peak memory 202316 kb
Host smart-4c02f696-a54b-4d81-b45e-330d1431aea7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345926827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2345926827
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1488697018
Short name T46
Test name
Test status
Simulation time 79051433443 ps
CPU time 353.59 seconds
Started May 07 03:25:18 PM PDT 24
Finished May 07 03:31:13 PM PDT 24
Peak memory 202684 kb
Host smart-3d53d8e1-ce35-42e6-a9ea-4124e3af7277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488697018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1488697018
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2644594999
Short name T365
Test name
Test status
Simulation time 23900558777 ps
CPU time 57.65 seconds
Started May 07 03:25:17 PM PDT 24
Finished May 07 03:26:16 PM PDT 24
Peak memory 202128 kb
Host smart-7eed8aaf-d6fc-4243-8120-6ef733a10aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644594999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2644594999
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2007131771
Short name T520
Test name
Test status
Simulation time 4043365022 ps
CPU time 5.89 seconds
Started May 07 03:25:12 PM PDT 24
Finished May 07 03:25:19 PM PDT 24
Peak memory 202160 kb
Host smart-2e13755f-2a52-4f71-8a81-d48261c8a9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007131771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2007131771
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2976335447
Short name T131
Test name
Test status
Simulation time 5844762923 ps
CPU time 14.43 seconds
Started May 07 03:25:14 PM PDT 24
Finished May 07 03:25:30 PM PDT 24
Peak memory 202144 kb
Host smart-b8f48814-5549-43c9-97a2-0cabaa481017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976335447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2976335447
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1010279691
Short name T622
Test name
Test status
Simulation time 464492173 ps
CPU time 0.81 seconds
Started May 07 03:25:21 PM PDT 24
Finished May 07 03:25:23 PM PDT 24
Peak memory 202040 kb
Host smart-7862dd9e-50d5-40b7-8897-19a4aa7a910c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010279691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1010279691
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1560636463
Short name T699
Test name
Test status
Simulation time 157724839941 ps
CPU time 59.55 seconds
Started May 07 03:25:19 PM PDT 24
Finished May 07 03:26:19 PM PDT 24
Peak memory 202192 kb
Host smart-58004078-29db-40ef-bd4d-37bcdbf8dacb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560636463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1560636463
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3678599970
Short name T557
Test name
Test status
Simulation time 373968134360 ps
CPU time 184.4 seconds
Started May 07 03:25:18 PM PDT 24
Finished May 07 03:28:23 PM PDT 24
Peak memory 202312 kb
Host smart-7d821fc5-8044-4e8d-b4f4-548b4b7fce6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678599970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3678599970
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1709044729
Short name T548
Test name
Test status
Simulation time 165743512521 ps
CPU time 256.25 seconds
Started May 07 03:25:23 PM PDT 24
Finished May 07 03:29:41 PM PDT 24
Peak memory 202304 kb
Host smart-89365885-2f29-4eab-aab7-ec089d7c0c12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709044729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1709044729
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3922286445
Short name T527
Test name
Test status
Simulation time 331273496492 ps
CPU time 838.87 seconds
Started May 07 03:25:20 PM PDT 24
Finished May 07 03:39:20 PM PDT 24
Peak memory 202312 kb
Host smart-53001dfe-6340-4f96-b1a3-e51044395fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922286445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3922286445
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2285374569
Short name T436
Test name
Test status
Simulation time 481854967639 ps
CPU time 1189.52 seconds
Started May 07 03:25:21 PM PDT 24
Finished May 07 03:45:12 PM PDT 24
Peak memory 202352 kb
Host smart-f600b1ed-090b-4099-a1cc-8dc5f00d1e1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285374569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2285374569
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2249109848
Short name T237
Test name
Test status
Simulation time 181711762061 ps
CPU time 123.82 seconds
Started May 07 03:25:20 PM PDT 24
Finished May 07 03:27:25 PM PDT 24
Peak memory 202316 kb
Host smart-a2625fc2-23d5-4e3a-82ec-3101de15f12b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249109848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2249109848
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.992777024
Short name T542
Test name
Test status
Simulation time 403522977394 ps
CPU time 1000.37 seconds
Started May 07 03:25:17 PM PDT 24
Finished May 07 03:41:59 PM PDT 24
Peak memory 202336 kb
Host smart-a2dc60d6-6b95-4609-b74d-805db2075fab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992777024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.992777024
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1253999353
Short name T503
Test name
Test status
Simulation time 87558901403 ps
CPU time 439.54 seconds
Started May 07 03:25:25 PM PDT 24
Finished May 07 03:32:45 PM PDT 24
Peak memory 202804 kb
Host smart-d165838d-3300-469a-b1a2-1c4b8e17c962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253999353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1253999353
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.436731702
Short name T471
Test name
Test status
Simulation time 43021691969 ps
CPU time 91.97 seconds
Started May 07 03:25:18 PM PDT 24
Finished May 07 03:26:51 PM PDT 24
Peak memory 202128 kb
Host smart-68573a00-93a0-4c26-a238-4f50a60a9b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436731702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.436731702
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1402357834
Short name T685
Test name
Test status
Simulation time 3833410299 ps
CPU time 3.02 seconds
Started May 07 03:25:16 PM PDT 24
Finished May 07 03:25:20 PM PDT 24
Peak memory 202116 kb
Host smart-1b8a7a47-e9bf-4039-a91a-6530f48ab1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402357834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1402357834
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1872568420
Short name T489
Test name
Test status
Simulation time 6186664266 ps
CPU time 14.77 seconds
Started May 07 03:25:13 PM PDT 24
Finished May 07 03:25:29 PM PDT 24
Peak memory 202140 kb
Host smart-caddec41-95ee-48e5-a6e5-b9fe6148444c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872568420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1872568420
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3086163306
Short name T450
Test name
Test status
Simulation time 373433065061 ps
CPU time 417.65 seconds
Started May 07 03:25:23 PM PDT 24
Finished May 07 03:32:22 PM PDT 24
Peak memory 202388 kb
Host smart-3f3fe85f-5447-4c2c-87c8-6b88c0c2782b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086163306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3086163306
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3770792623
Short name T333
Test name
Test status
Simulation time 71589850114 ps
CPU time 166.26 seconds
Started May 07 03:25:22 PM PDT 24
Finished May 07 03:28:10 PM PDT 24
Peak memory 211040 kb
Host smart-7e0eb754-21bb-4b3e-ad3f-faa8545478a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770792623 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3770792623
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1326204992
Short name T583
Test name
Test status
Simulation time 345589559 ps
CPU time 1.39 seconds
Started May 07 03:25:21 PM PDT 24
Finished May 07 03:25:24 PM PDT 24
Peak memory 202056 kb
Host smart-e30dd611-83d3-452f-842a-2c9c5fc134a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326204992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1326204992
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.237342635
Short name T214
Test name
Test status
Simulation time 514630732855 ps
CPU time 296.9 seconds
Started May 07 03:25:20 PM PDT 24
Finished May 07 03:30:18 PM PDT 24
Peak memory 202292 kb
Host smart-28de7d11-0dd0-48ed-af1b-c87f1a73a1fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237342635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.237342635
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.718563535
Short name T236
Test name
Test status
Simulation time 160006517587 ps
CPU time 102.42 seconds
Started May 07 03:25:28 PM PDT 24
Finished May 07 03:27:12 PM PDT 24
Peak memory 202412 kb
Host smart-f43ae02b-f1a9-420b-a070-9abbd1f4d213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718563535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.718563535
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2688768423
Short name T650
Test name
Test status
Simulation time 166699330498 ps
CPU time 51.69 seconds
Started May 07 03:25:22 PM PDT 24
Finished May 07 03:26:15 PM PDT 24
Peak memory 202408 kb
Host smart-edd17903-ae68-473b-bb0c-5c801dda6e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688768423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2688768423
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2112695019
Short name T754
Test name
Test status
Simulation time 482987631583 ps
CPU time 564.6 seconds
Started May 07 03:25:17 PM PDT 24
Finished May 07 03:34:43 PM PDT 24
Peak memory 202308 kb
Host smart-aea21243-8edc-4403-bc82-2a6840fd4ef7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112695019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2112695019
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2916064650
Short name T264
Test name
Test status
Simulation time 488896423504 ps
CPU time 607.8 seconds
Started May 07 03:25:20 PM PDT 24
Finished May 07 03:35:29 PM PDT 24
Peak memory 202392 kb
Host smart-7993fb62-ae64-40d7-a64f-266ada493a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916064650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2916064650
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3144666576
Short name T390
Test name
Test status
Simulation time 162766506632 ps
CPU time 94.52 seconds
Started May 07 03:25:20 PM PDT 24
Finished May 07 03:26:55 PM PDT 24
Peak memory 202304 kb
Host smart-4e090ae4-c99c-42fc-97fd-1a744fca82d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144666576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3144666576
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.427491431
Short name T474
Test name
Test status
Simulation time 619592540329 ps
CPU time 1333.15 seconds
Started May 07 03:25:23 PM PDT 24
Finished May 07 03:47:38 PM PDT 24
Peak memory 202404 kb
Host smart-42e82ae0-9f68-4b0d-9c91-13e1ec3f5aa5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427491431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.427491431
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.974510248
Short name T737
Test name
Test status
Simulation time 85405593829 ps
CPU time 282.23 seconds
Started May 07 03:25:19 PM PDT 24
Finished May 07 03:30:03 PM PDT 24
Peak memory 202696 kb
Host smart-b8e73422-2604-4483-bdbc-8b6ca9a6d80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974510248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.974510248
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.289547064
Short name T719
Test name
Test status
Simulation time 43549035311 ps
CPU time 48.41 seconds
Started May 07 03:25:18 PM PDT 24
Finished May 07 03:26:07 PM PDT 24
Peak memory 202132 kb
Host smart-86520f88-d010-4bbb-98ec-f6b26462a00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289547064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.289547064
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3747064633
Short name T799
Test name
Test status
Simulation time 3006272331 ps
CPU time 1.08 seconds
Started May 07 03:25:19 PM PDT 24
Finished May 07 03:25:21 PM PDT 24
Peak memory 202132 kb
Host smart-0a43fc0f-0205-42d4-80bf-f19062f03378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747064633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3747064633
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.4207272232
Short name T367
Test name
Test status
Simulation time 6087212029 ps
CPU time 4.2 seconds
Started May 07 03:25:26 PM PDT 24
Finished May 07 03:25:33 PM PDT 24
Peak memory 202160 kb
Host smart-0bccd25c-c796-4aef-a2fd-095522c90827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207272232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.4207272232
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3463541279
Short name T308
Test name
Test status
Simulation time 173186250618 ps
CPU time 508.24 seconds
Started May 07 03:25:23 PM PDT 24
Finished May 07 03:33:53 PM PDT 24
Peak memory 210996 kb
Host smart-d64750d4-d494-478b-82fe-90247e103768
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463541279 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3463541279
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1785140222
Short name T371
Test name
Test status
Simulation time 375770128 ps
CPU time 0.76 seconds
Started May 07 03:25:28 PM PDT 24
Finished May 07 03:25:31 PM PDT 24
Peak memory 201988 kb
Host smart-fee30f55-3563-40e9-bcec-6956aae81f6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785140222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1785140222
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2997992762
Short name T174
Test name
Test status
Simulation time 409103914026 ps
CPU time 256.01 seconds
Started May 07 03:25:22 PM PDT 24
Finished May 07 03:29:39 PM PDT 24
Peak memory 202336 kb
Host smart-af2717e5-4db3-4d63-bedc-f0d168cb2928
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997992762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2997992762
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.501118535
Short name T194
Test name
Test status
Simulation time 518252591987 ps
CPU time 307.35 seconds
Started May 07 03:25:21 PM PDT 24
Finished May 07 03:30:30 PM PDT 24
Peak memory 202320 kb
Host smart-4f878315-f7a9-48e1-aa4d-9bfc1e0c8cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501118535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.501118535
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2912708320
Short name T570
Test name
Test status
Simulation time 327033125746 ps
CPU time 389.69 seconds
Started May 07 03:25:25 PM PDT 24
Finished May 07 03:31:55 PM PDT 24
Peak memory 202320 kb
Host smart-dc1633ee-7aac-40b6-9d56-82755b0426fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912708320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2912708320
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.444160228
Short name T636
Test name
Test status
Simulation time 162193865052 ps
CPU time 124.3 seconds
Started May 07 03:25:21 PM PDT 24
Finished May 07 03:27:27 PM PDT 24
Peak memory 202308 kb
Host smart-85057791-756d-47b0-937b-5940b718bb3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=444160228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.444160228
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1325089455
Short name T247
Test name
Test status
Simulation time 165692857726 ps
CPU time 96.77 seconds
Started May 07 03:25:21 PM PDT 24
Finished May 07 03:26:59 PM PDT 24
Peak memory 202392 kb
Host smart-2e889879-9187-4905-ba1c-ac2dd463a9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325089455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1325089455
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1928537427
Short name T149
Test name
Test status
Simulation time 162523015652 ps
CPU time 46.22 seconds
Started May 07 03:25:24 PM PDT 24
Finished May 07 03:26:11 PM PDT 24
Peak memory 202368 kb
Host smart-37f3bba1-5a45-4611-9ea5-efaf4340ae93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928537427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1928537427
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2902298845
Short name T277
Test name
Test status
Simulation time 433541011409 ps
CPU time 1037.87 seconds
Started May 07 03:25:28 PM PDT 24
Finished May 07 03:42:48 PM PDT 24
Peak memory 202348 kb
Host smart-60edf9bc-57e3-4c32-887d-18c242fc161e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902298845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2902298845
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2169062233
Short name T231
Test name
Test status
Simulation time 199159965373 ps
CPU time 169.99 seconds
Started May 07 03:25:23 PM PDT 24
Finished May 07 03:28:14 PM PDT 24
Peak memory 202268 kb
Host smart-09a751ce-6f71-4482-8ace-087f4d42dc30
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169062233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2169062233
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2307845807
Short name T430
Test name
Test status
Simulation time 32081855881 ps
CPU time 71.67 seconds
Started May 07 03:25:19 PM PDT 24
Finished May 07 03:26:31 PM PDT 24
Peak memory 202120 kb
Host smart-4bdc4ef3-61b4-479d-bd7c-1f7a9288cca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307845807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2307845807
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1683153648
Short name T679
Test name
Test status
Simulation time 4109165918 ps
CPU time 2.3 seconds
Started May 07 03:25:23 PM PDT 24
Finished May 07 03:25:26 PM PDT 24
Peak memory 202140 kb
Host smart-bcea4190-c19c-4ed8-a0d7-692ca48f081a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683153648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1683153648
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2581462030
Short name T593
Test name
Test status
Simulation time 5699848027 ps
CPU time 5.39 seconds
Started May 07 03:25:24 PM PDT 24
Finished May 07 03:25:30 PM PDT 24
Peak memory 202140 kb
Host smart-93836352-39c3-47f3-9085-b30d39243777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581462030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2581462030
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2414048485
Short name T40
Test name
Test status
Simulation time 274209938703 ps
CPU time 206.54 seconds
Started May 07 03:25:26 PM PDT 24
Finished May 07 03:28:54 PM PDT 24
Peak memory 210720 kb
Host smart-8b060507-f41c-4251-af70-460686860fe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414048485 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2414048485
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.866591788
Short name T674
Test name
Test status
Simulation time 396166673 ps
CPU time 0.86 seconds
Started May 07 03:25:21 PM PDT 24
Finished May 07 03:25:23 PM PDT 24
Peak memory 202032 kb
Host smart-fbc9ead9-1c7c-477c-9f7c-6485736ecab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866591788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.866591788
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.719334960
Short name T476
Test name
Test status
Simulation time 162253785900 ps
CPU time 365.95 seconds
Started May 07 03:25:25 PM PDT 24
Finished May 07 03:31:32 PM PDT 24
Peak memory 202336 kb
Host smart-0c5a71d1-d01a-4548-bc67-f0f3fafbbddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719334960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.719334960
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2774103786
Short name T135
Test name
Test status
Simulation time 495192955691 ps
CPU time 279.43 seconds
Started May 07 03:25:33 PM PDT 24
Finished May 07 03:30:13 PM PDT 24
Peak memory 202388 kb
Host smart-c6781230-10d3-4368-8cef-49b3615dcb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774103786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2774103786
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2956908292
Short name T596
Test name
Test status
Simulation time 163609161687 ps
CPU time 364.6 seconds
Started May 07 03:25:23 PM PDT 24
Finished May 07 03:31:29 PM PDT 24
Peak memory 201756 kb
Host smart-8bba7722-ed10-4fb0-aec3-7a8182b9ea4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956908292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2956908292
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3562547088
Short name T688
Test name
Test status
Simulation time 325396754468 ps
CPU time 375.7 seconds
Started May 07 03:25:33 PM PDT 24
Finished May 07 03:31:50 PM PDT 24
Peak memory 202364 kb
Host smart-6f4f5266-e80f-449f-9cd2-01362dacd1e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562547088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3562547088
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.4257182822
Short name T163
Test name
Test status
Simulation time 562397013073 ps
CPU time 497.37 seconds
Started May 07 03:25:33 PM PDT 24
Finished May 07 03:33:52 PM PDT 24
Peak memory 202376 kb
Host smart-187d7523-be51-47c4-81f5-c50e8168e2bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257182822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.4257182822
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1528349793
Short name T415
Test name
Test status
Simulation time 400370740353 ps
CPU time 104.54 seconds
Started May 07 03:25:27 PM PDT 24
Finished May 07 03:27:14 PM PDT 24
Peak memory 202316 kb
Host smart-1b4edc23-5da0-4302-a564-1019297bf99a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528349793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1528349793
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3511239793
Short name T332
Test name
Test status
Simulation time 115165495271 ps
CPU time 618.64 seconds
Started May 07 03:25:25 PM PDT 24
Finished May 07 03:35:45 PM PDT 24
Peak memory 202680 kb
Host smart-d3a52210-9afd-40ca-9984-6142d6f0003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511239793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3511239793
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3815318324
Short name T154
Test name
Test status
Simulation time 45571185900 ps
CPU time 21.83 seconds
Started May 07 03:25:28 PM PDT 24
Finished May 07 03:25:52 PM PDT 24
Peak memory 202132 kb
Host smart-87bb45ff-dc68-400a-9d59-799192c38008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815318324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3815318324
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2730785745
Short name T745
Test name
Test status
Simulation time 5303001608 ps
CPU time 13.22 seconds
Started May 07 03:25:29 PM PDT 24
Finished May 07 03:25:45 PM PDT 24
Peak memory 202156 kb
Host smart-bcf5e17c-d518-4601-a129-34a08363f2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730785745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2730785745
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4143502884
Short name T585
Test name
Test status
Simulation time 5839132836 ps
CPU time 4.95 seconds
Started May 07 03:25:27 PM PDT 24
Finished May 07 03:25:34 PM PDT 24
Peak memory 202128 kb
Host smart-3350aa30-e630-4a7a-ac3d-a9a6e0cdfbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143502884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4143502884
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3656618024
Short name T400
Test name
Test status
Simulation time 385207208 ps
CPU time 1.51 seconds
Started May 07 03:25:35 PM PDT 24
Finished May 07 03:25:38 PM PDT 24
Peak memory 202020 kb
Host smart-111218d7-d3f6-4db6-8d95-79877b90943f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656618024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3656618024
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2305410887
Short name T597
Test name
Test status
Simulation time 169428612670 ps
CPU time 397.49 seconds
Started May 07 03:25:33 PM PDT 24
Finished May 07 03:32:11 PM PDT 24
Peak memory 202360 kb
Host smart-5c7f6f81-3ae3-44ad-bb5e-55cd9a8fcfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305410887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2305410887
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1978619113
Short name T518
Test name
Test status
Simulation time 495475978410 ps
CPU time 605.25 seconds
Started May 07 03:25:32 PM PDT 24
Finished May 07 03:35:39 PM PDT 24
Peak memory 202272 kb
Host smart-5100aa49-5627-4996-9f63-3c54ed306773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978619113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1978619113
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1060229025
Short name T103
Test name
Test status
Simulation time 488343396725 ps
CPU time 326.24 seconds
Started May 07 03:25:35 PM PDT 24
Finished May 07 03:31:03 PM PDT 24
Peak memory 202312 kb
Host smart-697a5a95-5187-4e9f-b92d-eada390cd3d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060229025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1060229025
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1102383481
Short name T680
Test name
Test status
Simulation time 165344490908 ps
CPU time 98.75 seconds
Started May 07 03:25:30 PM PDT 24
Finished May 07 03:27:11 PM PDT 24
Peak memory 202308 kb
Host smart-9720ae5d-16d0-432c-b087-b6ffec801d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102383481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1102383481
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1029665639
Short name T681
Test name
Test status
Simulation time 489574592482 ps
CPU time 261.49 seconds
Started May 07 03:25:27 PM PDT 24
Finished May 07 03:29:51 PM PDT 24
Peak memory 202348 kb
Host smart-473281d1-2c9e-4029-86fb-6d66d0102597
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029665639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1029665639
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3235604943
Short name T473
Test name
Test status
Simulation time 191585531993 ps
CPU time 206.1 seconds
Started May 07 03:25:28 PM PDT 24
Finished May 07 03:28:57 PM PDT 24
Peak memory 202352 kb
Host smart-b79aa475-6594-4422-9de6-ca4244458d46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235604943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3235604943
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1126665201
Short name T638
Test name
Test status
Simulation time 202147933222 ps
CPU time 459.86 seconds
Started May 07 03:25:25 PM PDT 24
Finished May 07 03:33:07 PM PDT 24
Peak memory 202412 kb
Host smart-3e3ed1cc-f2d2-4d14-856e-35ca1f8afa83
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126665201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1126665201
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1040185006
Short name T750
Test name
Test status
Simulation time 120156465028 ps
CPU time 341.61 seconds
Started May 07 03:25:33 PM PDT 24
Finished May 07 03:31:15 PM PDT 24
Peak memory 202740 kb
Host smart-51772356-bdcb-421d-b387-c1d0a8bc0cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040185006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1040185006
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3819024935
Short name T401
Test name
Test status
Simulation time 26586265969 ps
CPU time 33.17 seconds
Started May 07 03:25:28 PM PDT 24
Finished May 07 03:26:04 PM PDT 24
Peak memory 202164 kb
Host smart-de69b1bc-f073-4f7c-b9b3-54747f058982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819024935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3819024935
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3532192229
Short name T96
Test name
Test status
Simulation time 5000795219 ps
CPU time 6.93 seconds
Started May 07 03:25:22 PM PDT 24
Finished May 07 03:25:30 PM PDT 24
Peak memory 202152 kb
Host smart-58769db7-da0d-416f-aa98-0d755b852b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532192229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3532192229
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.722030167
Short name T524
Test name
Test status
Simulation time 5977192689 ps
CPU time 14.17 seconds
Started May 07 03:25:21 PM PDT 24
Finished May 07 03:25:36 PM PDT 24
Peak memory 202108 kb
Host smart-6a2d4256-cbbd-4c55-a3bf-1e139b68c3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722030167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.722030167
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1953440989
Short name T274
Test name
Test status
Simulation time 388019349483 ps
CPU time 721.5 seconds
Started May 07 03:25:34 PM PDT 24
Finished May 07 03:37:37 PM PDT 24
Peak memory 210868 kb
Host smart-9af6454c-fa9b-464f-ac80-7ed416f97d1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953440989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1953440989
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3319716500
Short name T662
Test name
Test status
Simulation time 64389829702 ps
CPU time 147.14 seconds
Started May 07 03:25:36 PM PDT 24
Finished May 07 03:28:04 PM PDT 24
Peak memory 211224 kb
Host smart-3dbf2ab4-5707-426c-a33f-e6f3e28eb90e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319716500 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3319716500
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1533702868
Short name T568
Test name
Test status
Simulation time 362314051 ps
CPU time 1.5 seconds
Started May 07 03:25:35 PM PDT 24
Finished May 07 03:25:38 PM PDT 24
Peak memory 202016 kb
Host smart-0b1c193b-d321-4227-abb9-5668a9589e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533702868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1533702868
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3284521412
Short name T374
Test name
Test status
Simulation time 158385192781 ps
CPU time 50.51 seconds
Started May 07 03:25:33 PM PDT 24
Finished May 07 03:26:25 PM PDT 24
Peak memory 202316 kb
Host smart-fb9a1954-cae2-479f-8e5d-d4d0411031e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284521412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3284521412
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3394918670
Short name T459
Test name
Test status
Simulation time 167436461772 ps
CPU time 403.45 seconds
Started May 07 03:25:34 PM PDT 24
Finished May 07 03:32:19 PM PDT 24
Peak memory 202268 kb
Host smart-ca81d445-b7a1-4187-9c0d-ce3c41687358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394918670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3394918670
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1908708639
Short name T553
Test name
Test status
Simulation time 165189699164 ps
CPU time 389.13 seconds
Started May 07 03:25:33 PM PDT 24
Finished May 07 03:32:04 PM PDT 24
Peak memory 202208 kb
Host smart-a6eed55c-a759-4e80-9c39-d2a15bcaaf78
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908708639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1908708639
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1407517307
Short name T234
Test name
Test status
Simulation time 573149410660 ps
CPU time 1436.7 seconds
Started May 07 03:25:29 PM PDT 24
Finished May 07 03:49:28 PM PDT 24
Peak memory 202320 kb
Host smart-e894c804-6161-420a-9b97-1935371a55fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407517307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1407517307
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2929684357
Short name T32
Test name
Test status
Simulation time 584439197515 ps
CPU time 1276.3 seconds
Started May 07 03:25:31 PM PDT 24
Finished May 07 03:46:49 PM PDT 24
Peak memory 202380 kb
Host smart-e00c9759-dbb3-4a10-a1b4-a359e03d5c02
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929684357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2929684357
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.234704501
Short name T447
Test name
Test status
Simulation time 97735636669 ps
CPU time 505.04 seconds
Started May 07 03:25:32 PM PDT 24
Finished May 07 03:33:59 PM PDT 24
Peak memory 202720 kb
Host smart-ca89a0b5-e43d-4b2d-bd67-2da382cb1bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234704501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.234704501
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.241834626
Short name T701
Test name
Test status
Simulation time 35815501031 ps
CPU time 16.65 seconds
Started May 07 03:25:28 PM PDT 24
Finished May 07 03:25:47 PM PDT 24
Peak memory 202100 kb
Host smart-67cbb03a-7a6b-4ea3-9b99-f56583639936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241834626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.241834626
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2716293391
Short name T802
Test name
Test status
Simulation time 4343789159 ps
CPU time 1.69 seconds
Started May 07 03:25:32 PM PDT 24
Finished May 07 03:25:34 PM PDT 24
Peak memory 202144 kb
Host smart-13b19a68-935f-4b47-8ff1-9224a6f1c2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716293391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2716293391
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.134427668
Short name T781
Test name
Test status
Simulation time 5830533963 ps
CPU time 4.35 seconds
Started May 07 03:25:29 PM PDT 24
Finished May 07 03:25:36 PM PDT 24
Peak memory 202160 kb
Host smart-b2d41e94-1ba7-46ee-9f1c-36c1549e8262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134427668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.134427668
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.537218587
Short name T19
Test name
Test status
Simulation time 25239047616 ps
CPU time 47.63 seconds
Started May 07 03:25:33 PM PDT 24
Finished May 07 03:26:22 PM PDT 24
Peak memory 210624 kb
Host smart-16f468d7-12e8-410b-b3d6-43b87e7a0a9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537218587 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.537218587
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.4208243162
Short name T428
Test name
Test status
Simulation time 547162499 ps
CPU time 0.94 seconds
Started May 07 03:25:35 PM PDT 24
Finished May 07 03:25:38 PM PDT 24
Peak memory 202012 kb
Host smart-3a731817-cbd5-4420-b648-cf1495536193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208243162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.4208243162
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3903471519
Short name T554
Test name
Test status
Simulation time 175644194234 ps
CPU time 219.26 seconds
Started May 07 03:25:36 PM PDT 24
Finished May 07 03:29:16 PM PDT 24
Peak memory 202400 kb
Host smart-426f9697-a484-4b01-bf13-f1017c062875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903471519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3903471519
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2800225303
Short name T505
Test name
Test status
Simulation time 162324540185 ps
CPU time 365.38 seconds
Started May 07 03:25:31 PM PDT 24
Finished May 07 03:31:38 PM PDT 24
Peak memory 202380 kb
Host smart-1ed08ad1-1353-46a6-b484-49e7a684c1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800225303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2800225303
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2720723098
Short name T722
Test name
Test status
Simulation time 329094064661 ps
CPU time 186.71 seconds
Started May 07 03:25:33 PM PDT 24
Finished May 07 03:28:41 PM PDT 24
Peak memory 202308 kb
Host smart-9e72bd53-b35c-4304-ac76-95b6e3716b41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720723098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2720723098
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.808268980
Short name T732
Test name
Test status
Simulation time 493596518213 ps
CPU time 1078.59 seconds
Started May 07 03:25:33 PM PDT 24
Finished May 07 03:43:32 PM PDT 24
Peak memory 202304 kb
Host smart-4c6efe15-426e-4403-a5a7-5b6d012c3b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808268980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.808268980
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.539460046
Short name T148
Test name
Test status
Simulation time 336967303009 ps
CPU time 696.17 seconds
Started May 07 03:25:34 PM PDT 24
Finished May 07 03:37:11 PM PDT 24
Peak memory 202372 kb
Host smart-42916f74-97e2-43cc-a3f7-35c1151d9502
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=539460046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.539460046
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3058178764
Short name T779
Test name
Test status
Simulation time 190989200222 ps
CPU time 54.92 seconds
Started May 07 03:25:32 PM PDT 24
Finished May 07 03:26:28 PM PDT 24
Peak memory 202336 kb
Host smart-2fb6b9c2-5780-4812-a531-d86a55a7adb3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058178764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3058178764
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2334270078
Short name T796
Test name
Test status
Simulation time 590347337592 ps
CPU time 1273.04 seconds
Started May 07 03:25:32 PM PDT 24
Finished May 07 03:46:46 PM PDT 24
Peak memory 202316 kb
Host smart-84a78216-a23f-41e3-b59a-439cbdb437b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334270078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2334270078
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.4001183054
Short name T44
Test name
Test status
Simulation time 96468191234 ps
CPU time 369.71 seconds
Started May 07 03:25:40 PM PDT 24
Finished May 07 03:31:51 PM PDT 24
Peak memory 202732 kb
Host smart-e9eb540c-b479-4491-95b7-a4a128d4c91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001183054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.4001183054
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.4023906950
Short name T345
Test name
Test status
Simulation time 43901485961 ps
CPU time 84.75 seconds
Started May 07 03:25:37 PM PDT 24
Finished May 07 03:27:03 PM PDT 24
Peak memory 202164 kb
Host smart-8a98ba97-38f0-4c7a-938a-621ec6977f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023906950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.4023906950
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1905545352
Short name T698
Test name
Test status
Simulation time 4638535694 ps
CPU time 4.91 seconds
Started May 07 03:25:41 PM PDT 24
Finished May 07 03:25:47 PM PDT 24
Peak memory 202160 kb
Host smart-9c069fd9-821f-4ac1-b51d-121e1c5f9c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905545352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1905545352
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2806295558
Short name T751
Test name
Test status
Simulation time 6096603755 ps
CPU time 4.43 seconds
Started May 07 03:25:31 PM PDT 24
Finished May 07 03:25:37 PM PDT 24
Peak memory 202156 kb
Host smart-6c69cdec-4838-47d5-9088-a6a64fec7195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806295558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2806295558
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1469171691
Short name T310
Test name
Test status
Simulation time 335391756977 ps
CPU time 211.73 seconds
Started May 07 03:25:34 PM PDT 24
Finished May 07 03:29:07 PM PDT 24
Peak memory 202368 kb
Host smart-4c574c0c-13c1-4b0b-bca1-0205834fd737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469171691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1469171691
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3763181621
Short name T67
Test name
Test status
Simulation time 499647433 ps
CPU time 0.71 seconds
Started May 07 03:25:40 PM PDT 24
Finished May 07 03:25:42 PM PDT 24
Peak memory 202004 kb
Host smart-b8a3953b-60df-47d6-9ea1-f519e24be614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763181621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3763181621
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.558128936
Short name T456
Test name
Test status
Simulation time 324707870111 ps
CPU time 195.4 seconds
Started May 07 03:25:35 PM PDT 24
Finished May 07 03:28:52 PM PDT 24
Peak memory 202276 kb
Host smart-4d9de8bd-82eb-48aa-abd6-7a2a6a200739
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=558128936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.558128936
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.241279304
Short name T172
Test name
Test status
Simulation time 486997252276 ps
CPU time 1131.01 seconds
Started May 07 03:25:41 PM PDT 24
Finished May 07 03:44:33 PM PDT 24
Peak memory 201800 kb
Host smart-e9cdafde-2b2e-4691-80a1-ac769eb25791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241279304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.241279304
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.4017627586
Short name T368
Test name
Test status
Simulation time 494547133991 ps
CPU time 1110.27 seconds
Started May 07 03:25:41 PM PDT 24
Finished May 07 03:44:12 PM PDT 24
Peak memory 202272 kb
Host smart-10d47fcc-22ec-4c58-ba8e-c9a4aef216c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017627586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.4017627586
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2435372554
Short name T551
Test name
Test status
Simulation time 172324152687 ps
CPU time 43.31 seconds
Started May 07 03:25:35 PM PDT 24
Finished May 07 03:26:20 PM PDT 24
Peak memory 202408 kb
Host smart-043120b2-da22-4bb6-87bb-62eff3ec5643
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435372554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2435372554
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1591327879
Short name T748
Test name
Test status
Simulation time 601790192301 ps
CPU time 184.36 seconds
Started May 07 03:25:42 PM PDT 24
Finished May 07 03:28:47 PM PDT 24
Peak memory 202368 kb
Host smart-c0b8160b-f3f2-4132-8e4e-184ca7fbf420
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591327879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1591327879
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3767069782
Short name T611
Test name
Test status
Simulation time 91422543177 ps
CPU time 319 seconds
Started May 07 03:25:40 PM PDT 24
Finished May 07 03:31:00 PM PDT 24
Peak memory 202732 kb
Host smart-03310d57-e488-4669-9722-4235ce422f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767069782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3767069782
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2699411605
Short name T370
Test name
Test status
Simulation time 29085058018 ps
CPU time 43.52 seconds
Started May 07 03:25:34 PM PDT 24
Finished May 07 03:26:19 PM PDT 24
Peak memory 202088 kb
Host smart-3793c14c-bf5a-4049-a5e0-53ab7404740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699411605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2699411605
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1043999328
Short name T545
Test name
Test status
Simulation time 5105255087 ps
CPU time 6.34 seconds
Started May 07 03:25:37 PM PDT 24
Finished May 07 03:25:44 PM PDT 24
Peak memory 202136 kb
Host smart-283a2f3a-74ee-4f08-85f3-d9fbafcb47c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043999328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1043999328
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1710006607
Short name T397
Test name
Test status
Simulation time 5762817169 ps
CPU time 4.23 seconds
Started May 07 03:25:34 PM PDT 24
Finished May 07 03:25:40 PM PDT 24
Peak memory 202160 kb
Host smart-b72dbfd6-deab-4f99-b9d6-04b83cdb58bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710006607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1710006607
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.425337293
Short name T533
Test name
Test status
Simulation time 482156246849 ps
CPU time 723.78 seconds
Started May 07 03:25:40 PM PDT 24
Finished May 07 03:37:45 PM PDT 24
Peak memory 210936 kb
Host smart-e93e46c4-5edd-4671-82fa-855733ff1c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425337293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
425337293
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1754517589
Short name T668
Test name
Test status
Simulation time 328914468 ps
CPU time 0.8 seconds
Started May 07 03:25:42 PM PDT 24
Finished May 07 03:25:44 PM PDT 24
Peak memory 202000 kb
Host smart-accdd8b1-0a40-4dc3-a50f-189499b82b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754517589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1754517589
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3762254380
Short name T184
Test name
Test status
Simulation time 181143205069 ps
CPU time 404.41 seconds
Started May 07 03:25:42 PM PDT 24
Finished May 07 03:32:27 PM PDT 24
Peak memory 202304 kb
Host smart-30569a02-dad4-4aca-9b46-c93bd89ee731
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762254380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3762254380
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.4050744650
Short name T162
Test name
Test status
Simulation time 341790740147 ps
CPU time 377.43 seconds
Started May 07 03:25:41 PM PDT 24
Finished May 07 03:32:00 PM PDT 24
Peak memory 202308 kb
Host smart-a4db44ec-bde6-43bb-8e5b-641be300ee8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050744650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.4050744650
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3503985058
Short name T300
Test name
Test status
Simulation time 326394458759 ps
CPU time 708.77 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:37:36 PM PDT 24
Peak memory 202244 kb
Host smart-b29dc190-741e-4bbe-99d0-eb21e48df563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503985058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3503985058
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1251061102
Short name T356
Test name
Test status
Simulation time 329693060288 ps
CPU time 63.96 seconds
Started May 07 03:25:44 PM PDT 24
Finished May 07 03:26:48 PM PDT 24
Peak memory 202376 kb
Host smart-14843726-ed23-49d9-b921-1bd1b7c46afa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251061102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1251061102
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2491197259
Short name T213
Test name
Test status
Simulation time 329787649205 ps
CPU time 784.09 seconds
Started May 07 03:25:39 PM PDT 24
Finished May 07 03:38:44 PM PDT 24
Peak memory 202304 kb
Host smart-dfb4bcc0-c0a8-4f63-a426-4701623db7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491197259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2491197259
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.892473440
Short name T483
Test name
Test status
Simulation time 328992742867 ps
CPU time 143.14 seconds
Started May 07 03:25:47 PM PDT 24
Finished May 07 03:28:12 PM PDT 24
Peak memory 202324 kb
Host smart-62f46b01-4506-4afc-90c5-1e3aba7458ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=892473440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.892473440
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.4077253440
Short name T735
Test name
Test status
Simulation time 386608498335 ps
CPU time 638.09 seconds
Started May 07 03:25:45 PM PDT 24
Finished May 07 03:36:23 PM PDT 24
Peak memory 202376 kb
Host smart-8758c69c-db25-4d00-978b-0832234f6290
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077253440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.4077253440
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2379718635
Short name T435
Test name
Test status
Simulation time 600625475179 ps
CPU time 1380.5 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:48:48 PM PDT 24
Peak memory 202288 kb
Host smart-455e522a-34f8-4d2d-93ba-295af1921445
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379718635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2379718635
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3562025796
Short name T206
Test name
Test status
Simulation time 80189797447 ps
CPU time 275.6 seconds
Started May 07 03:25:45 PM PDT 24
Finished May 07 03:30:22 PM PDT 24
Peak memory 202740 kb
Host smart-958539a2-c49e-4994-af90-ae6f6681b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562025796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3562025796
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2645252822
Short name T8
Test name
Test status
Simulation time 30286693651 ps
CPU time 68.25 seconds
Started May 07 03:25:50 PM PDT 24
Finished May 07 03:26:59 PM PDT 24
Peak memory 202248 kb
Host smart-df57da18-41d5-4084-a04b-5688373c2cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645252822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2645252822
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3014064942
Short name T630
Test name
Test status
Simulation time 4508693981 ps
CPU time 11.77 seconds
Started May 07 03:25:40 PM PDT 24
Finished May 07 03:25:53 PM PDT 24
Peak memory 202148 kb
Host smart-a0daea14-6e7c-4e28-95a2-ce0183895b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014064942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3014064942
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1600150781
Short name T541
Test name
Test status
Simulation time 6005361857 ps
CPU time 15.15 seconds
Started May 07 03:25:43 PM PDT 24
Finished May 07 03:25:59 PM PDT 24
Peak memory 202132 kb
Host smart-0eddb756-9885-4c36-8ff1-442c962e9691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600150781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1600150781
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1231468694
Short name T561
Test name
Test status
Simulation time 102500330037 ps
CPU time 523.9 seconds
Started May 07 03:25:41 PM PDT 24
Finished May 07 03:34:26 PM PDT 24
Peak memory 202688 kb
Host smart-8fc47af9-5930-4236-b8fc-0fd8984069e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231468694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1231468694
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3515166231
Short name T93
Test name
Test status
Simulation time 498401156795 ps
CPU time 334.88 seconds
Started May 07 03:25:45 PM PDT 24
Finished May 07 03:31:21 PM PDT 24
Peak memory 211044 kb
Host smart-b3f93845-0559-4fb9-a308-88006a469941
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515166231 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3515166231
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1711021867
Short name T614
Test name
Test status
Simulation time 443282561 ps
CPU time 0.91 seconds
Started May 07 03:24:56 PM PDT 24
Finished May 07 03:24:59 PM PDT 24
Peak memory 201996 kb
Host smart-3b3b9a44-881e-4fb8-a5cf-5e8425683786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711021867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1711021867
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2048876085
Short name T11
Test name
Test status
Simulation time 355451457038 ps
CPU time 410.63 seconds
Started May 07 03:24:57 PM PDT 24
Finished May 07 03:31:49 PM PDT 24
Peak memory 202356 kb
Host smart-2cddb8f9-a234-4988-bea3-8b75c6e7861a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048876085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2048876085
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4240964331
Short name T260
Test name
Test status
Simulation time 337286695062 ps
CPU time 194.89 seconds
Started May 07 03:24:56 PM PDT 24
Finished May 07 03:28:12 PM PDT 24
Peak memory 202384 kb
Host smart-be805244-a85b-43aa-b223-f05fd736b1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240964331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4240964331
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3156066878
Short name T717
Test name
Test status
Simulation time 169016766521 ps
CPU time 102.55 seconds
Started May 07 03:25:00 PM PDT 24
Finished May 07 03:26:43 PM PDT 24
Peak memory 202284 kb
Host smart-7bcfbaaa-f6b9-4b65-be5d-3dc0a8befda4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156066878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3156066878
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2558926188
Short name T539
Test name
Test status
Simulation time 170711150281 ps
CPU time 404.44 seconds
Started May 07 03:25:05 PM PDT 24
Finished May 07 03:31:50 PM PDT 24
Peak memory 202240 kb
Host smart-496e5af4-945a-4b6a-900d-dc207844b0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558926188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2558926188
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3634918430
Short name T99
Test name
Test status
Simulation time 491688771267 ps
CPU time 321.94 seconds
Started May 07 03:24:56 PM PDT 24
Finished May 07 03:30:20 PM PDT 24
Peak memory 202316 kb
Host smart-e1d439db-f21e-492b-847c-7f4da252840c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634918430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3634918430
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2579096468
Short name T190
Test name
Test status
Simulation time 178124334654 ps
CPU time 128.04 seconds
Started May 07 03:24:55 PM PDT 24
Finished May 07 03:27:05 PM PDT 24
Peak memory 202396 kb
Host smart-76ab2f97-417b-41f5-9d25-4e8a0e1545af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579096468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2579096468
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.145366008
Short name T538
Test name
Test status
Simulation time 409464417827 ps
CPU time 456.04 seconds
Started May 07 03:25:03 PM PDT 24
Finished May 07 03:32:40 PM PDT 24
Peak memory 202308 kb
Host smart-49bc1e4e-7840-4317-b45a-69172f9f49b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145366008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.145366008
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2272852309
Short name T399
Test name
Test status
Simulation time 142507559679 ps
CPU time 425.31 seconds
Started May 07 03:24:59 PM PDT 24
Finished May 07 03:32:05 PM PDT 24
Peak memory 202656 kb
Host smart-c4e06505-cfcb-4300-af76-1e298e4ac2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272852309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2272852309
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1884079865
Short name T569
Test name
Test status
Simulation time 42590168648 ps
CPU time 53.05 seconds
Started May 07 03:24:56 PM PDT 24
Finished May 07 03:25:50 PM PDT 24
Peak memory 202116 kb
Host smart-2432c0ad-0d12-4f86-b92f-fb72ccea62d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884079865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1884079865
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3019447637
Short name T444
Test name
Test status
Simulation time 2980330589 ps
CPU time 3.07 seconds
Started May 07 03:25:09 PM PDT 24
Finished May 07 03:25:13 PM PDT 24
Peak memory 202128 kb
Host smart-565aa702-63ec-479f-884c-174028dc3cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019447637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3019447637
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2668670494
Short name T73
Test name
Test status
Simulation time 3611792727 ps
CPU time 2.5 seconds
Started May 07 03:25:04 PM PDT 24
Finished May 07 03:25:08 PM PDT 24
Peak memory 217772 kb
Host smart-7dbf15aa-d0f2-4e46-b4ad-9e9dd8896425
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668670494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2668670494
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2923130852
Short name T344
Test name
Test status
Simulation time 5817177285 ps
CPU time 13.12 seconds
Started May 07 03:24:59 PM PDT 24
Finished May 07 03:25:14 PM PDT 24
Peak memory 202108 kb
Host smart-72f6964d-6faa-4415-98af-e39afcd9da73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923130852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2923130852
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.4074512704
Short name T510
Test name
Test status
Simulation time 5048154983 ps
CPU time 11.34 seconds
Started May 07 03:24:55 PM PDT 24
Finished May 07 03:25:08 PM PDT 24
Peak memory 202136 kb
Host smart-16994d41-1b5b-4ed7-9a86-42dd3bc6776a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074512704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
4074512704
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1512212745
Short name T657
Test name
Test status
Simulation time 119070402404 ps
CPU time 43.71 seconds
Started May 07 03:24:59 PM PDT 24
Finished May 07 03:25:44 PM PDT 24
Peak memory 202368 kb
Host smart-a7da4907-81be-45e9-95dd-152368e151ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512212745 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1512212745
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2799650076
Short name T348
Test name
Test status
Simulation time 539796761 ps
CPU time 1.09 seconds
Started May 07 03:25:45 PM PDT 24
Finished May 07 03:25:47 PM PDT 24
Peak memory 202028 kb
Host smart-13cabf4a-7e2a-47e2-a3a9-e1bb4885d91a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799650076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2799650076
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3435300291
Short name T709
Test name
Test status
Simulation time 387789039055 ps
CPU time 731.63 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:37:59 PM PDT 24
Peak memory 202344 kb
Host smart-9f93ebe4-f85f-4497-9db5-e61b41ffcc61
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435300291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3435300291
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1274013394
Short name T276
Test name
Test status
Simulation time 461000107975 ps
CPU time 261.89 seconds
Started May 07 03:25:48 PM PDT 24
Finished May 07 03:30:10 PM PDT 24
Peak memory 202316 kb
Host smart-dfd77e82-5625-46bb-9bd1-8c87626f02c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274013394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1274013394
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1522062099
Short name T311
Test name
Test status
Simulation time 329287306062 ps
CPU time 187.11 seconds
Started May 07 03:25:47 PM PDT 24
Finished May 07 03:28:55 PM PDT 24
Peak memory 202324 kb
Host smart-d753dbbd-05e2-44a9-a89c-a7b4326b624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522062099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1522062099
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2660665620
Short name T451
Test name
Test status
Simulation time 167286158228 ps
CPU time 102.14 seconds
Started May 07 03:25:48 PM PDT 24
Finished May 07 03:27:31 PM PDT 24
Peak memory 202312 kb
Host smart-21d5b668-2797-44ba-a909-587418388060
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660665620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2660665620
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3314655545
Short name T480
Test name
Test status
Simulation time 163712543372 ps
CPU time 36.68 seconds
Started May 07 03:25:42 PM PDT 24
Finished May 07 03:26:20 PM PDT 24
Peak memory 202320 kb
Host smart-61a0a4be-5f11-49d2-9b1a-83b28818d8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314655545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3314655545
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1389047601
Short name T658
Test name
Test status
Simulation time 325132933060 ps
CPU time 771.52 seconds
Started May 07 03:25:42 PM PDT 24
Finished May 07 03:38:34 PM PDT 24
Peak memory 202288 kb
Host smart-d4353c5c-3b64-4ab2-964e-2d64f2fb5a93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389047601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1389047601
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.657177490
Short name T282
Test name
Test status
Simulation time 169736822195 ps
CPU time 366.51 seconds
Started May 07 03:25:48 PM PDT 24
Finished May 07 03:31:55 PM PDT 24
Peak memory 202312 kb
Host smart-3934423e-af97-4686-a891-dc756bb4b222
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657177490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.657177490
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1852364775
Short name T416
Test name
Test status
Simulation time 203946896203 ps
CPU time 246.52 seconds
Started May 07 03:25:45 PM PDT 24
Finished May 07 03:29:53 PM PDT 24
Peak memory 202320 kb
Host smart-1425864f-636a-4aae-bdc7-58dcc74c5c87
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852364775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1852364775
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1506612102
Short name T726
Test name
Test status
Simulation time 132496398100 ps
CPU time 530.49 seconds
Started May 07 03:25:49 PM PDT 24
Finished May 07 03:34:40 PM PDT 24
Peak memory 202692 kb
Host smart-a8bebbef-9dd4-46c0-9c75-9dd2e1c321c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506612102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1506612102
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.545823130
Short name T414
Test name
Test status
Simulation time 30763562369 ps
CPU time 33.93 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:26:21 PM PDT 24
Peak memory 202148 kb
Host smart-4abf3df3-eb83-406b-a5e6-3842e09b3bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545823130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.545823130
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.534964272
Short name T373
Test name
Test status
Simulation time 3246409862 ps
CPU time 7.71 seconds
Started May 07 03:25:50 PM PDT 24
Finished May 07 03:25:59 PM PDT 24
Peak memory 202156 kb
Host smart-c55cbc69-6e92-4e44-b223-7cba43af29a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534964272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.534964272
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1597819102
Short name T692
Test name
Test status
Simulation time 5793345203 ps
CPU time 9.8 seconds
Started May 07 03:25:39 PM PDT 24
Finished May 07 03:25:50 PM PDT 24
Peak memory 202164 kb
Host smart-e4726e04-518f-4d38-ae1d-4b96b28a9a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597819102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1597819102
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.261390320
Short name T66
Test name
Test status
Simulation time 199774835087 ps
CPU time 133.43 seconds
Started May 07 03:25:51 PM PDT 24
Finished May 07 03:28:06 PM PDT 24
Peak memory 202476 kb
Host smart-c060a5ac-b1d6-40cf-9e8c-d87a388da1f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261390320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
261390320
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.4108768297
Short name T205
Test name
Test status
Simulation time 224212290996 ps
CPU time 489.79 seconds
Started May 07 03:25:51 PM PDT 24
Finished May 07 03:34:02 PM PDT 24
Peak memory 211168 kb
Host smart-42638926-daa4-441b-9efb-01005c573f13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108768297 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.4108768297
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1017678926
Short name T517
Test name
Test status
Simulation time 363121699 ps
CPU time 1 seconds
Started May 07 03:25:48 PM PDT 24
Finished May 07 03:25:50 PM PDT 24
Peak memory 202000 kb
Host smart-605323fe-c6a6-46d4-bd60-dbc747537f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017678926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1017678926
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2055129568
Short name T494
Test name
Test status
Simulation time 260492629810 ps
CPU time 43.39 seconds
Started May 07 03:25:47 PM PDT 24
Finished May 07 03:26:32 PM PDT 24
Peak memory 202304 kb
Host smart-37718c1a-38de-4f4b-89b4-ed6f051269fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055129568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2055129568
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1330764577
Short name T643
Test name
Test status
Simulation time 340302121743 ps
CPU time 160.28 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:28:27 PM PDT 24
Peak memory 202384 kb
Host smart-1a1a4702-7d28-4ac1-b2e6-dc006400e06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330764577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1330764577
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1375176111
Short name T302
Test name
Test status
Simulation time 484215280643 ps
CPU time 111.41 seconds
Started May 07 03:25:50 PM PDT 24
Finished May 07 03:27:43 PM PDT 24
Peak memory 202448 kb
Host smart-af05a88b-ff59-4d4b-86d7-dff0e6e5c7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375176111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1375176111
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1485114161
Short name T619
Test name
Test status
Simulation time 324728048434 ps
CPU time 745.18 seconds
Started May 07 03:25:48 PM PDT 24
Finished May 07 03:38:14 PM PDT 24
Peak memory 202276 kb
Host smart-edfdaee7-cf8e-4f54-9daf-9e1ca72d4706
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485114161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1485114161
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.674612033
Short name T319
Test name
Test status
Simulation time 162320412819 ps
CPU time 367.34 seconds
Started May 07 03:25:47 PM PDT 24
Finished May 07 03:31:56 PM PDT 24
Peak memory 202360 kb
Host smart-cd5a2b4f-4b2c-4a4b-a356-a6b50c09ba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674612033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.674612033
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.212292412
Short name T693
Test name
Test status
Simulation time 487913719724 ps
CPU time 1029.31 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:42:57 PM PDT 24
Peak memory 202332 kb
Host smart-5c41ed78-f195-4b9e-a3b8-0b1b71ba6415
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=212292412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.212292412
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1433280141
Short name T486
Test name
Test status
Simulation time 348984833728 ps
CPU time 198.39 seconds
Started May 07 03:25:49 PM PDT 24
Finished May 07 03:29:08 PM PDT 24
Peak memory 202428 kb
Host smart-fe31a283-e0ba-4937-9dab-53be9884d3c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433280141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1433280141
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.96197328
Short name T512
Test name
Test status
Simulation time 191727381076 ps
CPU time 115.77 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:27:43 PM PDT 24
Peak memory 202376 kb
Host smart-13fbf0e8-3b6f-402c-96e3-a34e2a09665d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96197328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.a
dc_ctrl_filters_wakeup_fixed.96197328
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1875336943
Short name T445
Test name
Test status
Simulation time 101674124070 ps
CPU time 344.11 seconds
Started May 07 03:25:51 PM PDT 24
Finished May 07 03:31:36 PM PDT 24
Peak memory 202776 kb
Host smart-71adbeb9-a47d-4dc5-9ace-3652a2a18d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875336943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1875336943
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.4168601125
Short name T566
Test name
Test status
Simulation time 47277707084 ps
CPU time 21.99 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:26:09 PM PDT 24
Peak memory 202140 kb
Host smart-1a232967-a2d4-40cd-9794-3f4937e9d388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168601125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.4168601125
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1059093466
Short name T707
Test name
Test status
Simulation time 4103077450 ps
CPU time 2.99 seconds
Started May 07 03:25:47 PM PDT 24
Finished May 07 03:25:51 PM PDT 24
Peak memory 202156 kb
Host smart-3d99024b-7f13-4264-81da-2166a339d14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059093466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1059093466
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2554628167
Short name T648
Test name
Test status
Simulation time 5834908064 ps
CPU time 13.57 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:26:01 PM PDT 24
Peak memory 202128 kb
Host smart-bba70e15-9a3b-410f-a8b2-f10eb5463862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554628167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2554628167
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.334856331
Short name T18
Test name
Test status
Simulation time 143044603910 ps
CPU time 68.02 seconds
Started May 07 03:25:51 PM PDT 24
Finished May 07 03:27:00 PM PDT 24
Peak memory 211168 kb
Host smart-57e00685-d41f-4f36-abf5-3d201de3ba05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334856331 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.334856331
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3597094659
Short name T529
Test name
Test status
Simulation time 292140282 ps
CPU time 1.04 seconds
Started May 07 03:25:54 PM PDT 24
Finished May 07 03:25:55 PM PDT 24
Peak memory 201484 kb
Host smart-74cdbf7c-26f7-4fbb-b0ae-6af1721c10ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597094659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3597094659
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3687146634
Short name T761
Test name
Test status
Simulation time 337759675182 ps
CPU time 470.18 seconds
Started May 07 03:25:45 PM PDT 24
Finished May 07 03:33:36 PM PDT 24
Peak memory 202320 kb
Host smart-f331b77f-8df8-47d2-8ae9-2b6fb2478d23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687146634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3687146634
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1310540421
Short name T229
Test name
Test status
Simulation time 356724636253 ps
CPU time 175.79 seconds
Started May 07 03:25:50 PM PDT 24
Finished May 07 03:28:47 PM PDT 24
Peak memory 202388 kb
Host smart-1ef786e2-dfac-494a-afbf-3ae1f16eac87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310540421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1310540421
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2315278502
Short name T261
Test name
Test status
Simulation time 160189084847 ps
CPU time 174.34 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:28:42 PM PDT 24
Peak memory 202388 kb
Host smart-ff811d68-3440-4047-a3ef-e041c72953d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315278502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2315278502
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1502629466
Short name T346
Test name
Test status
Simulation time 328489174239 ps
CPU time 209.14 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:29:16 PM PDT 24
Peak memory 202320 kb
Host smart-dba81832-1210-4345-b14c-c3720c8661f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502629466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1502629466
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2411944015
Short name T579
Test name
Test status
Simulation time 160650552304 ps
CPU time 25.91 seconds
Started May 07 03:25:50 PM PDT 24
Finished May 07 03:26:16 PM PDT 24
Peak memory 202348 kb
Host smart-411cc105-17e4-4bc4-94e2-7c909d4b24dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411944015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2411944015
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.271150268
Short name T434
Test name
Test status
Simulation time 330308400152 ps
CPU time 369.08 seconds
Started May 07 03:25:44 PM PDT 24
Finished May 07 03:31:54 PM PDT 24
Peak memory 202304 kb
Host smart-cec716b4-63d8-4663-b9a8-6bf42a90027b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=271150268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.271150268
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1744985208
Short name T305
Test name
Test status
Simulation time 346550764016 ps
CPU time 823.75 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:39:31 PM PDT 24
Peak memory 202384 kb
Host smart-1dd110a6-0f36-47cc-9e54-383bed8fa5b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744985208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1744985208
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3503242908
Short name T623
Test name
Test status
Simulation time 401894284705 ps
CPU time 538.77 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:34:46 PM PDT 24
Peak memory 202400 kb
Host smart-1ba24b08-9d27-48e5-95b4-b89a5e791208
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503242908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3503242908
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2105229224
Short name T43
Test name
Test status
Simulation time 86120087143 ps
CPU time 460.36 seconds
Started May 07 03:25:52 PM PDT 24
Finished May 07 03:33:33 PM PDT 24
Peak memory 202720 kb
Host smart-a71fabfa-914f-44eb-8481-69d3ca743c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105229224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2105229224
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1358078528
Short name T703
Test name
Test status
Simulation time 38559514901 ps
CPU time 6.64 seconds
Started May 07 03:25:50 PM PDT 24
Finished May 07 03:25:58 PM PDT 24
Peak memory 202112 kb
Host smart-46524921-1dda-422e-af66-8dbb4b1b3997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358078528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1358078528
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2863091918
Short name T724
Test name
Test status
Simulation time 4155877077 ps
CPU time 9.84 seconds
Started May 07 03:25:49 PM PDT 24
Finished May 07 03:26:00 PM PDT 24
Peak memory 202152 kb
Host smart-61d1753d-b917-40f7-ac58-02ad4e8af1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863091918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2863091918
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.835607396
Short name T130
Test name
Test status
Simulation time 5928963758 ps
CPU time 14.33 seconds
Started May 07 03:25:46 PM PDT 24
Finished May 07 03:26:02 PM PDT 24
Peak memory 202316 kb
Host smart-191bbfeb-aab8-4a83-a17f-9c3c27d15858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835607396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.835607396
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2437996414
Short name T293
Test name
Test status
Simulation time 232446033600 ps
CPU time 570.25 seconds
Started May 07 03:25:52 PM PDT 24
Finished May 07 03:35:23 PM PDT 24
Peak memory 202332 kb
Host smart-1b8bb0b2-8493-43d1-b6a0-f4ec412290d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437996414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2437996414
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2587839889
Short name T338
Test name
Test status
Simulation time 93970697020 ps
CPU time 105.2 seconds
Started May 07 03:25:51 PM PDT 24
Finished May 07 03:27:38 PM PDT 24
Peak memory 211000 kb
Host smart-01d32b19-ab67-4417-aa72-2a6d641fdb94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587839889 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2587839889
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.51623361
Short name T609
Test name
Test status
Simulation time 356176027 ps
CPU time 0.83 seconds
Started May 07 03:25:54 PM PDT 24
Finished May 07 03:25:56 PM PDT 24
Peak memory 201956 kb
Host smart-5b115605-468a-4cd7-b095-949e7048d5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51623361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.51623361
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3521123605
Short name T251
Test name
Test status
Simulation time 323847198172 ps
CPU time 799.5 seconds
Started May 07 03:25:52 PM PDT 24
Finished May 07 03:39:13 PM PDT 24
Peak memory 202376 kb
Host smart-4792cc5f-db77-4522-b53b-8bd0e4476c26
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521123605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3521123605
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3084517815
Short name T736
Test name
Test status
Simulation time 184106778269 ps
CPU time 461.37 seconds
Started May 07 03:25:51 PM PDT 24
Finished May 07 03:33:34 PM PDT 24
Peak memory 202328 kb
Host smart-fbb628ac-89b1-4c5a-932b-1c65d489f7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084517815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3084517815
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2741380456
Short name T598
Test name
Test status
Simulation time 163964910903 ps
CPU time 106.16 seconds
Started May 07 03:25:51 PM PDT 24
Finished May 07 03:27:38 PM PDT 24
Peak memory 202364 kb
Host smart-8b2b928d-cb5c-4ff6-8274-a4699d31714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741380456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2741380456
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1058477875
Short name T386
Test name
Test status
Simulation time 168738373766 ps
CPU time 108.51 seconds
Started May 07 03:25:52 PM PDT 24
Finished May 07 03:27:42 PM PDT 24
Peak memory 202284 kb
Host smart-d6a19368-7487-4a01-8032-e8ae7b638794
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058477875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1058477875
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2861973135
Short name T484
Test name
Test status
Simulation time 487587381296 ps
CPU time 1138.92 seconds
Started May 07 03:25:53 PM PDT 24
Finished May 07 03:44:53 PM PDT 24
Peak memory 202424 kb
Host smart-d8f104bd-3b18-4dbc-9d1f-b609d8d8fcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861973135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2861973135
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.8651795
Short name T443
Test name
Test status
Simulation time 161410336342 ps
CPU time 362.32 seconds
Started May 07 03:25:53 PM PDT 24
Finished May 07 03:31:56 PM PDT 24
Peak memory 202312 kb
Host smart-3709c323-cd7f-4ee3-ad1a-61092137e54c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=8651795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed.8651795
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.641196929
Short name T559
Test name
Test status
Simulation time 194996279412 ps
CPU time 410.71 seconds
Started May 07 03:25:52 PM PDT 24
Finished May 07 03:32:44 PM PDT 24
Peak memory 202400 kb
Host smart-f280d2b8-d3a6-4b4d-8a31-d8b2e1b80845
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641196929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.641196929
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2842701371
Short name T572
Test name
Test status
Simulation time 121482819177 ps
CPU time 387.85 seconds
Started May 07 03:25:54 PM PDT 24
Finished May 07 03:32:23 PM PDT 24
Peak memory 202696 kb
Host smart-17fb255a-99d4-45a9-8319-44bf5e6926c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842701371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2842701371
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.664410815
Short name T389
Test name
Test status
Simulation time 38340513798 ps
CPU time 48.5 seconds
Started May 07 03:25:51 PM PDT 24
Finished May 07 03:26:40 PM PDT 24
Peak memory 202168 kb
Host smart-ffdb5bb1-3778-45c9-8796-cbbc48d09d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664410815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.664410815
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.616603497
Short name T537
Test name
Test status
Simulation time 4343492083 ps
CPU time 11.24 seconds
Started May 07 03:25:52 PM PDT 24
Finished May 07 03:26:04 PM PDT 24
Peak memory 202140 kb
Host smart-0f183aae-89f5-4de8-a073-c27b7ae2b74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616603497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.616603497
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2112680267
Short name T410
Test name
Test status
Simulation time 5653046324 ps
CPU time 8.27 seconds
Started May 07 03:25:52 PM PDT 24
Finished May 07 03:26:02 PM PDT 24
Peak memory 202140 kb
Host smart-5bcf2c69-a5ca-4d35-b6de-a10de150a687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112680267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2112680267
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1003686380
Short name T180
Test name
Test status
Simulation time 223597316884 ps
CPU time 139.65 seconds
Started May 07 03:25:52 PM PDT 24
Finished May 07 03:28:13 PM PDT 24
Peak memory 202304 kb
Host smart-6c54d1e6-3214-48bb-8a3d-1ddd24443efb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003686380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1003686380
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1007366451
Short name T515
Test name
Test status
Simulation time 15822442755 ps
CPU time 44.6 seconds
Started May 07 03:25:54 PM PDT 24
Finished May 07 03:26:39 PM PDT 24
Peak memory 210936 kb
Host smart-bfe7cc0f-6573-49ad-8b10-c80fd721067b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007366451 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1007366451
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2287474269
Short name T92
Test name
Test status
Simulation time 504975533 ps
CPU time 1.19 seconds
Started May 07 03:25:58 PM PDT 24
Finished May 07 03:26:01 PM PDT 24
Peak memory 202024 kb
Host smart-efc89a37-1bd1-45dd-9963-12053618f0d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287474269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2287474269
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.1075246234
Short name T304
Test name
Test status
Simulation time 498773941603 ps
CPU time 584.85 seconds
Started May 07 03:25:57 PM PDT 24
Finished May 07 03:35:42 PM PDT 24
Peak memory 202396 kb
Host smart-20071c4d-3d15-4b0f-95bc-3b2c49d10e76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075246234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.1075246234
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.230527876
Short name T185
Test name
Test status
Simulation time 539970726782 ps
CPU time 288.52 seconds
Started May 07 03:25:59 PM PDT 24
Finished May 07 03:30:48 PM PDT 24
Peak memory 202336 kb
Host smart-7475053f-5f80-4c4f-b918-8ea9df827435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230527876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.230527876
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.192860047
Short name T220
Test name
Test status
Simulation time 164660359352 ps
CPU time 390.32 seconds
Started May 07 03:25:57 PM PDT 24
Finished May 07 03:32:28 PM PDT 24
Peak memory 202296 kb
Host smart-cb735273-34cb-45b7-83cf-236f41d7a8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192860047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.192860047
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.380569329
Short name T431
Test name
Test status
Simulation time 323474375582 ps
CPU time 770.46 seconds
Started May 07 03:25:57 PM PDT 24
Finished May 07 03:38:49 PM PDT 24
Peak memory 202292 kb
Host smart-88e05ba9-c790-442a-8fb4-d22a111c65f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=380569329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.380569329
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.701935577
Short name T285
Test name
Test status
Simulation time 163126742192 ps
CPU time 331.23 seconds
Started May 07 03:25:51 PM PDT 24
Finished May 07 03:31:23 PM PDT 24
Peak memory 202320 kb
Host smart-c792125c-c490-4289-9fcd-96b7c4db0e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701935577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.701935577
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.202774052
Short name T481
Test name
Test status
Simulation time 496156622788 ps
CPU time 959.2 seconds
Started May 07 03:25:58 PM PDT 24
Finished May 07 03:41:57 PM PDT 24
Peak memory 202324 kb
Host smart-038f625a-0ffe-4375-8e90-37983a7ad728
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=202774052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.202774052
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.576821903
Short name T624
Test name
Test status
Simulation time 419104381136 ps
CPU time 667.97 seconds
Started May 07 03:25:59 PM PDT 24
Finished May 07 03:37:08 PM PDT 24
Peak memory 202320 kb
Host smart-bbf94789-c1af-4ff2-8022-d648f7beaa02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576821903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.576821903
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2328314933
Short name T617
Test name
Test status
Simulation time 397707284015 ps
CPU time 491.81 seconds
Started May 07 03:25:58 PM PDT 24
Finished May 07 03:34:11 PM PDT 24
Peak memory 202312 kb
Host smart-fb2c458d-a605-4166-8808-dfc3189645b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328314933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2328314933
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3827353201
Short name T330
Test name
Test status
Simulation time 112956881427 ps
CPU time 362.11 seconds
Started May 07 03:25:57 PM PDT 24
Finished May 07 03:32:00 PM PDT 24
Peak memory 202724 kb
Host smart-d2d1b51a-d569-427c-be28-fb2e21086f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827353201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3827353201
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1379873359
Short name T366
Test name
Test status
Simulation time 46615280181 ps
CPU time 27.88 seconds
Started May 07 03:25:57 PM PDT 24
Finished May 07 03:26:25 PM PDT 24
Peak memory 202120 kb
Host smart-278e8bf9-fd7a-49bf-8562-cedc526803d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379873359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1379873359
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3992006159
Short name T360
Test name
Test status
Simulation time 4297260763 ps
CPU time 3.12 seconds
Started May 07 03:25:57 PM PDT 24
Finished May 07 03:26:01 PM PDT 24
Peak memory 202128 kb
Host smart-3d0efba9-546d-4f8f-86ce-28fc16b8aecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992006159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3992006159
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.494946788
Short name T584
Test name
Test status
Simulation time 5757011139 ps
CPU time 7.77 seconds
Started May 07 03:25:52 PM PDT 24
Finished May 07 03:26:01 PM PDT 24
Peak memory 202140 kb
Host smart-cc8b49a7-cb97-44e9-8854-54db703d3ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494946788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.494946788
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1712516904
Short name T372
Test name
Test status
Simulation time 48807138099 ps
CPU time 115.25 seconds
Started May 07 03:25:58 PM PDT 24
Finished May 07 03:27:55 PM PDT 24
Peak memory 202156 kb
Host smart-32792554-4ac5-4141-b48b-a617980c1505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712516904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1712516904
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.892751881
Short name T792
Test name
Test status
Simulation time 211746192456 ps
CPU time 187.25 seconds
Started May 07 03:25:58 PM PDT 24
Finished May 07 03:29:06 PM PDT 24
Peak memory 210980 kb
Host smart-3c1ef3e1-d9fb-4476-b55b-4064856f458f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892751881 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.892751881
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.459208054
Short name T101
Test name
Test status
Simulation time 475422070 ps
CPU time 0.78 seconds
Started May 07 03:26:02 PM PDT 24
Finished May 07 03:26:03 PM PDT 24
Peak memory 202032 kb
Host smart-b0c63594-6130-4269-9a2c-37761afe0a20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459208054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.459208054
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3693628165
Short name T763
Test name
Test status
Simulation time 167064566704 ps
CPU time 350.91 seconds
Started May 07 03:26:03 PM PDT 24
Finished May 07 03:31:55 PM PDT 24
Peak memory 202412 kb
Host smart-b297f3b8-a3fc-4844-a2ab-70f7986fc538
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693628165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3693628165
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1773826185
Short name T744
Test name
Test status
Simulation time 171331461192 ps
CPU time 378.37 seconds
Started May 07 03:26:05 PM PDT 24
Finished May 07 03:32:25 PM PDT 24
Peak memory 202336 kb
Host smart-ba455de1-9beb-442c-8f65-7dcbc5db1b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773826185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1773826185
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2661761163
Short name T281
Test name
Test status
Simulation time 322450875171 ps
CPU time 67.33 seconds
Started May 07 03:26:00 PM PDT 24
Finished May 07 03:27:08 PM PDT 24
Peak memory 202380 kb
Host smart-cfa7edc3-0594-483a-be71-20dd332afbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661761163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2661761163
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3136952239
Short name T349
Test name
Test status
Simulation time 165874309698 ps
CPU time 101 seconds
Started May 07 03:26:00 PM PDT 24
Finished May 07 03:27:42 PM PDT 24
Peak memory 202332 kb
Host smart-4d26570a-6ceb-48e5-b847-199d9d61a28d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136952239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3136952239
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3170903329
Short name T188
Test name
Test status
Simulation time 329695795734 ps
CPU time 123.19 seconds
Started May 07 03:25:57 PM PDT 24
Finished May 07 03:28:01 PM PDT 24
Peak memory 202312 kb
Host smart-ccf3f465-f3a5-4a9f-b26e-8c25bd71d36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170903329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3170903329
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1007210051
Short name T392
Test name
Test status
Simulation time 488605198393 ps
CPU time 1144.24 seconds
Started May 07 03:25:56 PM PDT 24
Finished May 07 03:45:01 PM PDT 24
Peak memory 202284 kb
Host smart-0e514f85-ae54-43e3-bd45-48a6f77b3723
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007210051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1007210051
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.586497917
Short name T470
Test name
Test status
Simulation time 600048018658 ps
CPU time 345 seconds
Started May 07 03:26:03 PM PDT 24
Finished May 07 03:31:48 PM PDT 24
Peak memory 202284 kb
Host smart-2d6d44ed-c57c-4d5d-880f-66d1c1b26a04
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586497917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.586497917
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2207639176
Short name T453
Test name
Test status
Simulation time 108268717040 ps
CPU time 401.01 seconds
Started May 07 03:26:04 PM PDT 24
Finished May 07 03:32:46 PM PDT 24
Peak memory 202752 kb
Host smart-4bef6353-d564-444d-9348-009651ca247a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207639176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2207639176
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3894638628
Short name T523
Test name
Test status
Simulation time 44212146482 ps
CPU time 112.35 seconds
Started May 07 03:26:03 PM PDT 24
Finished May 07 03:27:56 PM PDT 24
Peak memory 202132 kb
Host smart-487d8172-7e46-4d5c-9fb4-b46a2d2086f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894638628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3894638628
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2402768960
Short name T740
Test name
Test status
Simulation time 4872879478 ps
CPU time 6.58 seconds
Started May 07 03:26:05 PM PDT 24
Finished May 07 03:26:12 PM PDT 24
Peak memory 202152 kb
Host smart-1f99536a-ae53-4f9a-9e5b-26170e342ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402768960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2402768960
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1185571475
Short name T731
Test name
Test status
Simulation time 5919514637 ps
CPU time 9.05 seconds
Started May 07 03:25:58 PM PDT 24
Finished May 07 03:26:08 PM PDT 24
Peak memory 202148 kb
Host smart-1c2f482c-dd28-4edf-885b-31b08560a4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185571475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1185571475
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1626497528
Short name T36
Test name
Test status
Simulation time 14752917581 ps
CPU time 36.55 seconds
Started May 07 03:26:04 PM PDT 24
Finished May 07 03:26:42 PM PDT 24
Peak memory 202704 kb
Host smart-b77e5730-add7-45d4-a49d-cce1dac2e66e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626497528 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1626497528
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.767125115
Short name T784
Test name
Test status
Simulation time 470005659 ps
CPU time 1.79 seconds
Started May 07 03:26:09 PM PDT 24
Finished May 07 03:26:11 PM PDT 24
Peak memory 202024 kb
Host smart-c3680f61-a02b-471c-ad89-6d97fced788e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767125115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.767125115
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2065847347
Short name T294
Test name
Test status
Simulation time 620550903245 ps
CPU time 693.84 seconds
Started May 07 03:26:04 PM PDT 24
Finished May 07 03:37:39 PM PDT 24
Peak memory 202504 kb
Host smart-68655c4d-92de-4146-b5ba-6e0a8aded4dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065847347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2065847347
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.965583887
Short name T178
Test name
Test status
Simulation time 325613514617 ps
CPU time 175.77 seconds
Started May 07 03:26:01 PM PDT 24
Finished May 07 03:28:57 PM PDT 24
Peak memory 202304 kb
Host smart-a08943d3-acdc-49a7-ac40-4bbb0da3a0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965583887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.965583887
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3501438572
Short name T800
Test name
Test status
Simulation time 490748809877 ps
CPU time 297.43 seconds
Started May 07 03:26:06 PM PDT 24
Finished May 07 03:31:04 PM PDT 24
Peak memory 202268 kb
Host smart-2a55265e-737a-4aea-af16-a12fedaa3e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501438572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3501438572
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.726202703
Short name T100
Test name
Test status
Simulation time 500473280831 ps
CPU time 1174.71 seconds
Started May 07 03:26:02 PM PDT 24
Finished May 07 03:45:38 PM PDT 24
Peak memory 202328 kb
Host smart-4708cd39-cdba-49fe-8630-78d4d7da01fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=726202703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.726202703
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2356633871
Short name T513
Test name
Test status
Simulation time 329427576882 ps
CPU time 773.83 seconds
Started May 07 03:26:05 PM PDT 24
Finished May 07 03:39:00 PM PDT 24
Peak memory 202240 kb
Host smart-e676e8d6-21f7-4f0c-adb8-b19d0dfd3ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356633871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2356633871
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1026689892
Short name T574
Test name
Test status
Simulation time 164951057665 ps
CPU time 96.84 seconds
Started May 07 03:26:02 PM PDT 24
Finished May 07 03:27:40 PM PDT 24
Peak memory 202284 kb
Host smart-cd355b9c-f990-4793-8c96-48487581aa82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026689892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1026689892
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2534454098
Short name T705
Test name
Test status
Simulation time 373857543181 ps
CPU time 222.22 seconds
Started May 07 03:26:04 PM PDT 24
Finished May 07 03:29:48 PM PDT 24
Peak memory 202368 kb
Host smart-0cf575ca-4750-4c60-ace7-c756c612fd7b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534454098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2534454098
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.443905110
Short name T465
Test name
Test status
Simulation time 617268685904 ps
CPU time 1392.65 seconds
Started May 07 03:26:01 PM PDT 24
Finished May 07 03:49:15 PM PDT 24
Peak memory 202332 kb
Host smart-5b3c0637-e006-4d57-a715-d84cb7fb7ee0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443905110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.443905110
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3583853603
Short name T508
Test name
Test status
Simulation time 83805377597 ps
CPU time 417.11 seconds
Started May 07 03:26:02 PM PDT 24
Finished May 07 03:33:00 PM PDT 24
Peak memory 202668 kb
Host smart-c15b2c8e-21d7-4145-8cd8-c7fe2fa5708a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583853603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3583853603
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.232203814
Short name T556
Test name
Test status
Simulation time 38241337065 ps
CPU time 88.21 seconds
Started May 07 03:26:06 PM PDT 24
Finished May 07 03:27:35 PM PDT 24
Peak memory 202096 kb
Host smart-2da2ad6a-4087-43de-98c2-75a2c7356019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232203814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.232203814
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.839561277
Short name T343
Test name
Test status
Simulation time 3919049937 ps
CPU time 9.28 seconds
Started May 07 03:26:04 PM PDT 24
Finished May 07 03:26:15 PM PDT 24
Peak memory 202104 kb
Host smart-6bd3c064-36b2-49bb-a8fc-05fda03456bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839561277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.839561277
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.331291366
Short name T684
Test name
Test status
Simulation time 6154498896 ps
CPU time 15.46 seconds
Started May 07 03:26:04 PM PDT 24
Finished May 07 03:26:20 PM PDT 24
Peak memory 202196 kb
Host smart-7830206d-9ddf-4f6c-8c57-351850fff5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331291366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.331291366
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3419110212
Short name T290
Test name
Test status
Simulation time 363248439602 ps
CPU time 814.38 seconds
Started May 07 03:26:09 PM PDT 24
Finished May 07 03:39:45 PM PDT 24
Peak memory 202408 kb
Host smart-7f475d04-55a8-4b0f-ab5f-9531feea6e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419110212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3419110212
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3475733539
Short name T702
Test name
Test status
Simulation time 512159413091 ps
CPU time 628.76 seconds
Started May 07 03:26:04 PM PDT 24
Finished May 07 03:36:34 PM PDT 24
Peak memory 211020 kb
Host smart-a53a6173-ce2d-4288-a41f-bd01a7f815f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475733539 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3475733539
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3186737170
Short name T355
Test name
Test status
Simulation time 533915319 ps
CPU time 0.85 seconds
Started May 07 03:26:11 PM PDT 24
Finished May 07 03:26:13 PM PDT 24
Peak memory 202020 kb
Host smart-94f4ab6c-de70-428a-b7df-dcaddfdc7ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186737170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3186737170
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1950457061
Short name T758
Test name
Test status
Simulation time 336520507973 ps
CPU time 59.82 seconds
Started May 07 03:26:11 PM PDT 24
Finished May 07 03:27:12 PM PDT 24
Peak memory 202312 kb
Host smart-4252d908-ffbf-45e2-92ae-73ed14637271
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950457061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1950457061
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3805626823
Short name T280
Test name
Test status
Simulation time 183016467851 ps
CPU time 419.62 seconds
Started May 07 03:26:09 PM PDT 24
Finished May 07 03:33:10 PM PDT 24
Peak memory 202320 kb
Host smart-3b69e8ef-ebd4-4753-8f73-76958cdb2452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805626823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3805626823
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3294966101
Short name T528
Test name
Test status
Simulation time 165286631677 ps
CPU time 385.29 seconds
Started May 07 03:26:13 PM PDT 24
Finished May 07 03:32:39 PM PDT 24
Peak memory 202304 kb
Host smart-aac42acf-5612-4aa1-a4eb-1411815be5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294966101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3294966101
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1597368783
Short name T469
Test name
Test status
Simulation time 317757510650 ps
CPU time 702.3 seconds
Started May 07 03:26:07 PM PDT 24
Finished May 07 03:37:50 PM PDT 24
Peak memory 202320 kb
Host smart-c9bab0bf-dcc0-4549-99d8-799da6836387
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597368783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1597368783
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3572998909
Short name T697
Test name
Test status
Simulation time 497753755889 ps
CPU time 200.04 seconds
Started May 07 03:26:10 PM PDT 24
Finished May 07 03:29:31 PM PDT 24
Peak memory 202296 kb
Host smart-7e8942a0-bebb-4565-b805-c33d35c461f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572998909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3572998909
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1722616208
Short name T25
Test name
Test status
Simulation time 325790962503 ps
CPU time 139.23 seconds
Started May 07 03:26:11 PM PDT 24
Finished May 07 03:28:32 PM PDT 24
Peak memory 202288 kb
Host smart-aa890465-91fd-4fa1-b5ef-c7c24d39c802
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722616208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1722616208
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3352575404
Short name T549
Test name
Test status
Simulation time 250425928786 ps
CPU time 284.76 seconds
Started May 07 03:26:12 PM PDT 24
Finished May 07 03:30:57 PM PDT 24
Peak memory 202388 kb
Host smart-a3c60e04-33f3-4389-a407-100534c87ce8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352575404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3352575404
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2410978133
Short name T418
Test name
Test status
Simulation time 189123773823 ps
CPU time 418.13 seconds
Started May 07 03:26:11 PM PDT 24
Finished May 07 03:33:10 PM PDT 24
Peak memory 202264 kb
Host smart-f87db0ba-c54d-49e6-b228-7fd92859191e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410978133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2410978133
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1950672576
Short name T696
Test name
Test status
Simulation time 88174712691 ps
CPU time 326.61 seconds
Started May 07 03:26:10 PM PDT 24
Finished May 07 03:31:37 PM PDT 24
Peak memory 202692 kb
Host smart-8c5f637c-593c-4a45-b7aa-1b9a3a915d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950672576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1950672576
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2751215628
Short name T565
Test name
Test status
Simulation time 21261367506 ps
CPU time 13.29 seconds
Started May 07 03:26:11 PM PDT 24
Finished May 07 03:26:25 PM PDT 24
Peak memory 202168 kb
Host smart-002c42ae-aa46-47a2-8f5a-8de452b8805d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751215628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2751215628
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.4183544108
Short name T413
Test name
Test status
Simulation time 3072578308 ps
CPU time 7.86 seconds
Started May 07 03:26:11 PM PDT 24
Finished May 07 03:26:20 PM PDT 24
Peak memory 202156 kb
Host smart-9fb35284-a08d-4a6e-ab97-0adfe48720c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183544108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.4183544108
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.280457764
Short name T396
Test name
Test status
Simulation time 5941668617 ps
CPU time 7.08 seconds
Started May 07 03:26:10 PM PDT 24
Finished May 07 03:26:18 PM PDT 24
Peak memory 202140 kb
Host smart-fcf1ecc9-a618-44b8-8b50-db8f93775e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280457764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.280457764
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.196487572
Short name T535
Test name
Test status
Simulation time 63566941673 ps
CPU time 313.8 seconds
Started May 07 03:26:07 PM PDT 24
Finished May 07 03:31:22 PM PDT 24
Peak memory 202648 kb
Host smart-81853229-0dfe-4b82-8cba-740d3626aba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196487572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
196487572
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3892812220
Short name T17
Test name
Test status
Simulation time 135246593817 ps
CPU time 34.43 seconds
Started May 07 03:26:10 PM PDT 24
Finished May 07 03:26:46 PM PDT 24
Peak memory 211060 kb
Host smart-f3435ff6-1eb5-4d65-baef-6138c800c99b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892812220 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3892812220
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2867761773
Short name T363
Test name
Test status
Simulation time 370525701 ps
CPU time 1.03 seconds
Started May 07 03:26:16 PM PDT 24
Finished May 07 03:26:18 PM PDT 24
Peak memory 201972 kb
Host smart-9f26ebf9-ed19-4ecc-abe5-62a800444b6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867761773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2867761773
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.285618406
Short name T269
Test name
Test status
Simulation time 514398028101 ps
CPU time 1120.1 seconds
Started May 07 03:26:15 PM PDT 24
Finished May 07 03:44:56 PM PDT 24
Peak memory 202388 kb
Host smart-0b03827e-9198-4752-82ae-236b2ccac1f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285618406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.285618406
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2928419089
Short name T141
Test name
Test status
Simulation time 329191526964 ps
CPU time 781.21 seconds
Started May 07 03:26:13 PM PDT 24
Finished May 07 03:39:16 PM PDT 24
Peak memory 202392 kb
Host smart-ae573327-7ef8-44c3-a5de-675f7e6f5350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928419089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2928419089
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1175480911
Short name T419
Test name
Test status
Simulation time 162689933425 ps
CPU time 346.27 seconds
Started May 07 03:26:09 PM PDT 24
Finished May 07 03:31:56 PM PDT 24
Peak memory 202408 kb
Host smart-c41953cd-9a50-4741-82e7-e9170bb4ecc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175480911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1175480911
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2357601850
Short name T625
Test name
Test status
Simulation time 489602405044 ps
CPU time 1121.57 seconds
Started May 07 03:26:11 PM PDT 24
Finished May 07 03:44:53 PM PDT 24
Peak memory 202336 kb
Host smart-f15ad0d5-753d-42f4-bae6-532579206b22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357601850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2357601850
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2891504283
Short name T241
Test name
Test status
Simulation time 493440376997 ps
CPU time 1178.64 seconds
Started May 07 03:26:08 PM PDT 24
Finished May 07 03:45:47 PM PDT 24
Peak memory 202284 kb
Host smart-6e3bdf56-870e-4775-b90d-aaf1fd17663b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891504283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2891504283
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1117303530
Short name T2
Test name
Test status
Simulation time 168092655471 ps
CPU time 418.81 seconds
Started May 07 03:26:10 PM PDT 24
Finished May 07 03:33:09 PM PDT 24
Peak memory 202296 kb
Host smart-49eabf81-ec33-4483-832b-5d89e77635ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117303530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1117303530
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.228928079
Short name T665
Test name
Test status
Simulation time 188728710330 ps
CPU time 117.85 seconds
Started May 07 03:26:14 PM PDT 24
Finished May 07 03:28:13 PM PDT 24
Peak memory 202364 kb
Host smart-e2d59c28-db25-47b5-8b4f-917e1fab5465
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228928079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.228928079
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1454192887
Short name T627
Test name
Test status
Simulation time 192541820237 ps
CPU time 442.98 seconds
Started May 07 03:26:17 PM PDT 24
Finished May 07 03:33:41 PM PDT 24
Peak memory 202304 kb
Host smart-9ee49a13-289c-4446-ad1d-c08a66007b33
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454192887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1454192887
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1742810020
Short name T457
Test name
Test status
Simulation time 123349833943 ps
CPU time 345.5 seconds
Started May 07 03:26:14 PM PDT 24
Finished May 07 03:32:00 PM PDT 24
Peak memory 202732 kb
Host smart-24c49d47-3d55-4377-9ca9-614e588956eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742810020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1742810020
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2984172297
Short name T458
Test name
Test status
Simulation time 34231151806 ps
CPU time 20.67 seconds
Started May 07 03:26:15 PM PDT 24
Finished May 07 03:26:37 PM PDT 24
Peak memory 202140 kb
Host smart-d0c0474b-52b4-4417-b459-3dd9194a1c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984172297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2984172297
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3025489388
Short name T788
Test name
Test status
Simulation time 4155199812 ps
CPU time 9.59 seconds
Started May 07 03:26:14 PM PDT 24
Finished May 07 03:26:24 PM PDT 24
Peak memory 202148 kb
Host smart-c9b9226a-7d91-4319-9190-1b78d510a0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025489388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3025489388
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.4223081096
Short name T629
Test name
Test status
Simulation time 5611439444 ps
CPU time 4.23 seconds
Started May 07 03:26:11 PM PDT 24
Finished May 07 03:26:16 PM PDT 24
Peak memory 202152 kb
Host smart-04b6db90-5932-4dfc-a8cd-2588819d993d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223081096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.4223081096
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.906629578
Short name T316
Test name
Test status
Simulation time 199322217560 ps
CPU time 61.14 seconds
Started May 07 03:26:13 PM PDT 24
Finished May 07 03:27:15 PM PDT 24
Peak memory 202400 kb
Host smart-d13b33ce-7aa8-4a9e-83fd-fc12977c8dbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906629578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
906629578
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2223955471
Short name T496
Test name
Test status
Simulation time 107280126831 ps
CPU time 62.39 seconds
Started May 07 03:26:17 PM PDT 24
Finished May 07 03:27:21 PM PDT 24
Peak memory 210696 kb
Host smart-d9a87be9-6043-4902-a35b-38b821db6b3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223955471 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2223955471
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.276667263
Short name T424
Test name
Test status
Simulation time 321224086 ps
CPU time 0.81 seconds
Started May 07 03:26:22 PM PDT 24
Finished May 07 03:26:24 PM PDT 24
Peak memory 202004 kb
Host smart-fd84e64b-cd0a-418f-b633-f91678bde5a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276667263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.276667263
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3188395575
Short name T273
Test name
Test status
Simulation time 161729444983 ps
CPU time 187.87 seconds
Started May 07 03:26:15 PM PDT 24
Finished May 07 03:29:24 PM PDT 24
Peak memory 202320 kb
Host smart-cc617d9e-e760-4918-bc74-45f5175839d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188395575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3188395575
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.890185507
Short name T491
Test name
Test status
Simulation time 325298803297 ps
CPU time 394.6 seconds
Started May 07 03:26:16 PM PDT 24
Finished May 07 03:32:52 PM PDT 24
Peak memory 202252 kb
Host smart-2ffb5c43-876b-4aab-ae88-7de4398e562c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=890185507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.890185507
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3441592673
Short name T240
Test name
Test status
Simulation time 330274313674 ps
CPU time 280.43 seconds
Started May 07 03:26:15 PM PDT 24
Finished May 07 03:30:56 PM PDT 24
Peak memory 202384 kb
Host smart-80315703-2fdb-4984-98e8-07e152e9dfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441592673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3441592673
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3563029822
Short name T531
Test name
Test status
Simulation time 324617881760 ps
CPU time 184.31 seconds
Started May 07 03:26:16 PM PDT 24
Finished May 07 03:29:21 PM PDT 24
Peak memory 202244 kb
Host smart-9b214e84-b7b6-41dc-9850-98f99c79c73c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563029822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3563029822
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3650471592
Short name T312
Test name
Test status
Simulation time 349275535964 ps
CPU time 208.94 seconds
Started May 07 03:26:15 PM PDT 24
Finished May 07 03:29:45 PM PDT 24
Peak memory 202400 kb
Host smart-66bb77d2-000d-45b7-84c2-ac101152475f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650471592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3650471592
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2966185744
Short name T377
Test name
Test status
Simulation time 605607689295 ps
CPU time 145.13 seconds
Started May 07 03:26:13 PM PDT 24
Finished May 07 03:28:39 PM PDT 24
Peak memory 202312 kb
Host smart-c7bd681d-5e42-4a76-bbff-a4d18003fe46
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966185744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2966185744
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.350023396
Short name T421
Test name
Test status
Simulation time 133196104150 ps
CPU time 485.65 seconds
Started May 07 03:26:22 PM PDT 24
Finished May 07 03:34:29 PM PDT 24
Peak memory 202692 kb
Host smart-ae294984-4020-4e38-a4a4-1785eb74ed73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350023396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.350023396
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1756113514
Short name T429
Test name
Test status
Simulation time 42934227375 ps
CPU time 20.12 seconds
Started May 07 03:26:20 PM PDT 24
Finished May 07 03:26:42 PM PDT 24
Peak memory 202140 kb
Host smart-1b5f9621-14a0-4051-8a86-b1291bf9a8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756113514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1756113514
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1732290008
Short name T581
Test name
Test status
Simulation time 3274656134 ps
CPU time 2.39 seconds
Started May 07 03:26:24 PM PDT 24
Finished May 07 03:26:27 PM PDT 24
Peak memory 202128 kb
Host smart-41bfab5a-3da3-404c-83a1-d970489d15eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732290008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1732290008
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.268162571
Short name T449
Test name
Test status
Simulation time 5872676129 ps
CPU time 12.95 seconds
Started May 07 03:26:15 PM PDT 24
Finished May 07 03:26:29 PM PDT 24
Peak memory 202180 kb
Host smart-d4eadd3d-db28-44e1-8ac2-f17f4bee4901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268162571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.268162571
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2805073887
Short name T168
Test name
Test status
Simulation time 322139854859 ps
CPU time 204.77 seconds
Started May 07 03:26:21 PM PDT 24
Finished May 07 03:29:47 PM PDT 24
Peak memory 202296 kb
Host smart-1050040b-d206-4b24-9011-bf5312d1f3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805073887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2805073887
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1468391474
Short name T602
Test name
Test status
Simulation time 25221631781 ps
CPU time 57.31 seconds
Started May 07 03:26:23 PM PDT 24
Finished May 07 03:27:21 PM PDT 24
Peak memory 210612 kb
Host smart-6c6a08e9-21e0-4eb5-905f-46f02f6bb6b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468391474 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1468391474
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1928931062
Short name T381
Test name
Test status
Simulation time 486767890 ps
CPU time 1.73 seconds
Started May 07 03:25:03 PM PDT 24
Finished May 07 03:25:06 PM PDT 24
Peak memory 202000 kb
Host smart-f130091a-0b10-4242-aa9a-f8fabc74afcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928931062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1928931062
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3067780564
Short name T253
Test name
Test status
Simulation time 327809454435 ps
CPU time 729.4 seconds
Started May 07 03:24:56 PM PDT 24
Finished May 07 03:37:08 PM PDT 24
Peak memory 202328 kb
Host smart-84c0f666-6a37-489e-8b47-56339adeef4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067780564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3067780564
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2906571844
Short name T642
Test name
Test status
Simulation time 330031472106 ps
CPU time 188.83 seconds
Started May 07 03:25:03 PM PDT 24
Finished May 07 03:28:13 PM PDT 24
Peak memory 202320 kb
Host smart-c15d25ab-61dd-4722-bbdc-b2cdd8f7afef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906571844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2906571844
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2338840179
Short name T495
Test name
Test status
Simulation time 502654074488 ps
CPU time 642.42 seconds
Started May 07 03:25:05 PM PDT 24
Finished May 07 03:35:48 PM PDT 24
Peak memory 202260 kb
Host smart-4fc221d1-e978-44be-a977-d9ed055b1544
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338840179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2338840179
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2208155320
Short name T195
Test name
Test status
Simulation time 495385947364 ps
CPU time 263.27 seconds
Started May 07 03:24:58 PM PDT 24
Finished May 07 03:29:23 PM PDT 24
Peak memory 202332 kb
Host smart-a24614e2-0584-4cc0-8934-513e7e6a9feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208155320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2208155320
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3051762384
Short name T376
Test name
Test status
Simulation time 167625493117 ps
CPU time 64.01 seconds
Started May 07 03:24:56 PM PDT 24
Finished May 07 03:26:02 PM PDT 24
Peak memory 202324 kb
Host smart-65d620d0-000a-48a4-94fe-8c0b45e14fac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051762384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3051762384
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.4085565829
Short name T361
Test name
Test status
Simulation time 405915880312 ps
CPU time 1024.89 seconds
Started May 07 03:24:55 PM PDT 24
Finished May 07 03:42:02 PM PDT 24
Peak memory 202332 kb
Host smart-3eea39e4-faec-42a1-bf5f-2450fb37a464
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085565829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.4085565829
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1554556921
Short name T466
Test name
Test status
Simulation time 92450847557 ps
CPU time 488.72 seconds
Started May 07 03:24:58 PM PDT 24
Finished May 07 03:33:09 PM PDT 24
Peak memory 202700 kb
Host smart-ed22c340-feac-4c1f-888b-d8f65840b5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554556921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1554556921
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2495473525
Short name T405
Test name
Test status
Simulation time 45120409197 ps
CPU time 97.05 seconds
Started May 07 03:25:07 PM PDT 24
Finished May 07 03:26:45 PM PDT 24
Peak memory 202144 kb
Host smart-0782adac-9192-4fa3-80b3-c9bb8fba144e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495473525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2495473525
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2932641072
Short name T605
Test name
Test status
Simulation time 3092524691 ps
CPU time 2.26 seconds
Started May 07 03:25:00 PM PDT 24
Finished May 07 03:25:03 PM PDT 24
Peak memory 202124 kb
Host smart-4497469c-1287-4f78-aa11-a7b9353b72b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932641072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2932641072
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3215499514
Short name T56
Test name
Test status
Simulation time 8317353209 ps
CPU time 17.46 seconds
Started May 07 03:25:03 PM PDT 24
Finished May 07 03:25:22 PM PDT 24
Peak memory 218116 kb
Host smart-dddc8bee-ed01-46e6-b6ee-cbf501ff8165
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215499514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3215499514
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1164333359
Short name T393
Test name
Test status
Simulation time 5754325134 ps
CPU time 10.67 seconds
Started May 07 03:24:58 PM PDT 24
Finished May 07 03:25:11 PM PDT 24
Peak memory 202252 kb
Host smart-4bd30d6b-e0ef-48dd-b061-09f714aa1814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164333359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1164333359
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2691729813
Short name T15
Test name
Test status
Simulation time 334408503446 ps
CPU time 223.36 seconds
Started May 07 03:25:05 PM PDT 24
Finished May 07 03:28:50 PM PDT 24
Peak memory 211000 kb
Host smart-4be533ab-638d-49fe-988e-d2c7f713f3d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691729813 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2691729813
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.871708322
Short name T446
Test name
Test status
Simulation time 360171811 ps
CPU time 1.42 seconds
Started May 07 03:26:25 PM PDT 24
Finished May 07 03:26:27 PM PDT 24
Peak memory 201996 kb
Host smart-d7ac7ad3-687d-4fae-b37a-2410885d9767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871708322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.871708322
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.106600700
Short name T197
Test name
Test status
Simulation time 167415528714 ps
CPU time 384.09 seconds
Started May 07 03:26:22 PM PDT 24
Finished May 07 03:32:47 PM PDT 24
Peak memory 202492 kb
Host smart-8f9f9218-4330-4173-8c0c-e1fdb6384675
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106600700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.106600700
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2673421725
Short name T245
Test name
Test status
Simulation time 496824891087 ps
CPU time 1190.47 seconds
Started May 07 03:26:21 PM PDT 24
Finished May 07 03:46:12 PM PDT 24
Peak memory 202328 kb
Host smart-18d19ced-99d7-402b-8054-57beb1aaa91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673421725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2673421725
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.678856773
Short name T547
Test name
Test status
Simulation time 329107777001 ps
CPU time 220.62 seconds
Started May 07 03:26:23 PM PDT 24
Finished May 07 03:30:04 PM PDT 24
Peak memory 202320 kb
Host smart-6d35b746-ff38-47f7-9b61-c072460de29a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=678856773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.678856773
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1231534897
Short name T351
Test name
Test status
Simulation time 328346790063 ps
CPU time 388.48 seconds
Started May 07 03:26:22 PM PDT 24
Finished May 07 03:32:51 PM PDT 24
Peak memory 202348 kb
Host smart-5ec35918-7fde-4fe4-ace0-3434c0533a04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231534897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1231534897
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1955511148
Short name T303
Test name
Test status
Simulation time 192387991868 ps
CPU time 213.28 seconds
Started May 07 03:26:22 PM PDT 24
Finished May 07 03:29:56 PM PDT 24
Peak memory 202400 kb
Host smart-ad8cd711-8b26-4d68-87d3-1be608b6c70c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955511148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1955511148
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1351629324
Short name T567
Test name
Test status
Simulation time 609455196772 ps
CPU time 247.82 seconds
Started May 07 03:26:21 PM PDT 24
Finished May 07 03:30:30 PM PDT 24
Peak memory 202304 kb
Host smart-c5b5f1f7-6e02-46c0-ab10-9d05ab5bc2b0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351629324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1351629324
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2361415092
Short name T336
Test name
Test status
Simulation time 97849547551 ps
CPU time 305.44 seconds
Started May 07 03:26:23 PM PDT 24
Finished May 07 03:31:29 PM PDT 24
Peak memory 202736 kb
Host smart-bb816e43-8196-44ee-bf83-33b51cc0a9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361415092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2361415092
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1364545175
Short name T383
Test name
Test status
Simulation time 39400886937 ps
CPU time 44.03 seconds
Started May 07 03:26:20 PM PDT 24
Finished May 07 03:27:05 PM PDT 24
Peak memory 202160 kb
Host smart-0462e615-8a68-44ad-bb10-0cd97a2d9c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364545175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1364545175
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2392130969
Short name T578
Test name
Test status
Simulation time 5434823593 ps
CPU time 8.03 seconds
Started May 07 03:26:23 PM PDT 24
Finished May 07 03:26:32 PM PDT 24
Peak memory 202132 kb
Host smart-be84eab2-f309-4b7e-b93d-93479b4fdaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392130969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2392130969
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.210894866
Short name T727
Test name
Test status
Simulation time 5888374507 ps
CPU time 4.43 seconds
Started May 07 03:26:23 PM PDT 24
Finished May 07 03:26:28 PM PDT 24
Peak memory 202144 kb
Host smart-3ad2ddc6-746d-4d9a-8ac9-f99d9ab57066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210894866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.210894866
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1241838104
Short name T794
Test name
Test status
Simulation time 461787297 ps
CPU time 1.67 seconds
Started May 07 03:26:27 PM PDT 24
Finished May 07 03:26:30 PM PDT 24
Peak memory 202024 kb
Host smart-b442c187-1127-4351-a7bc-0e636c71f8ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241838104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1241838104
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3239822182
Short name T560
Test name
Test status
Simulation time 338050920877 ps
CPU time 180.5 seconds
Started May 07 03:26:26 PM PDT 24
Finished May 07 03:29:28 PM PDT 24
Peak memory 202320 kb
Host smart-9a574f70-7e10-43ec-a1e4-1bd6c950486c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239822182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3239822182
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.4190764825
Short name T222
Test name
Test status
Simulation time 328585426310 ps
CPU time 723.55 seconds
Started May 07 03:26:27 PM PDT 24
Finished May 07 03:38:32 PM PDT 24
Peak memory 202320 kb
Host smart-baafe309-c818-4906-ba0d-ca6add1751f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190764825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.4190764825
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.684444266
Short name T439
Test name
Test status
Simulation time 160289880497 ps
CPU time 193.36 seconds
Started May 07 03:26:27 PM PDT 24
Finished May 07 03:29:41 PM PDT 24
Peak memory 202280 kb
Host smart-03c18c2c-0155-4bfc-bd4a-5a387e1b4921
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=684444266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.684444266
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2605504922
Short name T283
Test name
Test status
Simulation time 318308492380 ps
CPU time 205.86 seconds
Started May 07 03:26:25 PM PDT 24
Finished May 07 03:29:52 PM PDT 24
Peak memory 202392 kb
Host smart-d199cc98-1c61-4423-bd79-33a19ce2bd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605504922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2605504922
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1187546579
Short name T552
Test name
Test status
Simulation time 162993751717 ps
CPU time 103.03 seconds
Started May 07 03:26:26 PM PDT 24
Finished May 07 03:28:10 PM PDT 24
Peak memory 202300 kb
Host smart-0e2ec71b-0041-4028-ae1e-6049148f0243
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187546579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1187546579
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2755722024
Short name T287
Test name
Test status
Simulation time 172523103335 ps
CPU time 397.87 seconds
Started May 07 03:26:27 PM PDT 24
Finished May 07 03:33:06 PM PDT 24
Peak memory 202324 kb
Host smart-8ddb71ae-d226-4824-ad68-ffd28ba7f99d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755722024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2755722024
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.181127481
Short name T519
Test name
Test status
Simulation time 191933211465 ps
CPU time 441.79 seconds
Started May 07 03:26:24 PM PDT 24
Finished May 07 03:33:47 PM PDT 24
Peak memory 202408 kb
Host smart-ea700a53-96e5-49fa-845a-497deee54dd1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181127481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.181127481
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3298613454
Short name T647
Test name
Test status
Simulation time 73749938044 ps
CPU time 323.13 seconds
Started May 07 03:26:26 PM PDT 24
Finished May 07 03:31:51 PM PDT 24
Peak memory 202752 kb
Host smart-96eeef43-43b9-4c21-86fd-6a3a6768572e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298613454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3298613454
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2349991174
Short name T716
Test name
Test status
Simulation time 40409005465 ps
CPU time 95.68 seconds
Started May 07 03:26:25 PM PDT 24
Finished May 07 03:28:02 PM PDT 24
Peak memory 202156 kb
Host smart-6c527601-3497-448a-bb69-f6a39cbb3921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349991174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2349991174
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1325356916
Short name T640
Test name
Test status
Simulation time 5409994610 ps
CPU time 7.28 seconds
Started May 07 03:26:26 PM PDT 24
Finished May 07 03:26:34 PM PDT 24
Peak memory 202140 kb
Host smart-d8813464-3a08-4a23-8ae5-3679e21ac8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325356916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1325356916
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1355979296
Short name T671
Test name
Test status
Simulation time 5692870801 ps
CPU time 4.42 seconds
Started May 07 03:26:25 PM PDT 24
Finished May 07 03:26:31 PM PDT 24
Peak memory 202144 kb
Host smart-aaa5ac31-40f7-4426-af8f-bb0aedceffb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355979296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1355979296
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.84221546
Short name T759
Test name
Test status
Simulation time 487670419271 ps
CPU time 1524.98 seconds
Started May 07 03:26:25 PM PDT 24
Finished May 07 03:51:52 PM PDT 24
Peak memory 213168 kb
Host smart-03659f4c-c747-4e9a-98df-04fd17e2cc5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84221546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.84221546
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1672010110
Short name T41
Test name
Test status
Simulation time 19775661755 ps
CPU time 45.63 seconds
Started May 07 03:26:27 PM PDT 24
Finished May 07 03:27:14 PM PDT 24
Peak memory 212128 kb
Host smart-552f14f6-a551-4a07-9b9b-5cef11b03a1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672010110 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1672010110
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1581635502
Short name T773
Test name
Test status
Simulation time 294029348 ps
CPU time 1.45 seconds
Started May 07 03:26:32 PM PDT 24
Finished May 07 03:26:34 PM PDT 24
Peak memory 202024 kb
Host smart-430e3a19-4027-4080-b3a4-e747d21c6b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581635502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1581635502
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1491726650
Short name T544
Test name
Test status
Simulation time 492082393681 ps
CPU time 1166.71 seconds
Started May 07 03:26:33 PM PDT 24
Finished May 07 03:46:01 PM PDT 24
Peak memory 202300 kb
Host smart-cd5b2904-dd51-4e7e-8582-0d1592eaaeb3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491726650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1491726650
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.469011183
Short name T455
Test name
Test status
Simulation time 332836570071 ps
CPU time 198.17 seconds
Started May 07 03:26:25 PM PDT 24
Finished May 07 03:29:45 PM PDT 24
Peak memory 202428 kb
Host smart-9e6ea041-8fac-4d23-ad05-e467788f8434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469011183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.469011183
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.875481955
Short name T164
Test name
Test status
Simulation time 170218295611 ps
CPU time 101.83 seconds
Started May 07 03:26:26 PM PDT 24
Finished May 07 03:28:09 PM PDT 24
Peak memory 202328 kb
Host smart-34933609-dcc1-4d30-b899-0d69e49da487
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=875481955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.875481955
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2079371682
Short name T239
Test name
Test status
Simulation time 525772391632 ps
CPU time 576.3 seconds
Started May 07 03:26:33 PM PDT 24
Finished May 07 03:36:10 PM PDT 24
Peak memory 202320 kb
Host smart-23153455-4c4f-4eb1-841d-322e45450025
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079371682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2079371682
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2231322243
Short name T411
Test name
Test status
Simulation time 409958304582 ps
CPU time 1045.65 seconds
Started May 07 03:26:32 PM PDT 24
Finished May 07 03:43:59 PM PDT 24
Peak memory 202332 kb
Host smart-ec19ddd9-e1d7-4718-bf95-99dd2c0228ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231322243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2231322243
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2544727222
Short name T756
Test name
Test status
Simulation time 120104559031 ps
CPU time 506.92 seconds
Started May 07 03:26:32 PM PDT 24
Finished May 07 03:35:00 PM PDT 24
Peak memory 202688 kb
Host smart-6b307c18-537d-4674-8009-202f84ae9e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544727222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2544727222
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2941193547
Short name T408
Test name
Test status
Simulation time 43558394786 ps
CPU time 101.99 seconds
Started May 07 03:26:33 PM PDT 24
Finished May 07 03:28:16 PM PDT 24
Peak memory 202160 kb
Host smart-5f7bc45f-e84a-475a-816d-c099583f12c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941193547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2941193547
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1732058353
Short name T391
Test name
Test status
Simulation time 4337329129 ps
CPU time 3.23 seconds
Started May 07 03:26:34 PM PDT 24
Finished May 07 03:26:38 PM PDT 24
Peak memory 202140 kb
Host smart-3daa5f5e-7004-4b79-9aae-4459cbb9060b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732058353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1732058353
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2167777768
Short name T497
Test name
Test status
Simulation time 5748418589 ps
CPU time 6.49 seconds
Started May 07 03:26:27 PM PDT 24
Finished May 07 03:26:35 PM PDT 24
Peak memory 202108 kb
Host smart-53ec9bfa-2b3f-404a-80f4-6d5dc8e025ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167777768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2167777768
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1586267362
Short name T364
Test name
Test status
Simulation time 14737916599 ps
CPU time 18.63 seconds
Started May 07 03:26:38 PM PDT 24
Finished May 07 03:26:59 PM PDT 24
Peak memory 202188 kb
Host smart-7164aaeb-5e8a-4e09-930b-6fa32eea5533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586267362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1586267362
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3597051938
Short name T795
Test name
Test status
Simulation time 22165312624 ps
CPU time 52.48 seconds
Started May 07 03:26:32 PM PDT 24
Finished May 07 03:27:25 PM PDT 24
Peak memory 202396 kb
Host smart-faff661c-5758-4e3d-b84a-3de954095312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597051938 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3597051938
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1236237618
Short name T785
Test name
Test status
Simulation time 352983992 ps
CPU time 0.79 seconds
Started May 07 03:26:38 PM PDT 24
Finished May 07 03:26:41 PM PDT 24
Peak memory 202024 kb
Host smart-fac0369c-92c7-43e6-b8a2-c6423d68e5e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236237618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1236237618
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3225682148
Short name T775
Test name
Test status
Simulation time 198931814860 ps
CPU time 120.08 seconds
Started May 07 03:26:37 PM PDT 24
Finished May 07 03:28:39 PM PDT 24
Peak memory 202340 kb
Host smart-f8db4e68-642c-4b98-b076-cf98116fdc76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225682148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3225682148
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.355514808
Short name T250
Test name
Test status
Simulation time 491784919031 ps
CPU time 276.01 seconds
Started May 07 03:26:34 PM PDT 24
Finished May 07 03:31:11 PM PDT 24
Peak memory 202320 kb
Host smart-b7b63a9d-2afa-4af9-91e9-03fab53b8bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355514808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.355514808
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3679986257
Short name T656
Test name
Test status
Simulation time 162727527822 ps
CPU time 95.4 seconds
Started May 07 03:26:37 PM PDT 24
Finished May 07 03:28:14 PM PDT 24
Peak memory 202472 kb
Host smart-70467146-e998-442e-a2e2-5d281f5928d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679986257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3679986257
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2692326313
Short name T151
Test name
Test status
Simulation time 326501854322 ps
CPU time 362.91 seconds
Started May 07 03:26:31 PM PDT 24
Finished May 07 03:32:35 PM PDT 24
Peak memory 201860 kb
Host smart-e1f8797e-6704-4f8e-8f99-8ab7d6e6ac29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692326313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2692326313
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2704455401
Short name T670
Test name
Test status
Simulation time 483915290587 ps
CPU time 265.79 seconds
Started May 07 03:26:34 PM PDT 24
Finished May 07 03:31:01 PM PDT 24
Peak memory 202236 kb
Host smart-804af611-815b-4e10-8452-996f560e1028
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704455401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2704455401
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3030285062
Short name T270
Test name
Test status
Simulation time 356757670475 ps
CPU time 220.93 seconds
Started May 07 03:26:35 PM PDT 24
Finished May 07 03:30:18 PM PDT 24
Peak memory 202304 kb
Host smart-e77657f7-14a3-43d7-be01-16a0c04e5fec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030285062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3030285062
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1955319464
Short name T402
Test name
Test status
Simulation time 603205613577 ps
CPU time 215.1 seconds
Started May 07 03:26:37 PM PDT 24
Finished May 07 03:30:14 PM PDT 24
Peak memory 202320 kb
Host smart-f15fd914-206e-4517-97bc-f2f38411da6c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955319464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1955319464
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.776042521
Short name T746
Test name
Test status
Simulation time 140029623864 ps
CPU time 545.04 seconds
Started May 07 03:26:37 PM PDT 24
Finished May 07 03:35:44 PM PDT 24
Peak memory 202660 kb
Host smart-87f411df-801b-47dd-b543-2ec4fa8ef447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776042521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.776042521
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2152974108
Short name T666
Test name
Test status
Simulation time 34715780324 ps
CPU time 33.55 seconds
Started May 07 03:26:36 PM PDT 24
Finished May 07 03:27:11 PM PDT 24
Peak memory 202128 kb
Host smart-923f3656-6193-474a-8985-f08fad10ea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152974108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2152974108
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3064252093
Short name T78
Test name
Test status
Simulation time 4315085719 ps
CPU time 4.38 seconds
Started May 07 03:26:36 PM PDT 24
Finished May 07 03:26:43 PM PDT 24
Peak memory 202132 kb
Host smart-cc9fea77-318b-4ea3-a505-50bd4baafc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064252093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3064252093
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3930388864
Short name T675
Test name
Test status
Simulation time 5770266009 ps
CPU time 1.63 seconds
Started May 07 03:26:30 PM PDT 24
Finished May 07 03:26:33 PM PDT 24
Peak memory 202156 kb
Host smart-ffe8abd0-8993-400c-bd3b-e10a691b3251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930388864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3930388864
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1836690704
Short name T753
Test name
Test status
Simulation time 557958346797 ps
CPU time 831.16 seconds
Started May 07 03:26:35 PM PDT 24
Finished May 07 03:40:28 PM PDT 24
Peak memory 210864 kb
Host smart-0b3a3056-0de1-47c5-920c-d61a9ee1509a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836690704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1836690704
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2608843359
Short name T23
Test name
Test status
Simulation time 351227822527 ps
CPU time 380.88 seconds
Started May 07 03:26:37 PM PDT 24
Finished May 07 03:33:00 PM PDT 24
Peak memory 211144 kb
Host smart-65436d43-fe57-45ea-9a8c-0289a2faa260
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608843359 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2608843359
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1395707643
Short name T686
Test name
Test status
Simulation time 394575663 ps
CPU time 0.83 seconds
Started May 07 03:26:43 PM PDT 24
Finished May 07 03:26:45 PM PDT 24
Peak memory 202032 kb
Host smart-8f400f99-3547-4b62-817c-b0499cc6c21e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395707643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1395707643
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.778774918
Short name T576
Test name
Test status
Simulation time 527148605006 ps
CPU time 300.74 seconds
Started May 07 03:26:35 PM PDT 24
Finished May 07 03:31:38 PM PDT 24
Peak memory 202344 kb
Host smart-b84db51a-5517-4df1-bbd4-2e2f75f70eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778774918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.778774918
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.4084506737
Short name T191
Test name
Test status
Simulation time 162004231398 ps
CPU time 86.75 seconds
Started May 07 03:26:39 PM PDT 24
Finished May 07 03:28:07 PM PDT 24
Peak memory 202264 kb
Host smart-1a87cd1e-27a7-4abf-ab4e-5583c3c87611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084506737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.4084506737
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2911383499
Short name T604
Test name
Test status
Simulation time 488103124263 ps
CPU time 1177.23 seconds
Started May 07 03:26:37 PM PDT 24
Finished May 07 03:46:16 PM PDT 24
Peak memory 202328 kb
Host smart-f698c185-096b-4660-991b-06c5b3534f98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911383499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2911383499
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1160539939
Short name T150
Test name
Test status
Simulation time 162783210225 ps
CPU time 63.58 seconds
Started May 07 03:26:39 PM PDT 24
Finished May 07 03:27:45 PM PDT 24
Peak memory 202304 kb
Host smart-9fed7655-94d4-4c6a-b2db-daa4108e4869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160539939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1160539939
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3660841634
Short name T24
Test name
Test status
Simulation time 485006478626 ps
CPU time 291.7 seconds
Started May 07 03:26:37 PM PDT 24
Finished May 07 03:31:31 PM PDT 24
Peak memory 202292 kb
Host smart-9f478c57-5810-4887-b8ee-ede4c444c07c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660841634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3660841634
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3481387316
Short name T700
Test name
Test status
Simulation time 349051002275 ps
CPU time 818.24 seconds
Started May 07 03:26:36 PM PDT 24
Finished May 07 03:40:16 PM PDT 24
Peak memory 202332 kb
Host smart-e269b30c-ae31-43de-a196-b2f203627316
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481387316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3481387316
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2762369544
Short name T711
Test name
Test status
Simulation time 376567277861 ps
CPU time 421.75 seconds
Started May 07 03:26:41 PM PDT 24
Finished May 07 03:33:44 PM PDT 24
Peak memory 202340 kb
Host smart-6de78ab6-03b6-4685-bb8f-0db999949b90
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762369544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2762369544
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2824213961
Short name T337
Test name
Test status
Simulation time 76152586265 ps
CPU time 262.47 seconds
Started May 07 03:26:44 PM PDT 24
Finished May 07 03:31:07 PM PDT 24
Peak memory 202676 kb
Host smart-a266702c-8425-4e47-8a50-5dd99ec8b748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824213961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2824213961
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3183637261
Short name T733
Test name
Test status
Simulation time 42434938142 ps
CPU time 80.46 seconds
Started May 07 03:26:44 PM PDT 24
Finished May 07 03:28:05 PM PDT 24
Peak memory 202128 kb
Host smart-510baebe-6205-4038-aa91-6d394967aad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183637261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3183637261
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3571531494
Short name T500
Test name
Test status
Simulation time 4108855455 ps
CPU time 11.18 seconds
Started May 07 03:26:38 PM PDT 24
Finished May 07 03:26:52 PM PDT 24
Peak memory 202164 kb
Host smart-95fad781-e6e0-4276-a4c5-908ca7b0ed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571531494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3571531494
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1328228648
Short name T395
Test name
Test status
Simulation time 6027427027 ps
CPU time 14.52 seconds
Started May 07 03:26:36 PM PDT 24
Finished May 07 03:26:52 PM PDT 24
Peak memory 202164 kb
Host smart-6d1753cd-d3c5-4d6f-b8d8-d4051c67258f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328228648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1328228648
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1970535439
Short name T760
Test name
Test status
Simulation time 335938258590 ps
CPU time 394.43 seconds
Started May 07 03:26:44 PM PDT 24
Finished May 07 03:33:19 PM PDT 24
Peak memory 202308 kb
Host smart-6864a059-819b-4727-ad25-fdd261b0da18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970535439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1970535439
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1994031651
Short name T74
Test name
Test status
Simulation time 355951815 ps
CPU time 1.33 seconds
Started May 07 03:26:49 PM PDT 24
Finished May 07 03:26:51 PM PDT 24
Peak memory 201996 kb
Host smart-f124eaf5-5590-4f11-876b-c83c4319d2a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994031651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1994031651
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2215477772
Short name T613
Test name
Test status
Simulation time 177736076515 ps
CPU time 221.67 seconds
Started May 07 03:26:44 PM PDT 24
Finished May 07 03:30:27 PM PDT 24
Peak memory 202308 kb
Host smart-158b4519-3607-49f1-8843-ed7313ece560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215477772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2215477772
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3572727774
Short name T160
Test name
Test status
Simulation time 324372114196 ps
CPU time 82.81 seconds
Started May 07 03:26:44 PM PDT 24
Finished May 07 03:28:08 PM PDT 24
Peak memory 202412 kb
Host smart-941e2196-5405-45fe-9192-e0ff63a518f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572727774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3572727774
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2976977336
Short name T79
Test name
Test status
Simulation time 330365779063 ps
CPU time 183.45 seconds
Started May 07 03:26:44 PM PDT 24
Finished May 07 03:29:49 PM PDT 24
Peak memory 202328 kb
Host smart-eb028fb0-d843-4225-9982-943e55664c5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976977336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2976977336
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2884346193
Short name T689
Test name
Test status
Simulation time 327264928810 ps
CPU time 192.13 seconds
Started May 07 03:26:44 PM PDT 24
Finished May 07 03:29:57 PM PDT 24
Peak memory 202392 kb
Host smart-6c4ff011-3b33-4562-956e-4c1f16c2c0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884346193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2884346193
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2671035906
Short name T615
Test name
Test status
Simulation time 159981429249 ps
CPU time 64.19 seconds
Started May 07 03:26:42 PM PDT 24
Finished May 07 03:27:48 PM PDT 24
Peak memory 202292 kb
Host smart-de64d113-6195-41a0-9394-bd39effd6b2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671035906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2671035906
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2848216070
Short name T790
Test name
Test status
Simulation time 567564379590 ps
CPU time 570.98 seconds
Started May 07 03:26:46 PM PDT 24
Finished May 07 03:36:18 PM PDT 24
Peak memory 202308 kb
Host smart-78f7beeb-88cc-4ee5-955a-5d33390df753
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848216070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2848216070
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1585548998
Short name T492
Test name
Test status
Simulation time 593265975936 ps
CPU time 1454.48 seconds
Started May 07 03:26:45 PM PDT 24
Finished May 07 03:51:01 PM PDT 24
Peak memory 202316 kb
Host smart-9a80c835-69a7-43b8-a079-3dedc81afd14
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585548998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1585548998
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2049944821
Short name T209
Test name
Test status
Simulation time 137195541634 ps
CPU time 694.83 seconds
Started May 07 03:26:49 PM PDT 24
Finished May 07 03:38:24 PM PDT 24
Peak memory 202712 kb
Host smart-7db1dbcc-2dea-4954-a48a-ea00d2a50f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049944821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2049944821
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3919272177
Short name T407
Test name
Test status
Simulation time 42224569773 ps
CPU time 108.23 seconds
Started May 07 03:26:52 PM PDT 24
Finished May 07 03:28:41 PM PDT 24
Peak memory 202124 kb
Host smart-d7554e7b-7cd7-40a9-b437-6a13bb43b6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919272177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3919272177
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.4189853491
Short name T86
Test name
Test status
Simulation time 5049489341 ps
CPU time 12.39 seconds
Started May 07 03:26:52 PM PDT 24
Finished May 07 03:27:05 PM PDT 24
Peak memory 202132 kb
Host smart-2aeac913-772b-43c4-9367-8d3d08a976d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189853491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.4189853491
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3892631770
Short name T798
Test name
Test status
Simulation time 6000427810 ps
CPU time 15.09 seconds
Started May 07 03:26:43 PM PDT 24
Finished May 07 03:26:59 PM PDT 24
Peak memory 202156 kb
Host smart-98aafedd-08e5-48c3-96aa-428e6c54309b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892631770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3892631770
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2716989698
Short name T632
Test name
Test status
Simulation time 236535975432 ps
CPU time 126.11 seconds
Started May 07 03:26:48 PM PDT 24
Finished May 07 03:28:55 PM PDT 24
Peak memory 202316 kb
Host smart-0d3b7884-14b2-4a2a-9ca7-6007d21cadde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716989698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2716989698
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.4037197416
Short name T765
Test name
Test status
Simulation time 436085454 ps
CPU time 0.91 seconds
Started May 07 03:26:59 PM PDT 24
Finished May 07 03:27:01 PM PDT 24
Peak memory 201948 kb
Host smart-e9e94bde-31a9-4507-85d5-c28f665855d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037197416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.4037197416
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1922045970
Short name T777
Test name
Test status
Simulation time 159106064586 ps
CPU time 338.65 seconds
Started May 07 03:26:46 PM PDT 24
Finished May 07 03:32:26 PM PDT 24
Peak memory 202332 kb
Host smart-5a6187be-dbe4-45da-a809-57f5ee381a27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922045970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1922045970
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3272274882
Short name T723
Test name
Test status
Simulation time 491106972406 ps
CPU time 1137.99 seconds
Started May 07 03:26:47 PM PDT 24
Finished May 07 03:45:46 PM PDT 24
Peak memory 202336 kb
Host smart-cd9b5c2a-915c-4eb3-ba26-9ed6a85c3d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272274882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3272274882
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1102909390
Short name T379
Test name
Test status
Simulation time 164837809759 ps
CPU time 111.32 seconds
Started May 07 03:26:48 PM PDT 24
Finished May 07 03:28:40 PM PDT 24
Peak memory 202328 kb
Host smart-8c562079-5e83-4378-866d-82e3d6a62c41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102909390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1102909390
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2765159665
Short name T179
Test name
Test status
Simulation time 490194864603 ps
CPU time 93.89 seconds
Started May 07 03:26:47 PM PDT 24
Finished May 07 03:28:21 PM PDT 24
Peak memory 202320 kb
Host smart-50fa86c7-7dde-4cff-96e1-dda002190445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765159665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2765159665
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1966396069
Short name T155
Test name
Test status
Simulation time 494395531902 ps
CPU time 1059.22 seconds
Started May 07 03:26:50 PM PDT 24
Finished May 07 03:44:30 PM PDT 24
Peak memory 202228 kb
Host smart-bded7310-5a7e-4c65-a371-2b6d5a62e9e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966396069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1966396069
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.827073171
Short name T233
Test name
Test status
Simulation time 360657176623 ps
CPU time 133.1 seconds
Started May 07 03:26:49 PM PDT 24
Finished May 07 03:29:03 PM PDT 24
Peak memory 202316 kb
Host smart-eee9becf-6931-44b2-81a5-8b7947e730af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827073171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.827073171
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2049415131
Short name T350
Test name
Test status
Simulation time 583466054841 ps
CPU time 1356.56 seconds
Started May 07 03:26:49 PM PDT 24
Finished May 07 03:49:27 PM PDT 24
Peak memory 202316 kb
Host smart-f4ad3bb3-98d2-4249-bc51-aa4f80c1074a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049415131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2049415131
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1728822897
Short name T607
Test name
Test status
Simulation time 110825329400 ps
CPU time 341.54 seconds
Started May 07 03:26:56 PM PDT 24
Finished May 07 03:32:39 PM PDT 24
Peak memory 202708 kb
Host smart-a2325656-30bb-4c0f-804a-11164079abb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728822897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1728822897
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.918044753
Short name T628
Test name
Test status
Simulation time 38972304594 ps
CPU time 45.41 seconds
Started May 07 03:26:50 PM PDT 24
Finished May 07 03:27:37 PM PDT 24
Peak memory 202136 kb
Host smart-b5899587-cef4-4359-84bf-d46cae235c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918044753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.918044753
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.41973116
Short name T669
Test name
Test status
Simulation time 5303777607 ps
CPU time 6.38 seconds
Started May 07 03:26:49 PM PDT 24
Finished May 07 03:26:56 PM PDT 24
Peak memory 202124 kb
Host smart-216ae71b-0974-482b-865f-05323eca55ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41973116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.41973116
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3025401250
Short name T369
Test name
Test status
Simulation time 5967230616 ps
CPU time 6.63 seconds
Started May 07 03:26:50 PM PDT 24
Finished May 07 03:26:57 PM PDT 24
Peak memory 202128 kb
Host smart-60673989-9cec-4fa7-a581-211671d1be96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025401250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3025401250
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1006473252
Short name T564
Test name
Test status
Simulation time 163930166053 ps
CPU time 358.09 seconds
Started May 07 03:26:55 PM PDT 24
Finished May 07 03:32:54 PM PDT 24
Peak memory 202312 kb
Host smart-ed01fafa-400c-435c-b805-ccf1cf922b5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006473252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1006473252
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2173838158
Short name T655
Test name
Test status
Simulation time 32800286386 ps
CPU time 132.86 seconds
Started May 07 03:26:56 PM PDT 24
Finished May 07 03:29:10 PM PDT 24
Peak memory 210992 kb
Host smart-841a9957-cb0d-40b7-b874-0008b40fb54d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173838158 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2173838158
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.75746408
Short name T786
Test name
Test status
Simulation time 422512411 ps
CPU time 0.84 seconds
Started May 07 03:27:05 PM PDT 24
Finished May 07 03:27:07 PM PDT 24
Peak memory 202032 kb
Host smart-7663474e-be4b-4da1-950b-890bd23061eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75746408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.75746408
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4288128600
Short name T90
Test name
Test status
Simulation time 208715040040 ps
CPU time 101.01 seconds
Started May 07 03:26:54 PM PDT 24
Finished May 07 03:28:36 PM PDT 24
Peak memory 202300 kb
Host smart-9cd3f2f3-bdd7-4ede-8e1d-cf64756f27d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288128600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4288128600
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.4160914949
Short name T729
Test name
Test status
Simulation time 331771351215 ps
CPU time 245.02 seconds
Started May 07 03:26:55 PM PDT 24
Finished May 07 03:31:00 PM PDT 24
Peak memory 201788 kb
Host smart-77a9b021-0cad-4fd5-ae1a-b68af0b94c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160914949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.4160914949
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3195630470
Short name T522
Test name
Test status
Simulation time 168173556556 ps
CPU time 109.52 seconds
Started May 07 03:26:58 PM PDT 24
Finished May 07 03:28:48 PM PDT 24
Peak memory 202304 kb
Host smart-83252633-c228-47de-8ccc-90b53b3c9694
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195630470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3195630470
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2034226636
Short name T5
Test name
Test status
Simulation time 500015794968 ps
CPU time 1167.88 seconds
Started May 07 03:26:54 PM PDT 24
Finished May 07 03:46:22 PM PDT 24
Peak memory 202348 kb
Host smart-ffadb8ef-c576-491e-aecf-930463f1db70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034226636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2034226636
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3705101328
Short name T161
Test name
Test status
Simulation time 163756309992 ps
CPU time 88.69 seconds
Started May 07 03:26:57 PM PDT 24
Finished May 07 03:28:27 PM PDT 24
Peak memory 202292 kb
Host smart-a4ab23b7-8620-4f8a-a11f-e84c52cc0bb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705101328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3705101328
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1694327850
Short name T477
Test name
Test status
Simulation time 611054216797 ps
CPU time 1496.34 seconds
Started May 07 03:26:55 PM PDT 24
Finished May 07 03:51:52 PM PDT 24
Peak memory 202324 kb
Host smart-72e7067c-40b7-4108-bf22-e85169deae40
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694327850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1694327850
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1319935326
Short name T687
Test name
Test status
Simulation time 68561454524 ps
CPU time 211.93 seconds
Started May 07 03:26:57 PM PDT 24
Finished May 07 03:30:30 PM PDT 24
Peak memory 202628 kb
Host smart-069acfdb-5bf9-4cb8-b20b-6aa1ccbc9ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319935326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1319935326
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.464514892
Short name T521
Test name
Test status
Simulation time 32302717301 ps
CPU time 7.82 seconds
Started May 07 03:26:54 PM PDT 24
Finished May 07 03:27:03 PM PDT 24
Peak memory 202148 kb
Host smart-ce5c4cc3-9bb9-4526-a35f-c5b5f1d0e48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464514892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.464514892
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2213386788
Short name T742
Test name
Test status
Simulation time 3064058572 ps
CPU time 2.09 seconds
Started May 07 03:26:57 PM PDT 24
Finished May 07 03:26:59 PM PDT 24
Peak memory 202156 kb
Host smart-2c34b1ad-cec8-4b75-92d0-4acc1a5ea0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213386788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2213386788
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2898356504
Short name T770
Test name
Test status
Simulation time 5689293007 ps
CPU time 13.9 seconds
Started May 07 03:26:56 PM PDT 24
Finished May 07 03:27:10 PM PDT 24
Peak memory 202140 kb
Host smart-ee413e0d-46d1-450a-bc3f-2c4b862c8135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898356504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2898356504
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1800300772
Short name T404
Test name
Test status
Simulation time 64442086234 ps
CPU time 37.41 seconds
Started May 07 03:27:02 PM PDT 24
Finished May 07 03:27:40 PM PDT 24
Peak memory 202104 kb
Host smart-305f49ff-8e0f-4f4b-a667-13ce8961abef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800300772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1800300772
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3414268485
Short name T249
Test name
Test status
Simulation time 425262777340 ps
CPU time 208.13 seconds
Started May 07 03:26:55 PM PDT 24
Finished May 07 03:30:24 PM PDT 24
Peak memory 211036 kb
Host smart-2a79a926-907a-446a-bc6f-871065296cc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414268485 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3414268485
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2292645843
Short name T353
Test name
Test status
Simulation time 352590999 ps
CPU time 1.5 seconds
Started May 07 03:27:00 PM PDT 24
Finished May 07 03:27:02 PM PDT 24
Peak memory 202008 kb
Host smart-7b548386-a574-4a09-b77f-241d7507a374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292645843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2292645843
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2147920763
Short name T165
Test name
Test status
Simulation time 332216276300 ps
CPU time 356.95 seconds
Started May 07 03:27:00 PM PDT 24
Finished May 07 03:32:58 PM PDT 24
Peak memory 202332 kb
Host smart-eabf95eb-fb6f-40ce-92cf-ec640148d1a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147920763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2147920763
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3810594624
Short name T762
Test name
Test status
Simulation time 204213061315 ps
CPU time 124.08 seconds
Started May 07 03:27:00 PM PDT 24
Finished May 07 03:29:05 PM PDT 24
Peak memory 202400 kb
Host smart-1753c551-af4a-4d67-9e6b-3dbe30312b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810594624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3810594624
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3128495523
Short name T482
Test name
Test status
Simulation time 332595663937 ps
CPU time 256.24 seconds
Started May 07 03:27:04 PM PDT 24
Finished May 07 03:31:21 PM PDT 24
Peak memory 202344 kb
Host smart-d31cef8d-93e0-4f2c-928e-ad71c5e0a0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128495523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3128495523
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3123143416
Short name T192
Test name
Test status
Simulation time 488070726739 ps
CPU time 276.36 seconds
Started May 07 03:27:01 PM PDT 24
Finished May 07 03:31:38 PM PDT 24
Peak memory 202368 kb
Host smart-1b7d0eb5-cab0-4821-acba-08750f3ebcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123143416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3123143416
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1707967823
Short name T406
Test name
Test status
Simulation time 487517566440 ps
CPU time 999.68 seconds
Started May 07 03:27:04 PM PDT 24
Finished May 07 03:43:44 PM PDT 24
Peak memory 202272 kb
Host smart-738122d8-352d-488d-95ba-a97643f56a60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707967823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1707967823
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1823617662
Short name T747
Test name
Test status
Simulation time 199588718560 ps
CPU time 167.27 seconds
Started May 07 03:27:01 PM PDT 24
Finished May 07 03:29:49 PM PDT 24
Peak memory 202276 kb
Host smart-15c80834-677e-423e-8e00-ee9274cdfb27
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823617662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1823617662
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3216732010
Short name T639
Test name
Test status
Simulation time 69454280933 ps
CPU time 288.57 seconds
Started May 07 03:27:00 PM PDT 24
Finished May 07 03:31:50 PM PDT 24
Peak memory 202696 kb
Host smart-aa034b0a-aa5a-4735-89a0-1332fc63e96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216732010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3216732010
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1866898670
Short name T580
Test name
Test status
Simulation time 41966336610 ps
CPU time 104.16 seconds
Started May 07 03:27:00 PM PDT 24
Finished May 07 03:28:46 PM PDT 24
Peak memory 202152 kb
Host smart-f193584b-5379-4793-8ef9-ce29e701e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866898670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1866898670
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.685704402
Short name T739
Test name
Test status
Simulation time 4760832686 ps
CPU time 6.29 seconds
Started May 07 03:27:05 PM PDT 24
Finished May 07 03:27:12 PM PDT 24
Peak memory 202168 kb
Host smart-9002dc5c-bf76-4166-a658-d7792937f4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685704402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.685704402
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3796943917
Short name T385
Test name
Test status
Simulation time 6080136353 ps
CPU time 2.33 seconds
Started May 07 03:27:01 PM PDT 24
Finished May 07 03:27:04 PM PDT 24
Peak memory 202136 kb
Host smart-bf91f9d8-80a7-475d-ae3f-f0c81756ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796943917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3796943917
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3862020599
Short name T652
Test name
Test status
Simulation time 184594672875 ps
CPU time 75.68 seconds
Started May 07 03:27:02 PM PDT 24
Finished May 07 03:28:18 PM PDT 24
Peak memory 202364 kb
Host smart-af950b6a-e4ad-4bdc-ba83-3a50dea5d384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862020599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3862020599
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1181192148
Short name T782
Test name
Test status
Simulation time 447162352 ps
CPU time 0.92 seconds
Started May 07 03:27:07 PM PDT 24
Finished May 07 03:27:09 PM PDT 24
Peak memory 202008 kb
Host smart-03b062c5-3057-42fb-a30d-0f130cf94f6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181192148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1181192148
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.345198379
Short name T27
Test name
Test status
Simulation time 167530163218 ps
CPU time 382.69 seconds
Started May 07 03:27:06 PM PDT 24
Finished May 07 03:33:30 PM PDT 24
Peak memory 202296 kb
Host smart-6d65aed8-4118-4370-8769-417656758738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345198379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.345198379
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.924317963
Short name T801
Test name
Test status
Simulation time 492846448209 ps
CPU time 582.24 seconds
Started May 07 03:27:01 PM PDT 24
Finished May 07 03:36:44 PM PDT 24
Peak memory 202276 kb
Host smart-8bd7cccb-a2b7-4346-90a3-a39b1dbe7938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924317963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.924317963
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2294996460
Short name T441
Test name
Test status
Simulation time 498008942286 ps
CPU time 467.72 seconds
Started May 07 03:26:59 PM PDT 24
Finished May 07 03:34:48 PM PDT 24
Peak memory 202316 kb
Host smart-663e8a1c-0839-467c-b8dd-57f9cb1c9af8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294996460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2294996460
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.289008254
Short name T591
Test name
Test status
Simulation time 159607289647 ps
CPU time 394.38 seconds
Started May 07 03:27:01 PM PDT 24
Finished May 07 03:33:36 PM PDT 24
Peak memory 202364 kb
Host smart-a2b6c9e2-80eb-4ff7-9d3d-013732f5f66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289008254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.289008254
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2572410588
Short name T9
Test name
Test status
Simulation time 500767678489 ps
CPU time 621.63 seconds
Started May 07 03:27:03 PM PDT 24
Finished May 07 03:37:25 PM PDT 24
Peak memory 202356 kb
Host smart-ae602763-14fe-4320-aba0-71341992ed9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572410588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2572410588
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2516577430
Short name T248
Test name
Test status
Simulation time 192756157075 ps
CPU time 447.89 seconds
Started May 07 03:27:06 PM PDT 24
Finished May 07 03:34:35 PM PDT 24
Peak memory 202340 kb
Host smart-e1d3531d-3e55-42ee-8de2-06008f57b457
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516577430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2516577430
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.4176166504
Short name T422
Test name
Test status
Simulation time 412767106899 ps
CPU time 959.9 seconds
Started May 07 03:27:08 PM PDT 24
Finished May 07 03:43:09 PM PDT 24
Peak memory 202312 kb
Host smart-ceb18e5d-9b98-4386-a1c3-057de2bb173c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176166504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.4176166504
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2781897565
Short name T664
Test name
Test status
Simulation time 108670204525 ps
CPU time 535.16 seconds
Started May 07 03:27:07 PM PDT 24
Finished May 07 03:36:03 PM PDT 24
Peak memory 202676 kb
Host smart-71c6060f-8744-4931-b5ce-983c56c4e7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781897565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2781897565
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3611062752
Short name T425
Test name
Test status
Simulation time 30553819547 ps
CPU time 16.89 seconds
Started May 07 03:27:08 PM PDT 24
Finished May 07 03:27:26 PM PDT 24
Peak memory 202176 kb
Host smart-27fd9c76-d71b-47e1-a85b-87d6c6f3c227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611062752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3611062752
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.4058602903
Short name T682
Test name
Test status
Simulation time 5482202246 ps
CPU time 5.57 seconds
Started May 07 03:27:07 PM PDT 24
Finished May 07 03:27:13 PM PDT 24
Peak memory 202136 kb
Host smart-b0ac60f8-6459-4a4c-a13f-97b4e71dbb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058602903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.4058602903
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1998566390
Short name T575
Test name
Test status
Simulation time 5751779743 ps
CPU time 4.18 seconds
Started May 07 03:27:00 PM PDT 24
Finished May 07 03:27:05 PM PDT 24
Peak memory 202156 kb
Host smart-1e9bbdb4-f373-496a-95c0-6f8704fa650a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998566390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1998566390
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.691843192
Short name T203
Test name
Test status
Simulation time 571987609529 ps
CPU time 478.51 seconds
Started May 07 03:27:06 PM PDT 24
Finished May 07 03:35:05 PM PDT 24
Peak memory 202680 kb
Host smart-8bb91693-8ab6-49d9-9307-9ebdf3918346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691843192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
691843192
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2030578941
Short name T780
Test name
Test status
Simulation time 487433556 ps
CPU time 0.93 seconds
Started May 07 03:25:06 PM PDT 24
Finished May 07 03:25:09 PM PDT 24
Peak memory 202000 kb
Host smart-6f2ea90d-6bef-4248-9316-d42ee08aa21c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030578941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2030578941
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1745665676
Short name T171
Test name
Test status
Simulation time 328994258813 ps
CPU time 27.95 seconds
Started May 07 03:25:07 PM PDT 24
Finished May 07 03:25:36 PM PDT 24
Peak memory 202296 kb
Host smart-ee9b6acb-eaf0-4cde-9f93-725520e55e27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745665676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1745665676
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1464149884
Short name T257
Test name
Test status
Simulation time 574144497365 ps
CPU time 1330.81 seconds
Started May 07 03:25:03 PM PDT 24
Finished May 07 03:47:15 PM PDT 24
Peak memory 202288 kb
Host smart-9c93503a-d472-466e-8069-c972478cf72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464149884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1464149884
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3528863545
Short name T30
Test name
Test status
Simulation time 324012134136 ps
CPU time 379.23 seconds
Started May 07 03:25:05 PM PDT 24
Finished May 07 03:31:25 PM PDT 24
Peak memory 202340 kb
Host smart-691f56a8-591c-4c4a-89c1-bcd45974d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528863545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3528863545
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1812522738
Short name T586
Test name
Test status
Simulation time 324594848530 ps
CPU time 115.15 seconds
Started May 07 03:25:04 PM PDT 24
Finished May 07 03:27:00 PM PDT 24
Peak memory 202280 kb
Host smart-b429b7d6-e1fd-41cf-b284-d768eb214279
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812522738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1812522738
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3346167874
Short name T320
Test name
Test status
Simulation time 326065586943 ps
CPU time 383.23 seconds
Started May 07 03:25:01 PM PDT 24
Finished May 07 03:31:25 PM PDT 24
Peak memory 202328 kb
Host smart-b1c53976-4bb1-4b27-a10a-d2a0043620f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346167874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3346167874
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2018644307
Short name T525
Test name
Test status
Simulation time 486017607106 ps
CPU time 515.18 seconds
Started May 07 03:25:08 PM PDT 24
Finished May 07 03:33:44 PM PDT 24
Peak memory 202320 kb
Host smart-d448f044-691f-4028-be2c-5f4cc63f1db8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018644307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2018644307
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.856897099
Short name T137
Test name
Test status
Simulation time 165335987539 ps
CPU time 404.44 seconds
Started May 07 03:25:04 PM PDT 24
Finished May 07 03:31:50 PM PDT 24
Peak memory 202328 kb
Host smart-1fb9096d-29bc-424d-b99d-68b9c49826a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856897099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.856897099
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1338578957
Short name T634
Test name
Test status
Simulation time 196298937068 ps
CPU time 43.71 seconds
Started May 07 03:25:03 PM PDT 24
Finished May 07 03:25:48 PM PDT 24
Peak memory 202372 kb
Host smart-d01fa35f-611f-4c7b-8114-91f63b0ea578
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338578957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1338578957
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3163696385
Short name T644
Test name
Test status
Simulation time 104281992067 ps
CPU time 412.86 seconds
Started May 07 03:25:02 PM PDT 24
Finished May 07 03:31:56 PM PDT 24
Peak memory 202652 kb
Host smart-a5467e71-4bb7-4971-90a1-eb3920729652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163696385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3163696385
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.51116153
Short name T409
Test name
Test status
Simulation time 37829118843 ps
CPU time 21.39 seconds
Started May 07 03:25:07 PM PDT 24
Finished May 07 03:25:30 PM PDT 24
Peak memory 202120 kb
Host smart-e430a26f-d0fb-4e31-bcad-14e0be5ad925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51116153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.51116153
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.4262726956
Short name T534
Test name
Test status
Simulation time 4924037568 ps
CPU time 6.4 seconds
Started May 07 03:25:05 PM PDT 24
Finished May 07 03:25:13 PM PDT 24
Peak memory 202148 kb
Host smart-813e14e1-14ec-44b3-a7cd-ae977fd38712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262726956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.4262726956
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3974446214
Short name T72
Test name
Test status
Simulation time 3675875284 ps
CPU time 8.65 seconds
Started May 07 03:25:06 PM PDT 24
Finished May 07 03:25:16 PM PDT 24
Peak memory 217816 kb
Host smart-a90cc3c4-0a56-4f28-9f75-45733e43a3ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974446214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3974446214
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2987050915
Short name T725
Test name
Test status
Simulation time 5826660231 ps
CPU time 4.11 seconds
Started May 07 03:25:01 PM PDT 24
Finished May 07 03:25:06 PM PDT 24
Peak memory 202168 kb
Host smart-978e1c95-6285-4685-bee5-a6f4148c52b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987050915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2987050915
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1688477387
Short name T80
Test name
Test status
Simulation time 328838310884 ps
CPU time 162.43 seconds
Started May 07 03:25:08 PM PDT 24
Finished May 07 03:27:52 PM PDT 24
Peak memory 202336 kb
Host smart-f9e97d91-7a73-49ce-ac76-626d14a722da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688477387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1688477387
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3315934600
Short name T37
Test name
Test status
Simulation time 683162446456 ps
CPU time 206.15 seconds
Started May 07 03:25:03 PM PDT 24
Finished May 07 03:28:31 PM PDT 24
Peak memory 212136 kb
Host smart-007b5a35-91dc-4a6e-9644-df3d98225855
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315934600 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3315934600
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.4127306007
Short name T734
Test name
Test status
Simulation time 310569667 ps
CPU time 0.79 seconds
Started May 07 03:27:15 PM PDT 24
Finished May 07 03:27:16 PM PDT 24
Peak memory 201948 kb
Host smart-0e0bfd5e-a691-4524-b128-24770e53d0b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127306007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.4127306007
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.4053963881
Short name T313
Test name
Test status
Simulation time 165028746134 ps
CPU time 384.61 seconds
Started May 07 03:27:13 PM PDT 24
Finished May 07 03:33:38 PM PDT 24
Peak memory 202308 kb
Host smart-33a6e6f0-3430-4faf-b3bc-da88c6f1b5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053963881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.4053963881
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2386785019
Short name T295
Test name
Test status
Simulation time 168276192572 ps
CPU time 202.89 seconds
Started May 07 03:27:11 PM PDT 24
Finished May 07 03:30:35 PM PDT 24
Peak memory 202336 kb
Host smart-bb8a0991-4c9c-4741-bceb-91e77d272d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386785019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2386785019
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3044948763
Short name T225
Test name
Test status
Simulation time 488427563908 ps
CPU time 582.54 seconds
Started May 07 03:27:17 PM PDT 24
Finished May 07 03:37:00 PM PDT 24
Peak memory 202288 kb
Host smart-5e5c55d0-a29f-4594-bcc9-4d655a017c85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044948763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3044948763
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2923872958
Short name T738
Test name
Test status
Simulation time 495506918588 ps
CPU time 1237.31 seconds
Started May 07 03:27:06 PM PDT 24
Finished May 07 03:47:45 PM PDT 24
Peak memory 202388 kb
Host smart-cce3e2cb-644e-4d59-aace-eb49796ef86d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923872958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2923872958
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3229478352
Short name T487
Test name
Test status
Simulation time 203956324278 ps
CPU time 251.89 seconds
Started May 07 03:27:15 PM PDT 24
Finished May 07 03:31:27 PM PDT 24
Peak memory 202240 kb
Host smart-d687f5a7-2a4b-4b88-82b4-47d03dfa1fcf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229478352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3229478352
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2822968606
Short name T772
Test name
Test status
Simulation time 74436928955 ps
CPU time 239.89 seconds
Started May 07 03:27:11 PM PDT 24
Finished May 07 03:31:12 PM PDT 24
Peak memory 202632 kb
Host smart-ae98d03d-1f73-43f3-ac13-378866cfad7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822968606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2822968606
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3426193307
Short name T595
Test name
Test status
Simulation time 21069483668 ps
CPU time 6.15 seconds
Started May 07 03:27:11 PM PDT 24
Finished May 07 03:27:18 PM PDT 24
Peak memory 202148 kb
Host smart-c0a2aa5f-4294-4680-9505-eebff87ea922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426193307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3426193307
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3262851737
Short name T472
Test name
Test status
Simulation time 3397849881 ps
CPU time 8.84 seconds
Started May 07 03:27:12 PM PDT 24
Finished May 07 03:27:21 PM PDT 24
Peak memory 202124 kb
Host smart-b189d6fd-fde2-42b6-bc82-0dbf34e95120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262851737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3262851737
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3229022656
Short name T388
Test name
Test status
Simulation time 5557666428 ps
CPU time 14.65 seconds
Started May 07 03:27:05 PM PDT 24
Finished May 07 03:27:21 PM PDT 24
Peak memory 202156 kb
Host smart-d1a2c4a7-8ee6-4a0b-b922-5c7e66472f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229022656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3229022656
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3898627477
Short name T608
Test name
Test status
Simulation time 235788011917 ps
CPU time 162.67 seconds
Started May 07 03:27:11 PM PDT 24
Finished May 07 03:29:54 PM PDT 24
Peak memory 202328 kb
Host smart-5244e01b-bcc2-4414-92a8-9b62736cdf53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898627477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3898627477
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.681548233
Short name T199
Test name
Test status
Simulation time 332974234215 ps
CPU time 69.32 seconds
Started May 07 03:27:10 PM PDT 24
Finished May 07 03:28:20 PM PDT 24
Peak memory 210644 kb
Host smart-b08758a8-ba10-4f9b-aaed-c8d8fc22c843
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681548233 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.681548233
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1731592744
Short name T502
Test name
Test status
Simulation time 418931073 ps
CPU time 1.48 seconds
Started May 07 03:27:24 PM PDT 24
Finished May 07 03:27:27 PM PDT 24
Peak memory 202000 kb
Host smart-f9a0a3e4-5def-445c-8c08-4f1cecfc13cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731592744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1731592744
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.336333304
Short name T198
Test name
Test status
Simulation time 508310319100 ps
CPU time 199.33 seconds
Started May 07 03:27:17 PM PDT 24
Finished May 07 03:30:37 PM PDT 24
Peak memory 202332 kb
Host smart-9aa5379a-e113-45f4-8d64-67914e7f511b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336333304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.336333304
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3763257461
Short name T713
Test name
Test status
Simulation time 332360963452 ps
CPU time 209.22 seconds
Started May 07 03:27:17 PM PDT 24
Finished May 07 03:30:47 PM PDT 24
Peak memory 202252 kb
Host smart-58701665-3dbb-45f5-9209-dafd6de54738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763257461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3763257461
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.926807742
Short name T599
Test name
Test status
Simulation time 483012914982 ps
CPU time 72.3 seconds
Started May 07 03:27:22 PM PDT 24
Finished May 07 03:28:36 PM PDT 24
Peak memory 202284 kb
Host smart-ecf9762e-ceea-4efa-8887-8973d4a627b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=926807742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.926807742
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1555879707
Short name T774
Test name
Test status
Simulation time 322727347564 ps
CPU time 766.32 seconds
Started May 07 03:27:17 PM PDT 24
Finished May 07 03:40:04 PM PDT 24
Peak memory 202308 kb
Host smart-f2434550-afbf-4348-9dba-fcc4fb478fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555879707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1555879707
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3961609659
Short name T488
Test name
Test status
Simulation time 336130531906 ps
CPU time 301.65 seconds
Started May 07 03:27:17 PM PDT 24
Finished May 07 03:32:19 PM PDT 24
Peak memory 202276 kb
Host smart-a7d099ee-e2d2-420c-a548-5fe13f5adf40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961609659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3961609659
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2986386527
Short name T616
Test name
Test status
Simulation time 175311674312 ps
CPU time 107.11 seconds
Started May 07 03:27:22 PM PDT 24
Finished May 07 03:29:11 PM PDT 24
Peak memory 202384 kb
Host smart-afae7e46-72d9-4e3b-94c5-c4c3fa714776
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986386527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2986386527
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3361138501
Short name T757
Test name
Test status
Simulation time 205008992472 ps
CPU time 119.4 seconds
Started May 07 03:27:17 PM PDT 24
Finished May 07 03:29:17 PM PDT 24
Peak memory 202384 kb
Host smart-f442de24-b1d8-46bc-8bb8-74ce7d4846ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361138501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3361138501
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.4042382151
Short name T210
Test name
Test status
Simulation time 104181204567 ps
CPU time 560.75 seconds
Started May 07 03:27:22 PM PDT 24
Finished May 07 03:36:44 PM PDT 24
Peak memory 202636 kb
Host smart-14b442bc-5cf6-46e6-9c74-84587faed4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042382151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.4042382151
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.754608257
Short name T771
Test name
Test status
Simulation time 26080686117 ps
CPU time 62.83 seconds
Started May 07 03:27:23 PM PDT 24
Finished May 07 03:28:27 PM PDT 24
Peak memory 202112 kb
Host smart-c6b30b84-cfbd-4094-93d9-9de87d7a7063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754608257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.754608257
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1215880157
Short name T582
Test name
Test status
Simulation time 4037430987 ps
CPU time 10.86 seconds
Started May 07 03:27:17 PM PDT 24
Finished May 07 03:27:29 PM PDT 24
Peak memory 202140 kb
Host smart-ab824f97-b4a8-4653-802c-59253f4b2824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215880157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1215880157
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2840488956
Short name T347
Test name
Test status
Simulation time 5872008285 ps
CPU time 4.19 seconds
Started May 07 03:27:18 PM PDT 24
Finished May 07 03:27:23 PM PDT 24
Peak memory 202176 kb
Host smart-1c684e5a-84be-4603-a33f-6882780333c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840488956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2840488956
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2734723693
Short name T677
Test name
Test status
Simulation time 10943520125 ps
CPU time 6.61 seconds
Started May 07 03:27:27 PM PDT 24
Finished May 07 03:27:34 PM PDT 24
Peak memory 202112 kb
Host smart-b0b33ad4-08b6-4afb-9bb8-13ae7642dd52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734723693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2734723693
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3121819684
Short name T540
Test name
Test status
Simulation time 48409309222 ps
CPU time 142.28 seconds
Started May 07 03:27:20 PM PDT 24
Finished May 07 03:29:44 PM PDT 24
Peak memory 211008 kb
Host smart-2bcb9059-cef5-48e2-866f-897e2858adfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121819684 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3121819684
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3750787109
Short name T375
Test name
Test status
Simulation time 353837641 ps
CPU time 1 seconds
Started May 07 03:27:30 PM PDT 24
Finished May 07 03:27:32 PM PDT 24
Peak memory 201988 kb
Host smart-ab8a775c-f974-40be-bff9-cf96e58a0cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750787109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3750787109
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3831043567
Short name T610
Test name
Test status
Simulation time 163414434175 ps
CPU time 25.67 seconds
Started May 07 03:27:28 PM PDT 24
Finished May 07 03:27:54 PM PDT 24
Peak memory 202324 kb
Host smart-3f49da96-8581-44c3-be03-b5eee7f54bb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831043567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3831043567
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2465818288
Short name T562
Test name
Test status
Simulation time 532373055296 ps
CPU time 1146.35 seconds
Started May 07 03:27:26 PM PDT 24
Finished May 07 03:46:34 PM PDT 24
Peak memory 202412 kb
Host smart-bdde0d63-352c-4d84-bea9-4858b1d9c8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465818288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2465818288
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.748582637
Short name T589
Test name
Test status
Simulation time 165820395145 ps
CPU time 425.96 seconds
Started May 07 03:27:22 PM PDT 24
Finished May 07 03:34:29 PM PDT 24
Peak memory 202376 kb
Host smart-930cd3d4-579b-435e-9992-24828d07188b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748582637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.748582637
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2865921383
Short name T728
Test name
Test status
Simulation time 491108577145 ps
CPU time 279.77 seconds
Started May 07 03:27:21 PM PDT 24
Finished May 07 03:32:02 PM PDT 24
Peak memory 202304 kb
Host smart-b8b79b67-71b2-45cf-896e-cde120841575
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865921383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2865921383
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1114424870
Short name T752
Test name
Test status
Simulation time 489489634016 ps
CPU time 1097.81 seconds
Started May 07 03:27:26 PM PDT 24
Finished May 07 03:45:45 PM PDT 24
Peak memory 202268 kb
Host smart-826da07f-daea-400c-b971-d160aa74c67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114424870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1114424870
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.447549711
Short name T10
Test name
Test status
Simulation time 488805510375 ps
CPU time 598.16 seconds
Started May 07 03:27:22 PM PDT 24
Finished May 07 03:37:22 PM PDT 24
Peak memory 202296 kb
Host smart-b024c069-8327-4fa2-8397-ff956969d7b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=447549711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.447549711
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.702670235
Short name T571
Test name
Test status
Simulation time 169834035169 ps
CPU time 96.05 seconds
Started May 07 03:27:21 PM PDT 24
Finished May 07 03:28:59 PM PDT 24
Peak memory 202324 kb
Host smart-99742015-0c04-4e9a-a8e0-73526d6c3828
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702670235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.702670235
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2267959759
Short name T342
Test name
Test status
Simulation time 424809180841 ps
CPU time 496.96 seconds
Started May 07 03:27:26 PM PDT 24
Finished May 07 03:35:44 PM PDT 24
Peak memory 202284 kb
Host smart-b23eb4ff-1ec1-4f05-b4f2-e21ddc543e74
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267959759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2267959759
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2575094971
Short name T633
Test name
Test status
Simulation time 113133111392 ps
CPU time 470.9 seconds
Started May 07 03:27:28 PM PDT 24
Finished May 07 03:35:20 PM PDT 24
Peak memory 202752 kb
Host smart-b5e8c75f-f936-45d8-add4-7f332689d544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575094971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2575094971
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1640724586
Short name T490
Test name
Test status
Simulation time 33117003108 ps
CPU time 77.74 seconds
Started May 07 03:27:29 PM PDT 24
Finished May 07 03:28:47 PM PDT 24
Peak memory 202140 kb
Host smart-329479f6-9fdc-4326-915e-a4095bc72298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640724586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1640724586
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2379153531
Short name T577
Test name
Test status
Simulation time 4180726531 ps
CPU time 3.23 seconds
Started May 07 03:27:28 PM PDT 24
Finished May 07 03:27:32 PM PDT 24
Peak memory 202168 kb
Host smart-b44a2ee1-b435-4787-bcd0-b1989ec17043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379153531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2379153531
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3914976757
Short name T380
Test name
Test status
Simulation time 5618647949 ps
CPU time 4.18 seconds
Started May 07 03:27:24 PM PDT 24
Finished May 07 03:27:30 PM PDT 24
Peak memory 202152 kb
Host smart-9619c171-2112-4ff1-953c-6044d9290a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914976757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3914976757
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.4240433957
Short name T134
Test name
Test status
Simulation time 276849517616 ps
CPU time 593.08 seconds
Started May 07 03:27:28 PM PDT 24
Finished May 07 03:37:21 PM PDT 24
Peak memory 202752 kb
Host smart-74d8d278-380b-4976-b6ea-d6d122c3b61b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240433957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.4240433957
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2210684799
Short name T16
Test name
Test status
Simulation time 114826020817 ps
CPU time 174.62 seconds
Started May 07 03:27:27 PM PDT 24
Finished May 07 03:30:22 PM PDT 24
Peak memory 210988 kb
Host smart-b6098eee-36ee-4627-8bdb-26b07ca21b2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210684799 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2210684799
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3027638221
Short name T88
Test name
Test status
Simulation time 411434299 ps
CPU time 0.75 seconds
Started May 07 03:27:31 PM PDT 24
Finished May 07 03:27:32 PM PDT 24
Peak memory 202028 kb
Host smart-f1b31a93-d501-4108-ad67-e0e3569a7476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027638221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3027638221
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2131573154
Short name T224
Test name
Test status
Simulation time 184413762900 ps
CPU time 383.16 seconds
Started May 07 03:27:33 PM PDT 24
Finished May 07 03:33:57 PM PDT 24
Peak memory 202336 kb
Host smart-bc205594-6fed-4f27-9057-b166811d6e21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131573154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2131573154
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.886884173
Short name T243
Test name
Test status
Simulation time 175083103752 ps
CPU time 125.1 seconds
Started May 07 03:27:31 PM PDT 24
Finished May 07 03:29:37 PM PDT 24
Peak memory 202344 kb
Host smart-7d473eb8-a095-4884-a4a2-86ec26d6271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886884173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.886884173
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2295151577
Short name T196
Test name
Test status
Simulation time 321059482164 ps
CPU time 404.61 seconds
Started May 07 03:27:33 PM PDT 24
Finished May 07 03:34:18 PM PDT 24
Peak memory 202336 kb
Host smart-218e4c15-94b4-4be0-9cb8-6e7436e4a239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295151577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2295151577
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3283161612
Short name T341
Test name
Test status
Simulation time 488180269267 ps
CPU time 1050.95 seconds
Started May 07 03:27:32 PM PDT 24
Finished May 07 03:45:04 PM PDT 24
Peak memory 202284 kb
Host smart-16aba741-05e9-4a42-afce-2e941ddceecf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283161612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3283161612
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2728932191
Short name T133
Test name
Test status
Simulation time 494938502697 ps
CPU time 1111.97 seconds
Started May 07 03:27:32 PM PDT 24
Finished May 07 03:46:04 PM PDT 24
Peak memory 202380 kb
Host smart-a83ccd07-8311-4d60-a31d-c2fb474404c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728932191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2728932191
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1173767386
Short name T743
Test name
Test status
Simulation time 165924861078 ps
CPU time 203.72 seconds
Started May 07 03:27:32 PM PDT 24
Finished May 07 03:30:57 PM PDT 24
Peak memory 202376 kb
Host smart-4b7b8f48-a9ae-47f1-aa50-a02774fba374
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173767386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1173767386
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1268668396
Short name T516
Test name
Test status
Simulation time 362683370712 ps
CPU time 881.22 seconds
Started May 07 03:27:32 PM PDT 24
Finished May 07 03:42:14 PM PDT 24
Peak memory 202388 kb
Host smart-c0d8e5e8-3ba2-4d3a-b0e7-8d34f9a7aa5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268668396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1268668396
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2261029971
Short name T653
Test name
Test status
Simulation time 593110342867 ps
CPU time 206.79 seconds
Started May 07 03:27:31 PM PDT 24
Finished May 07 03:30:59 PM PDT 24
Peak memory 202324 kb
Host smart-12bd5667-001f-4ffd-a619-ae281d5ba0a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261029971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2261029971
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3166870231
Short name T42
Test name
Test status
Simulation time 110267474820 ps
CPU time 395.32 seconds
Started May 07 03:27:34 PM PDT 24
Finished May 07 03:34:10 PM PDT 24
Peak memory 202768 kb
Host smart-073be537-2398-474e-9b90-80c2f10e3279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166870231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3166870231
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2508502770
Short name T464
Test name
Test status
Simulation time 43027326128 ps
CPU time 27.83 seconds
Started May 07 03:27:30 PM PDT 24
Finished May 07 03:27:59 PM PDT 24
Peak memory 202164 kb
Host smart-a20694e6-002a-4b05-a51b-3d7a9f71ef63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508502770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2508502770
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1786771344
Short name T600
Test name
Test status
Simulation time 2821307091 ps
CPU time 6.59 seconds
Started May 07 03:27:36 PM PDT 24
Finished May 07 03:27:43 PM PDT 24
Peak memory 202104 kb
Host smart-e71208fa-3d05-4cce-af4f-d62edf6e611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786771344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1786771344
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3057286627
Short name T741
Test name
Test status
Simulation time 5618598738 ps
CPU time 4.21 seconds
Started May 07 03:27:28 PM PDT 24
Finished May 07 03:27:33 PM PDT 24
Peak memory 202132 kb
Host smart-14f31e14-403b-4850-8c32-c9810c7fd03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057286627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3057286627
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.837174768
Short name T223
Test name
Test status
Simulation time 407076679484 ps
CPU time 1361.35 seconds
Started May 07 03:27:32 PM PDT 24
Finished May 07 03:50:15 PM PDT 24
Peak memory 213008 kb
Host smart-9f5a3019-b999-4ce4-9712-f036ddf07d16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837174768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
837174768
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3872495057
Short name T768
Test name
Test status
Simulation time 30383939879 ps
CPU time 27.67 seconds
Started May 07 03:27:33 PM PDT 24
Finished May 07 03:28:01 PM PDT 24
Peak memory 210968 kb
Host smart-029b60be-9da9-44c5-b1ec-d1781e3fc61e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872495057 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3872495057
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3539986565
Short name T620
Test name
Test status
Simulation time 295927078 ps
CPU time 0.97 seconds
Started May 07 03:27:44 PM PDT 24
Finished May 07 03:27:46 PM PDT 24
Peak memory 202016 kb
Host smart-62d92444-bee7-412b-bd3c-2c69b1371992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539986565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3539986565
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3355619513
Short name T695
Test name
Test status
Simulation time 344791235794 ps
CPU time 75.94 seconds
Started May 07 03:27:38 PM PDT 24
Finished May 07 03:28:55 PM PDT 24
Peak memory 202416 kb
Host smart-59c8e73d-d0a5-423a-bf10-3ea84a535081
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355619513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3355619513
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1177279103
Short name T156
Test name
Test status
Simulation time 353073441585 ps
CPU time 208.81 seconds
Started May 07 03:27:38 PM PDT 24
Finished May 07 03:31:08 PM PDT 24
Peak memory 202380 kb
Host smart-03a97e5f-96d9-47c0-b2ca-43fdd4e980c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177279103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1177279103
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3011085306
Short name T219
Test name
Test status
Simulation time 487749935031 ps
CPU time 1030.87 seconds
Started May 07 03:27:39 PM PDT 24
Finished May 07 03:44:50 PM PDT 24
Peak memory 202308 kb
Host smart-a1795d17-e63d-4787-9e9c-b830feed236f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011085306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3011085306
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1755844091
Short name T423
Test name
Test status
Simulation time 166131648637 ps
CPU time 101.84 seconds
Started May 07 03:27:45 PM PDT 24
Finished May 07 03:29:28 PM PDT 24
Peak memory 202336 kb
Host smart-0fdce2f5-4a3a-4a29-af30-d7d13d680266
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755844091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1755844091
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.472471250
Short name T706
Test name
Test status
Simulation time 170501935310 ps
CPU time 40.86 seconds
Started May 07 03:27:39 PM PDT 24
Finished May 07 03:28:20 PM PDT 24
Peak memory 202320 kb
Host smart-6784cc29-c750-409a-a2c9-a30266c92820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472471250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.472471250
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.995532308
Short name T660
Test name
Test status
Simulation time 500477170413 ps
CPU time 1142.84 seconds
Started May 07 03:27:39 PM PDT 24
Finished May 07 03:46:46 PM PDT 24
Peak memory 202288 kb
Host smart-e6446d9b-1acc-43bd-9c85-a4dc0526dbb6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=995532308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.995532308
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1133904942
Short name T789
Test name
Test status
Simulation time 580990133948 ps
CPU time 450.92 seconds
Started May 07 03:27:38 PM PDT 24
Finished May 07 03:35:10 PM PDT 24
Peak memory 202256 kb
Host smart-3e9ce639-4638-441b-90b5-208f6781dac6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133904942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1133904942
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1853629479
Short name T475
Test name
Test status
Simulation time 204184317024 ps
CPU time 39.99 seconds
Started May 07 03:27:37 PM PDT 24
Finished May 07 03:28:18 PM PDT 24
Peak memory 202296 kb
Host smart-2717e714-605c-4613-a68c-023304280547
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853629479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1853629479
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1553344711
Short name T440
Test name
Test status
Simulation time 68068179720 ps
CPU time 236.08 seconds
Started May 07 03:27:58 PM PDT 24
Finished May 07 03:31:55 PM PDT 24
Peak memory 202756 kb
Host smart-99319547-8605-44d8-b362-c74f26c2ad22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553344711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1553344711
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2104451341
Short name T749
Test name
Test status
Simulation time 27464803571 ps
CPU time 62.09 seconds
Started May 07 03:27:44 PM PDT 24
Finished May 07 03:28:48 PM PDT 24
Peak memory 202136 kb
Host smart-5d28fc6b-caa3-4028-b1ff-9a7a5217389d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104451341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2104451341
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.10770950
Short name T594
Test name
Test status
Simulation time 3639154024 ps
CPU time 2.64 seconds
Started May 07 03:27:46 PM PDT 24
Finished May 07 03:27:49 PM PDT 24
Peak memory 202152 kb
Host smart-0e48d0b8-3c63-45b7-874a-fe187a5ebee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10770950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.10770950
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.725485150
Short name T493
Test name
Test status
Simulation time 5819430821 ps
CPU time 13.61 seconds
Started May 07 03:27:39 PM PDT 24
Finished May 07 03:27:53 PM PDT 24
Peak memory 202160 kb
Host smart-d1a0fc43-7fb3-4991-a039-cc8c7864b47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725485150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.725485150
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.4249529263
Short name T13
Test name
Test status
Simulation time 343589678911 ps
CPU time 501.05 seconds
Started May 07 03:27:43 PM PDT 24
Finished May 07 03:36:05 PM PDT 24
Peak memory 202292 kb
Host smart-87113385-5d99-4bd5-8bc5-3c985af400f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249529263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.4249529263
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.780907502
Short name T437
Test name
Test status
Simulation time 175843454121 ps
CPU time 77.12 seconds
Started May 07 03:27:44 PM PDT 24
Finished May 07 03:29:03 PM PDT 24
Peak memory 202836 kb
Host smart-ec41597a-235d-4919-9591-9f2cb40254e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780907502 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.780907502
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.87426339
Short name T461
Test name
Test status
Simulation time 450392098 ps
CPU time 0.81 seconds
Started May 07 03:27:53 PM PDT 24
Finished May 07 03:27:54 PM PDT 24
Peak memory 201956 kb
Host smart-3bd3724b-f79b-4168-8a1a-fa34e54ee97b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87426339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.87426339
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3198970630
Short name T291
Test name
Test status
Simulation time 184528479696 ps
CPU time 425.5 seconds
Started May 07 03:27:43 PM PDT 24
Finished May 07 03:34:49 PM PDT 24
Peak memory 202292 kb
Host smart-67def8b7-816a-49e4-a61e-3cb16eb5f277
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198970630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3198970630
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3937787801
Short name T318
Test name
Test status
Simulation time 327085925574 ps
CPU time 785.71 seconds
Started May 07 03:27:54 PM PDT 24
Finished May 07 03:41:01 PM PDT 24
Peak memory 202304 kb
Host smart-e2a3d133-1c76-4a8d-aa22-dd79e1cf7d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937787801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3937787801
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1409283179
Short name T478
Test name
Test status
Simulation time 330366096525 ps
CPU time 194.99 seconds
Started May 07 03:27:45 PM PDT 24
Finished May 07 03:31:01 PM PDT 24
Peak memory 202340 kb
Host smart-2c440e3c-8160-451b-a43f-17b1f52bf03a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409283179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1409283179
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.4213355006
Short name T321
Test name
Test status
Simulation time 488058000766 ps
CPU time 1178.3 seconds
Started May 07 03:27:48 PM PDT 24
Finished May 07 03:47:27 PM PDT 24
Peak memory 202324 kb
Host smart-bfac0380-d733-4161-8f04-07860199dd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213355006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4213355006
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2281930897
Short name T412
Test name
Test status
Simulation time 333350602404 ps
CPU time 77.54 seconds
Started May 07 03:27:44 PM PDT 24
Finished May 07 03:29:03 PM PDT 24
Peak memory 202272 kb
Host smart-99368bf2-a46d-45bd-a6be-f294500a2c30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281930897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2281930897
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2892421343
Short name T271
Test name
Test status
Simulation time 536185624378 ps
CPU time 1247.19 seconds
Started May 07 03:27:43 PM PDT 24
Finished May 07 03:48:32 PM PDT 24
Peak memory 202332 kb
Host smart-4b9811bc-3297-44c4-a114-f7fdafb7baf9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892421343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2892421343
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.201359159
Short name T755
Test name
Test status
Simulation time 397625400480 ps
CPU time 865.51 seconds
Started May 07 03:27:43 PM PDT 24
Finished May 07 03:42:10 PM PDT 24
Peak memory 202328 kb
Host smart-024c035d-e368-40ca-ad62-add6fb33d52f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201359159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.201359159
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.537214700
Short name T649
Test name
Test status
Simulation time 125401549165 ps
CPU time 469.28 seconds
Started May 07 03:27:52 PM PDT 24
Finished May 07 03:35:42 PM PDT 24
Peak memory 202700 kb
Host smart-3db136b4-862c-44ac-8cd3-18e68cbfc6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537214700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.537214700
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1294473298
Short name T536
Test name
Test status
Simulation time 31219150606 ps
CPU time 36.73 seconds
Started May 07 03:27:49 PM PDT 24
Finished May 07 03:28:27 PM PDT 24
Peak memory 202172 kb
Host smart-8ffdb023-d66f-4ef8-b9d2-a3bf92a0bb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294473298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1294473298
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1936181346
Short name T87
Test name
Test status
Simulation time 4128585663 ps
CPU time 5.28 seconds
Started May 07 03:27:54 PM PDT 24
Finished May 07 03:28:00 PM PDT 24
Peak memory 202164 kb
Host smart-d3d80258-dc6d-443b-964e-53813b47d6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936181346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1936181346
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2390322924
Short name T563
Test name
Test status
Simulation time 5630694445 ps
CPU time 7.58 seconds
Started May 07 03:27:43 PM PDT 24
Finished May 07 03:27:51 PM PDT 24
Peak memory 202140 kb
Host smart-f05b8b7e-b068-4e07-80f9-74b990424c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390322924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2390322924
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.731482250
Short name T82
Test name
Test status
Simulation time 145937056235 ps
CPU time 79.22 seconds
Started May 07 03:27:54 PM PDT 24
Finished May 07 03:29:13 PM PDT 24
Peak memory 210688 kb
Host smart-bf275cf5-04f0-4d9c-b08b-6998b35abdfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731482250 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.731482250
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.305840249
Short name T460
Test name
Test status
Simulation time 349218910 ps
CPU time 0.83 seconds
Started May 07 03:28:02 PM PDT 24
Finished May 07 03:28:04 PM PDT 24
Peak memory 202028 kb
Host smart-f1764ae7-728a-4f5c-925f-d0128315ce31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305840249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.305840249
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3346988202
Short name T244
Test name
Test status
Simulation time 354130167733 ps
CPU time 34.5 seconds
Started May 07 03:28:03 PM PDT 24
Finished May 07 03:28:38 PM PDT 24
Peak memory 202408 kb
Host smart-e4dbf975-de63-45bc-88b4-e2ab9e7df500
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346988202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3346988202
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.567759332
Short name T485
Test name
Test status
Simulation time 182027522101 ps
CPU time 403.09 seconds
Started May 07 03:27:58 PM PDT 24
Finished May 07 03:34:41 PM PDT 24
Peak memory 202308 kb
Host smart-2703e101-6934-4887-a5ab-d64b33eebef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567759332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.567759332
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2704985194
Short name T558
Test name
Test status
Simulation time 484682279242 ps
CPU time 1025.21 seconds
Started May 07 03:27:57 PM PDT 24
Finished May 07 03:45:03 PM PDT 24
Peak memory 202320 kb
Host smart-ab0cd7cb-f364-4bed-b92c-67f0fbf095c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704985194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2704985194
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2737793221
Short name T654
Test name
Test status
Simulation time 331143482485 ps
CPU time 55.46 seconds
Started May 07 03:27:57 PM PDT 24
Finished May 07 03:28:53 PM PDT 24
Peak memory 202320 kb
Host smart-6dada1d8-0f37-42fb-9d6f-8b14e4d68c47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737793221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2737793221
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2871113012
Short name T147
Test name
Test status
Simulation time 495142853097 ps
CPU time 91.12 seconds
Started May 07 03:27:57 PM PDT 24
Finished May 07 03:29:29 PM PDT 24
Peak memory 202376 kb
Host smart-bd8e02ea-ec9d-44ca-a15f-cb5d5f17bac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871113012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2871113012
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3430507489
Short name T442
Test name
Test status
Simulation time 488735474936 ps
CPU time 301.34 seconds
Started May 07 03:28:02 PM PDT 24
Finished May 07 03:33:04 PM PDT 24
Peak memory 202304 kb
Host smart-84f5c0bc-8498-4959-a61b-c2eb24bbab5b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430507489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3430507489
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3369617571
Short name T193
Test name
Test status
Simulation time 549217509056 ps
CPU time 309.18 seconds
Started May 07 03:27:56 PM PDT 24
Finished May 07 03:33:06 PM PDT 24
Peak memory 202316 kb
Host smart-e737c162-3915-4e52-af24-c7edfd725ef4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369617571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3369617571
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3069125066
Short name T621
Test name
Test status
Simulation time 404991928812 ps
CPU time 889.87 seconds
Started May 07 03:27:56 PM PDT 24
Finished May 07 03:42:47 PM PDT 24
Peak memory 202404 kb
Host smart-56817e49-ec90-479f-a160-e3f38c77d2b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069125066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3069125066
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1014389752
Short name T673
Test name
Test status
Simulation time 115765245038 ps
CPU time 666.59 seconds
Started May 07 03:28:00 PM PDT 24
Finished May 07 03:39:07 PM PDT 24
Peak memory 202696 kb
Host smart-bf8eab03-9414-4ec6-a40b-3bd30dd9e56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014389752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1014389752
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.455945366
Short name T532
Test name
Test status
Simulation time 29076029821 ps
CPU time 71.58 seconds
Started May 07 03:28:03 PM PDT 24
Finished May 07 03:29:15 PM PDT 24
Peak memory 202172 kb
Host smart-4bc39d6d-4a03-4fc7-91d3-11f8000e9d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455945366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.455945366
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1887447734
Short name T530
Test name
Test status
Simulation time 3783761922 ps
CPU time 2.69 seconds
Started May 07 03:27:57 PM PDT 24
Finished May 07 03:28:00 PM PDT 24
Peak memory 202132 kb
Host smart-6634d087-7bac-4691-b892-0a3fa438ea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887447734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1887447734
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1935834691
Short name T340
Test name
Test status
Simulation time 5612693044 ps
CPU time 3.76 seconds
Started May 07 03:27:55 PM PDT 24
Finished May 07 03:28:00 PM PDT 24
Peak memory 202148 kb
Host smart-f0587f8e-54de-43e0-aeec-17db96ea9122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935834691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1935834691
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1235546493
Short name T454
Test name
Test status
Simulation time 170675363910 ps
CPU time 425.15 seconds
Started May 07 03:28:03 PM PDT 24
Finished May 07 03:35:08 PM PDT 24
Peak memory 202296 kb
Host smart-c8a84ec2-7a31-4b38-b24a-35e064fc5733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235546493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1235546493
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3436917292
Short name T448
Test name
Test status
Simulation time 522415028 ps
CPU time 1.56 seconds
Started May 07 03:28:05 PM PDT 24
Finished May 07 03:28:08 PM PDT 24
Peak memory 201996 kb
Host smart-b1294c5c-ad51-4837-b606-20b7bcc7ad0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436917292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3436917292
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.128482420
Short name T720
Test name
Test status
Simulation time 159222886517 ps
CPU time 32.54 seconds
Started May 07 03:28:07 PM PDT 24
Finished May 07 03:28:40 PM PDT 24
Peak memory 202316 kb
Host smart-46e724a1-11a3-4d17-bd39-e286c763f98e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128482420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.128482420
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2005726039
Short name T315
Test name
Test status
Simulation time 167269291652 ps
CPU time 396.22 seconds
Started May 07 03:28:07 PM PDT 24
Finished May 07 03:34:44 PM PDT 24
Peak memory 202312 kb
Host smart-394966fd-c486-42d8-ac65-17b8f00569c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005726039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2005726039
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2900281030
Short name T314
Test name
Test status
Simulation time 162737211156 ps
CPU time 134.96 seconds
Started May 07 03:28:07 PM PDT 24
Finished May 07 03:30:23 PM PDT 24
Peak memory 202412 kb
Host smart-9445cf3d-f089-45ce-b6fa-82ff153dfb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900281030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2900281030
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3117996515
Short name T382
Test name
Test status
Simulation time 163178983911 ps
CPU time 281.3 seconds
Started May 07 03:28:08 PM PDT 24
Finished May 07 03:32:50 PM PDT 24
Peak memory 202280 kb
Host smart-aae3b2cf-0d04-48b3-b380-93210d9f7268
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117996515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3117996515
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3856934918
Short name T186
Test name
Test status
Simulation time 326722673614 ps
CPU time 128.3 seconds
Started May 07 03:28:00 PM PDT 24
Finished May 07 03:30:09 PM PDT 24
Peak memory 202272 kb
Host smart-36fee62b-d72b-4de0-96fa-6b0a6648eb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856934918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3856934918
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2887469620
Short name T362
Test name
Test status
Simulation time 163609718972 ps
CPU time 172.43 seconds
Started May 07 03:28:06 PM PDT 24
Finished May 07 03:30:59 PM PDT 24
Peak memory 202304 kb
Host smart-cf069738-4458-47b7-9dd8-9c35a3f3d9ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887469620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2887469620
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3650706013
Short name T588
Test name
Test status
Simulation time 613505464872 ps
CPU time 1426.95 seconds
Started May 07 03:28:06 PM PDT 24
Finished May 07 03:51:54 PM PDT 24
Peak memory 202324 kb
Host smart-13b4207b-40a3-48f2-b977-6bc0e991be47
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650706013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3650706013
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.4114641572
Short name T384
Test name
Test status
Simulation time 40939124260 ps
CPU time 9.42 seconds
Started May 07 03:28:07 PM PDT 24
Finished May 07 03:28:18 PM PDT 24
Peak memory 202120 kb
Host smart-00cabd0c-5f79-4f3b-9014-4bd427b8a5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114641572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.4114641572
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1857928406
Short name T764
Test name
Test status
Simulation time 3196508351 ps
CPU time 9.21 seconds
Started May 07 03:28:08 PM PDT 24
Finished May 07 03:28:18 PM PDT 24
Peak memory 202132 kb
Host smart-92cc107a-ec62-42b4-894e-61d16a0e8d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857928406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1857928406
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3964933463
Short name T91
Test name
Test status
Simulation time 6126267773 ps
CPU time 8.2 seconds
Started May 07 03:28:02 PM PDT 24
Finished May 07 03:28:11 PM PDT 24
Peak memory 202156 kb
Host smart-a5aeb0ee-d3cb-431a-8d4d-84b41c80baf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964933463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3964933463
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3535691032
Short name T715
Test name
Test status
Simulation time 392240493237 ps
CPU time 207.53 seconds
Started May 07 03:28:07 PM PDT 24
Finished May 07 03:31:36 PM PDT 24
Peak memory 202308 kb
Host smart-64d969d8-74d3-41ee-9076-98512e4c0576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535691032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3535691032
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.120231061
Short name T590
Test name
Test status
Simulation time 73879694173 ps
CPU time 101.46 seconds
Started May 07 03:28:07 PM PDT 24
Finished May 07 03:29:50 PM PDT 24
Peak memory 210984 kb
Host smart-c1cb0893-dcb3-4fa8-8812-88db7bbf0151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120231061 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.120231061
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1522160709
Short name T4
Test name
Test status
Simulation time 334207646 ps
CPU time 1.02 seconds
Started May 07 03:28:15 PM PDT 24
Finished May 07 03:28:17 PM PDT 24
Peak memory 202040 kb
Host smart-b1b22aa9-f9c3-4028-8457-41010ee3c1d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522160709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1522160709
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.4278626918
Short name T432
Test name
Test status
Simulation time 162514095620 ps
CPU time 397.6 seconds
Started May 07 03:28:11 PM PDT 24
Finished May 07 03:34:49 PM PDT 24
Peak memory 202328 kb
Host smart-bb5ae809-05ed-4dc3-97bf-f13337879ba6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278626918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.4278626918
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1160859463
Short name T783
Test name
Test status
Simulation time 160398475442 ps
CPU time 98.28 seconds
Started May 07 03:28:11 PM PDT 24
Finished May 07 03:29:50 PM PDT 24
Peak memory 202392 kb
Host smart-e0b43c5a-1a83-4a9e-b7fa-1f2efd9058dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160859463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1160859463
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1691950558
Short name T710
Test name
Test status
Simulation time 163857939080 ps
CPU time 355.94 seconds
Started May 07 03:28:12 PM PDT 24
Finished May 07 03:34:09 PM PDT 24
Peak memory 202324 kb
Host smart-20f8a6e2-d243-4ef8-b27b-2a0cb0b041ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691950558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1691950558
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3311595079
Short name T272
Test name
Test status
Simulation time 506017426324 ps
CPU time 300.85 seconds
Started May 07 03:28:12 PM PDT 24
Finished May 07 03:33:14 PM PDT 24
Peak memory 202432 kb
Host smart-6e5470f0-2f5f-4510-b187-23bb0fae2f3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311595079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3311595079
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.822740962
Short name T509
Test name
Test status
Simulation time 601115945829 ps
CPU time 211.79 seconds
Started May 07 03:28:10 PM PDT 24
Finished May 07 03:31:43 PM PDT 24
Peak memory 202384 kb
Host smart-efd71bdb-23ed-41ed-8a8e-ff0db0e42a53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822740962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.822740962
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3720734248
Short name T48
Test name
Test status
Simulation time 83024173246 ps
CPU time 318.88 seconds
Started May 07 03:28:16 PM PDT 24
Finished May 07 03:33:36 PM PDT 24
Peak memory 202700 kb
Host smart-f49dcd1b-85be-4762-a2f5-ae7053d4e68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720734248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3720734248
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1555293500
Short name T3
Test name
Test status
Simulation time 34270263015 ps
CPU time 82.87 seconds
Started May 07 03:28:14 PM PDT 24
Finished May 07 03:29:37 PM PDT 24
Peak memory 202112 kb
Host smart-2f1113ff-9d4e-4ae5-ab29-671f5e79c8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555293500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1555293500
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3209594300
Short name T394
Test name
Test status
Simulation time 3706079119 ps
CPU time 4.29 seconds
Started May 07 03:28:17 PM PDT 24
Finished May 07 03:28:21 PM PDT 24
Peak memory 202140 kb
Host smart-0064c9ba-c461-4cda-8de2-0eb6f434827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209594300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3209594300
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2155829683
Short name T144
Test name
Test status
Simulation time 5650555354 ps
CPU time 15.36 seconds
Started May 07 03:28:11 PM PDT 24
Finished May 07 03:28:27 PM PDT 24
Peak memory 202308 kb
Host smart-afe33702-ba15-4935-821a-0b376286d975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155829683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2155829683
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1207748157
Short name T81
Test name
Test status
Simulation time 167569549843 ps
CPU time 250.18 seconds
Started May 07 03:28:15 PM PDT 24
Finished May 07 03:32:25 PM PDT 24
Peak memory 211048 kb
Host smart-cecf4f99-ba26-4b54-858d-c4068408732f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207748157 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1207748157
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1938943868
Short name T587
Test name
Test status
Simulation time 338459613 ps
CPU time 1.44 seconds
Started May 07 03:28:30 PM PDT 24
Finished May 07 03:28:32 PM PDT 24
Peak memory 202008 kb
Host smart-86c148cc-4548-4b7e-a976-1bd8cb23fac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938943868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1938943868
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3772018779
Short name T177
Test name
Test status
Simulation time 329618830162 ps
CPU time 54.76 seconds
Started May 07 03:28:27 PM PDT 24
Finished May 07 03:29:22 PM PDT 24
Peak memory 202356 kb
Host smart-6db2321c-3cf1-4a55-95cd-18ff0ed0b5e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772018779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3772018779
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1310379756
Short name T714
Test name
Test status
Simulation time 517845165643 ps
CPU time 329.03 seconds
Started May 07 03:28:25 PM PDT 24
Finished May 07 03:33:54 PM PDT 24
Peak memory 202352 kb
Host smart-8c387852-d84b-48ab-a67a-1c60a0105e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310379756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1310379756
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2315265283
Short name T635
Test name
Test status
Simulation time 484485610282 ps
CPU time 306.71 seconds
Started May 07 03:28:28 PM PDT 24
Finished May 07 03:33:36 PM PDT 24
Peak memory 202320 kb
Host smart-7abd0934-06f5-478d-901a-08556e875698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315265283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2315265283
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2681706668
Short name T426
Test name
Test status
Simulation time 167310047897 ps
CPU time 104.65 seconds
Started May 07 03:28:25 PM PDT 24
Finished May 07 03:30:11 PM PDT 24
Peak memory 202324 kb
Host smart-1d52da4c-9aef-4fd6-ada3-bc6265075a20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681706668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2681706668
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2965624075
Short name T322
Test name
Test status
Simulation time 326717567853 ps
CPU time 382.16 seconds
Started May 07 03:28:24 PM PDT 24
Finished May 07 03:34:46 PM PDT 24
Peak memory 202348 kb
Host smart-334daeaa-6332-4046-a417-6095054dfbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965624075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2965624075
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3590652716
Short name T398
Test name
Test status
Simulation time 167018245574 ps
CPU time 85.26 seconds
Started May 07 03:28:22 PM PDT 24
Finished May 07 03:29:48 PM PDT 24
Peak memory 202300 kb
Host smart-60bc72a7-b753-4c41-8276-c40138b74a4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590652716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3590652716
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.4242178583
Short name T678
Test name
Test status
Simulation time 186423264038 ps
CPU time 441.31 seconds
Started May 07 03:28:25 PM PDT 24
Finished May 07 03:35:48 PM PDT 24
Peak memory 202336 kb
Host smart-85e8a914-e338-47d6-9a75-a0701876f1ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242178583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.4242178583
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.173791300
Short name T776
Test name
Test status
Simulation time 594629926087 ps
CPU time 375.2 seconds
Started May 07 03:28:30 PM PDT 24
Finished May 07 03:34:47 PM PDT 24
Peak memory 202296 kb
Host smart-1775e1b6-b4d8-49f7-bd78-409cbf9eae48
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173791300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.173791300
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3007427615
Short name T618
Test name
Test status
Simulation time 84235239830 ps
CPU time 427.14 seconds
Started May 07 03:28:31 PM PDT 24
Finished May 07 03:35:39 PM PDT 24
Peak memory 202728 kb
Host smart-45f0255c-347f-49b7-9ab3-e9a0b8c9ab8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007427615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3007427615
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.4218555183
Short name T339
Test name
Test status
Simulation time 44934859117 ps
CPU time 99.02 seconds
Started May 07 03:28:28 PM PDT 24
Finished May 07 03:30:08 PM PDT 24
Peak memory 202144 kb
Host smart-c8931343-09b2-41e4-b15a-8d983a5cfdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218555183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.4218555183
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1436425870
Short name T173
Test name
Test status
Simulation time 3808349163 ps
CPU time 3.48 seconds
Started May 07 03:28:27 PM PDT 24
Finished May 07 03:28:31 PM PDT 24
Peak memory 202140 kb
Host smart-3ca62b08-8113-40dd-8e73-11c72ce06884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436425870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1436425870
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3385892112
Short name T793
Test name
Test status
Simulation time 5856207725 ps
CPU time 3.65 seconds
Started May 07 03:28:23 PM PDT 24
Finished May 07 03:28:27 PM PDT 24
Peak memory 202160 kb
Host smart-48518f33-1eda-45a9-b825-737eb543700e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385892112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3385892112
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2628067346
Short name T279
Test name
Test status
Simulation time 405322745364 ps
CPU time 277.67 seconds
Started May 07 03:28:31 PM PDT 24
Finished May 07 03:33:09 PM PDT 24
Peak memory 202340 kb
Host smart-222e6951-6bed-4e70-964a-0328fcd20ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628067346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2628067346
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2996130321
Short name T690
Test name
Test status
Simulation time 446439094 ps
CPU time 0.87 seconds
Started May 07 03:25:09 PM PDT 24
Finished May 07 03:25:11 PM PDT 24
Peak memory 201940 kb
Host smart-c3cc68bc-3732-4210-9057-f06ce072204c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996130321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2996130321
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1652128357
Short name T139
Test name
Test status
Simulation time 170811036647 ps
CPU time 93.8 seconds
Started May 07 03:25:07 PM PDT 24
Finished May 07 03:26:42 PM PDT 24
Peak memory 202392 kb
Host smart-67eb5892-a0c5-4963-8b4d-4cbdeae4476c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652128357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1652128357
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2155751225
Short name T651
Test name
Test status
Simulation time 533297340602 ps
CPU time 979.03 seconds
Started May 07 03:25:10 PM PDT 24
Finished May 07 03:41:31 PM PDT 24
Peak memory 202320 kb
Host smart-7df1a3ed-201c-43d1-a5f1-f10c0a940ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155751225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2155751225
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.998882861
Short name T645
Test name
Test status
Simulation time 162493819371 ps
CPU time 108.78 seconds
Started May 07 03:25:06 PM PDT 24
Finished May 07 03:26:56 PM PDT 24
Peak memory 202340 kb
Host smart-a2375652-efa6-4d3d-9e87-3b4bbcc12e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998882861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.998882861
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.628717935
Short name T631
Test name
Test status
Simulation time 165873494770 ps
CPU time 38.91 seconds
Started May 07 03:25:02 PM PDT 24
Finished May 07 03:25:42 PM PDT 24
Peak memory 202488 kb
Host smart-fb8ccdc9-38ab-4bf1-acd3-3d906dde7799
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=628717935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.628717935
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3376561582
Short name T259
Test name
Test status
Simulation time 335526421873 ps
CPU time 203.86 seconds
Started May 07 03:25:10 PM PDT 24
Finished May 07 03:28:35 PM PDT 24
Peak memory 202368 kb
Host smart-95924858-668e-47a8-8159-fb89e83489ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376561582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3376561582
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2313216681
Short name T555
Test name
Test status
Simulation time 494156396781 ps
CPU time 1103.54 seconds
Started May 07 03:25:03 PM PDT 24
Finished May 07 03:43:28 PM PDT 24
Peak memory 202328 kb
Host smart-ebe2104c-0fd9-4e1f-9b69-561ff0b18e68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313216681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2313216681
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1791554122
Short name T730
Test name
Test status
Simulation time 289212101239 ps
CPU time 339.48 seconds
Started May 07 03:25:07 PM PDT 24
Finished May 07 03:30:48 PM PDT 24
Peak memory 202348 kb
Host smart-378eec2b-9a97-482c-8b48-adf6b1bae2dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791554122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1791554122
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.4210005686
Short name T543
Test name
Test status
Simulation time 194944903721 ps
CPU time 81.11 seconds
Started May 07 03:25:04 PM PDT 24
Finished May 07 03:26:26 PM PDT 24
Peak memory 202296 kb
Host smart-9b3739b5-765e-4ba5-a50b-13e2547516b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210005686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.4210005686
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3967065754
Short name T189
Test name
Test status
Simulation time 32809227897 ps
CPU time 39.46 seconds
Started May 07 03:25:07 PM PDT 24
Finished May 07 03:25:48 PM PDT 24
Peak memory 202140 kb
Host smart-37486439-c7f1-4902-816f-6be240e5c61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967065754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3967065754
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2063368617
Short name T612
Test name
Test status
Simulation time 3980296574 ps
CPU time 5.4 seconds
Started May 07 03:25:08 PM PDT 24
Finished May 07 03:25:15 PM PDT 24
Peak memory 202136 kb
Host smart-8eb7d3f5-f3c3-40be-a75f-9bd65cd8489e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063368617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2063368617
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1404595600
Short name T797
Test name
Test status
Simulation time 5799813460 ps
CPU time 15.09 seconds
Started May 07 03:25:03 PM PDT 24
Finished May 07 03:25:20 PM PDT 24
Peak memory 202132 kb
Host smart-d177d8ed-7836-4f09-9abc-ede84b24172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404595600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1404595600
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2516387993
Short name T153
Test name
Test status
Simulation time 333558297489 ps
CPU time 184.97 seconds
Started May 07 03:25:08 PM PDT 24
Finished May 07 03:28:14 PM PDT 24
Peak memory 202408 kb
Host smart-7d76444c-cfca-4e9a-880b-d0c08b526b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516387993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2516387993
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2249494561
Short name T200
Test name
Test status
Simulation time 67749183518 ps
CPU time 152.44 seconds
Started May 07 03:25:08 PM PDT 24
Finished May 07 03:27:42 PM PDT 24
Peak memory 210680 kb
Host smart-14cf2d39-ed4e-4a79-bbdc-d83ab980451d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249494561 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2249494561
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.4227617758
Short name T358
Test name
Test status
Simulation time 371509012 ps
CPU time 1.51 seconds
Started May 07 03:25:08 PM PDT 24
Finished May 07 03:25:11 PM PDT 24
Peak memory 201996 kb
Host smart-b7144b1e-2835-4f8b-8261-7a2182e8bfed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227617758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.4227617758
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1027130651
Short name T138
Test name
Test status
Simulation time 525069952186 ps
CPU time 1217.06 seconds
Started May 07 03:25:08 PM PDT 24
Finished May 07 03:45:26 PM PDT 24
Peak memory 202308 kb
Host smart-17399acd-f1d0-4695-a54a-92df21bbb5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027130651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1027130651
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.769408439
Short name T145
Test name
Test status
Simulation time 159071981482 ps
CPU time 366.2 seconds
Started May 07 03:25:06 PM PDT 24
Finished May 07 03:31:14 PM PDT 24
Peak memory 202296 kb
Host smart-4d19899a-5dfb-4450-9678-1adf9bb587ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769408439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.769408439
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2789924920
Short name T661
Test name
Test status
Simulation time 492644824496 ps
CPU time 823.86 seconds
Started May 07 03:25:07 PM PDT 24
Finished May 07 03:38:52 PM PDT 24
Peak memory 202308 kb
Host smart-015dadfa-e219-4942-bc9f-42cced15a144
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789924920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2789924920
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.573294151
Short name T526
Test name
Test status
Simulation time 327826014712 ps
CPU time 796.51 seconds
Started May 07 03:25:07 PM PDT 24
Finished May 07 03:38:25 PM PDT 24
Peak memory 202308 kb
Host smart-dfdbcf56-fb5d-4c9b-a47d-758e7a1035f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573294151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.573294151
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3109738336
Short name T683
Test name
Test status
Simulation time 326013828620 ps
CPU time 187.48 seconds
Started May 07 03:25:09 PM PDT 24
Finished May 07 03:28:18 PM PDT 24
Peak memory 202328 kb
Host smart-27d33144-7fbd-4c2d-b1f8-b24c7c21c2a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109738336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3109738336
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2048358418
Short name T235
Test name
Test status
Simulation time 517704373745 ps
CPU time 213.6 seconds
Started May 07 03:25:13 PM PDT 24
Finished May 07 03:28:47 PM PDT 24
Peak memory 202400 kb
Host smart-ed144bcc-a0c7-4e18-b359-6842e4547d52
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048358418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2048358418
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2545128911
Short name T659
Test name
Test status
Simulation time 392016180966 ps
CPU time 146.15 seconds
Started May 07 03:25:09 PM PDT 24
Finished May 07 03:27:36 PM PDT 24
Peak memory 202348 kb
Host smart-156b4fca-cf3a-44cc-9408-4e64393c1bfa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545128911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2545128911
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2194150399
Short name T47
Test name
Test status
Simulation time 83365825208 ps
CPU time 431.77 seconds
Started May 07 03:25:08 PM PDT 24
Finished May 07 03:32:21 PM PDT 24
Peak memory 202744 kb
Host smart-3117bbd4-28fb-42d2-8255-f4ebb23ad56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194150399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2194150399
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1658277086
Short name T452
Test name
Test status
Simulation time 30473830906 ps
CPU time 16.47 seconds
Started May 07 03:25:08 PM PDT 24
Finished May 07 03:25:26 PM PDT 24
Peak memory 202156 kb
Host smart-6e0ed5ce-9a42-4708-89c6-3459b4d7526c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658277086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1658277086
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2066496773
Short name T77
Test name
Test status
Simulation time 3846637250 ps
CPU time 5.3 seconds
Started May 07 03:25:06 PM PDT 24
Finished May 07 03:25:12 PM PDT 24
Peak memory 202124 kb
Host smart-5a959622-34cd-4fc7-ac7c-75e8615c7b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066496773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2066496773
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3187447639
Short name T143
Test name
Test status
Simulation time 5664235584 ps
CPU time 2.38 seconds
Started May 07 03:25:09 PM PDT 24
Finished May 07 03:25:13 PM PDT 24
Peak memory 202168 kb
Host smart-7699894d-d338-4758-b55e-c092f32323fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187447639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3187447639
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1296111154
Short name T592
Test name
Test status
Simulation time 247564017520 ps
CPU time 498.41 seconds
Started May 07 03:25:10 PM PDT 24
Finished May 07 03:33:30 PM PDT 24
Peak memory 219064 kb
Host smart-43176805-78a5-40fa-a899-7f4b333847dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296111154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1296111154
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2740146909
Short name T463
Test name
Test status
Simulation time 513981945 ps
CPU time 0.88 seconds
Started May 07 03:25:07 PM PDT 24
Finished May 07 03:25:10 PM PDT 24
Peak memory 201956 kb
Host smart-2510191d-ebd7-46f6-85f3-b183c2673973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740146909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2740146909
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.696300545
Short name T637
Test name
Test status
Simulation time 167912526786 ps
CPU time 388.3 seconds
Started May 07 03:25:09 PM PDT 24
Finished May 07 03:31:39 PM PDT 24
Peak memory 202380 kb
Host smart-5fae5b11-9cdc-46bf-983b-d37df84025fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696300545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.696300545
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2079959693
Short name T468
Test name
Test status
Simulation time 325085603195 ps
CPU time 825.19 seconds
Started May 07 03:25:07 PM PDT 24
Finished May 07 03:38:54 PM PDT 24
Peak memory 202292 kb
Host smart-7bb2cfb9-1a1b-4b8c-811a-274c2ea3cc93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079959693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2079959693
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2415738844
Short name T514
Test name
Test status
Simulation time 323265129143 ps
CPU time 381.05 seconds
Started May 07 03:25:10 PM PDT 24
Finished May 07 03:31:32 PM PDT 24
Peak memory 202284 kb
Host smart-7a2f74e2-9c9b-4236-9c57-6247d6d0502e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415738844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2415738844
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.647934650
Short name T778
Test name
Test status
Simulation time 185045378482 ps
CPU time 107.71 seconds
Started May 07 03:25:06 PM PDT 24
Finished May 07 03:26:55 PM PDT 24
Peak memory 202316 kb
Host smart-66b59916-3fac-4103-9f12-2bf0d9a6dd68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647934650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.647934650
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2609651223
Short name T97
Test name
Test status
Simulation time 205195907923 ps
CPU time 443.23 seconds
Started May 07 03:25:05 PM PDT 24
Finished May 07 03:32:30 PM PDT 24
Peak memory 202324 kb
Host smart-e0bfb214-c9c8-4db0-a23a-5183561552c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609651223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2609651223
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.665356619
Short name T329
Test name
Test status
Simulation time 70130969557 ps
CPU time 280.33 seconds
Started May 07 03:25:09 PM PDT 24
Finished May 07 03:29:51 PM PDT 24
Peak memory 202752 kb
Host smart-6a8799b5-99a3-46cf-8e08-315881bc4ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665356619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.665356619
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.4082361578
Short name T479
Test name
Test status
Simulation time 42732234765 ps
CPU time 28.7 seconds
Started May 07 03:25:11 PM PDT 24
Finished May 07 03:25:41 PM PDT 24
Peak memory 202140 kb
Host smart-477a5998-703d-49c9-b41f-bb064f1cb8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082361578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.4082361578
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.135857745
Short name T132
Test name
Test status
Simulation time 3476157743 ps
CPU time 2.64 seconds
Started May 07 03:25:05 PM PDT 24
Finished May 07 03:25:09 PM PDT 24
Peak memory 202144 kb
Host smart-3bddf201-2c74-45c3-afeb-e30464d6db55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135857745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.135857745
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1345001110
Short name T359
Test name
Test status
Simulation time 6093637299 ps
CPU time 8.25 seconds
Started May 07 03:25:07 PM PDT 24
Finished May 07 03:25:17 PM PDT 24
Peak memory 202116 kb
Host smart-c15e972e-3e74-48d9-91d6-5d5527236b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345001110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1345001110
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2002167735
Short name T427
Test name
Test status
Simulation time 212658818704 ps
CPU time 429.08 seconds
Started May 07 03:25:09 PM PDT 24
Finished May 07 03:32:19 PM PDT 24
Peak memory 202260 kb
Host smart-febeaa50-7d61-42a1-8735-ed7f71c70d50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002167735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2002167735
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.679604187
Short name T601
Test name
Test status
Simulation time 24486249802 ps
CPU time 67.66 seconds
Started May 07 03:25:06 PM PDT 24
Finished May 07 03:26:15 PM PDT 24
Peak memory 210928 kb
Host smart-bf64a7b0-437c-4ae4-bf69-95807ae16907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679604187 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.679604187
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3104460244
Short name T378
Test name
Test status
Simulation time 484127945 ps
CPU time 1.84 seconds
Started May 07 03:25:14 PM PDT 24
Finished May 07 03:25:17 PM PDT 24
Peak memory 201988 kb
Host smart-96ce6a8c-8688-4300-b0be-3f18d7b173ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104460244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3104460244
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2855071672
Short name T603
Test name
Test status
Simulation time 349575840926 ps
CPU time 811.23 seconds
Started May 07 03:25:13 PM PDT 24
Finished May 07 03:38:45 PM PDT 24
Peak memory 202300 kb
Host smart-03257bbd-c2e4-4d0b-85f7-a99e98e9c46e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855071672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2855071672
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.763635701
Short name T694
Test name
Test status
Simulation time 487991711970 ps
CPU time 87.2 seconds
Started May 07 03:25:09 PM PDT 24
Finished May 07 03:26:38 PM PDT 24
Peak memory 202384 kb
Host smart-ab5fd42d-4051-484d-a756-66e3dac1a4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763635701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.763635701
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2550710890
Short name T667
Test name
Test status
Simulation time 329704828891 ps
CPU time 751.89 seconds
Started May 07 03:25:08 PM PDT 24
Finished May 07 03:37:41 PM PDT 24
Peak memory 202276 kb
Host smart-0bd5cbb1-818e-467b-a077-8fef1fbd74eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550710890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2550710890
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.4025113576
Short name T12
Test name
Test status
Simulation time 157859012099 ps
CPU time 63.01 seconds
Started May 07 03:25:09 PM PDT 24
Finished May 07 03:26:13 PM PDT 24
Peak memory 202388 kb
Host smart-86777c22-9146-4e74-98b3-659fc1e61325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025113576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.4025113576
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3521088687
Short name T511
Test name
Test status
Simulation time 163680652294 ps
CPU time 55.44 seconds
Started May 07 03:25:06 PM PDT 24
Finished May 07 03:26:03 PM PDT 24
Peak memory 202316 kb
Host smart-1b0605da-db33-46dc-b37b-293cf4a3b6b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521088687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3521088687
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1381496094
Short name T704
Test name
Test status
Simulation time 178092044733 ps
CPU time 44.32 seconds
Started May 07 03:25:10 PM PDT 24
Finished May 07 03:25:56 PM PDT 24
Peak memory 202352 kb
Host smart-f0241347-8226-4156-8230-2aa6e154410c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381496094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1381496094
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1542393152
Short name T767
Test name
Test status
Simulation time 393834575336 ps
CPU time 829.26 seconds
Started May 07 03:25:12 PM PDT 24
Finished May 07 03:39:02 PM PDT 24
Peak memory 202412 kb
Host smart-e88d97b3-24b5-4875-b12c-e7dead14b2ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542393152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1542393152
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1588524439
Short name T354
Test name
Test status
Simulation time 34443336838 ps
CPU time 7.67 seconds
Started May 07 03:25:14 PM PDT 24
Finished May 07 03:25:23 PM PDT 24
Peak memory 202148 kb
Host smart-c569ccf5-b1a4-4e86-9e9f-175c181f1712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588524439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1588524439
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.4190520164
Short name T672
Test name
Test status
Simulation time 3414450380 ps
CPU time 8.48 seconds
Started May 07 03:25:11 PM PDT 24
Finished May 07 03:25:21 PM PDT 24
Peak memory 202156 kb
Host smart-09caadfb-e637-4382-8c57-590ceb974011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190520164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.4190520164
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2816905330
Short name T467
Test name
Test status
Simulation time 5874021825 ps
CPU time 5.51 seconds
Started May 07 03:25:05 PM PDT 24
Finished May 07 03:25:12 PM PDT 24
Peak memory 202148 kb
Host smart-3fd3626a-cf58-40ef-a19b-9d4da8ca8744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816905330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2816905330
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.695061035
Short name T641
Test name
Test status
Simulation time 64014193240 ps
CPU time 274.58 seconds
Started May 07 03:25:12 PM PDT 24
Finished May 07 03:29:48 PM PDT 24
Peak memory 210940 kb
Host smart-c3f9eb8c-1628-44b7-93c9-abd80750c74c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695061035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.695061035
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3194901387
Short name T646
Test name
Test status
Simulation time 112306197600 ps
CPU time 249.79 seconds
Started May 07 03:25:20 PM PDT 24
Finished May 07 03:29:31 PM PDT 24
Peak memory 213136 kb
Host smart-598af484-4543-4e0b-b85c-20909ac8d8d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194901387 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3194901387
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3015688257
Short name T403
Test name
Test status
Simulation time 585798735 ps
CPU time 0.78 seconds
Started May 07 03:25:16 PM PDT 24
Finished May 07 03:25:18 PM PDT 24
Peak memory 202016 kb
Host smart-65ea3d37-9f71-487b-83cf-61cd64b423af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015688257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3015688257
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1163670188
Short name T166
Test name
Test status
Simulation time 513168633159 ps
CPU time 244.41 seconds
Started May 07 03:25:13 PM PDT 24
Finished May 07 03:29:18 PM PDT 24
Peak memory 201788 kb
Host smart-43110068-1543-41ab-811a-1544a8160f36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163670188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1163670188
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.4216381451
Short name T286
Test name
Test status
Simulation time 164387574897 ps
CPU time 101.64 seconds
Started May 07 03:25:09 PM PDT 24
Finished May 07 03:26:53 PM PDT 24
Peak memory 202332 kb
Host smart-ffc2a110-5225-460a-9678-86ab146a034d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216381451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.4216381451
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2299951058
Short name T691
Test name
Test status
Simulation time 162599054071 ps
CPU time 379.34 seconds
Started May 07 03:25:13 PM PDT 24
Finished May 07 03:31:34 PM PDT 24
Peak memory 202308 kb
Host smart-e648a521-ef8f-4f57-ac3c-baa7ba81bdfc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299951058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2299951058
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2169629988
Short name T417
Test name
Test status
Simulation time 163457077216 ps
CPU time 177.58 seconds
Started May 07 03:25:35 PM PDT 24
Finished May 07 03:28:34 PM PDT 24
Peak memory 201832 kb
Host smart-60b99b01-b6de-4465-bf7e-eebf4cd4d023
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169629988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2169629988
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.504801197
Short name T712
Test name
Test status
Simulation time 369640925004 ps
CPU time 837.98 seconds
Started May 07 03:25:25 PM PDT 24
Finished May 07 03:39:24 PM PDT 24
Peak memory 202348 kb
Host smart-5a04f7b2-9ff7-4eb6-821c-5e228d4ad618
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504801197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.504801197
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.493912338
Short name T387
Test name
Test status
Simulation time 202216901286 ps
CPU time 118.12 seconds
Started May 07 03:25:15 PM PDT 24
Finished May 07 03:27:14 PM PDT 24
Peak memory 202280 kb
Host smart-33ce9aa8-250a-48fb-bfac-3ab55642717b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493912338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.493912338
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.188696276
Short name T506
Test name
Test status
Simulation time 90427018972 ps
CPU time 350.43 seconds
Started May 07 03:25:11 PM PDT 24
Finished May 07 03:31:03 PM PDT 24
Peak memory 202756 kb
Host smart-b971879b-bdb9-4e4c-a9c8-6b66e5aaf2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188696276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.188696276
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2962462915
Short name T573
Test name
Test status
Simulation time 40700100295 ps
CPU time 94.25 seconds
Started May 07 03:25:10 PM PDT 24
Finished May 07 03:26:46 PM PDT 24
Peak memory 202132 kb
Host smart-5cfe6e14-c012-4c5a-bf50-f73eaa65995f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962462915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2962462915
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.43545307
Short name T357
Test name
Test status
Simulation time 3104788585 ps
CPU time 2.43 seconds
Started May 07 03:25:11 PM PDT 24
Finished May 07 03:25:15 PM PDT 24
Peak memory 202128 kb
Host smart-3745c520-95ab-407f-87dc-bd8d63f31f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43545307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.43545307
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3353159901
Short name T89
Test name
Test status
Simulation time 5672456727 ps
CPU time 3.99 seconds
Started May 07 03:25:13 PM PDT 24
Finished May 07 03:25:18 PM PDT 24
Peak memory 202084 kb
Host smart-6fcc1701-e963-460d-9e4f-b6bb46f2b480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353159901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3353159901
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3116054275
Short name T255
Test name
Test status
Simulation time 232934825221 ps
CPU time 560.81 seconds
Started May 07 03:25:10 PM PDT 24
Finished May 07 03:34:32 PM PDT 24
Peak memory 202344 kb
Host smart-90956c28-3620-49db-ad48-89906d5d3f38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116054275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3116054275
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1578139309
Short name T498
Test name
Test status
Simulation time 10658811117 ps
CPU time 26.09 seconds
Started May 07 03:25:23 PM PDT 24
Finished May 07 03:25:51 PM PDT 24
Peak memory 202432 kb
Host smart-b0a04062-5321-4270-a0c8-b765408e6c0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578139309 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1578139309
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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