Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6259	1			T5	6		T7	20		T9	20
testmodes[AdcCtrlTestmodeNormal]	4932	1			T1	1		T3	1		T5	4
testmodes[AdcCtrlTestmodeLowpower]	5014	1			T2	3		T4	2		T5	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3486	1			T5	3		T7	19		T9	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1553	1			T5	2		T10	4		T49	16
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1111	1			T5	1		T49	9		T13	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1577	1			T5	2		T10	4		T49	17
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1795	1			T5	1		T10	4		T49	7
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1225	1			T5	1		T49	12		T13	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1083	1			T5	1		T49	8		T13	16
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1250	1			T49	13		T13	14		T57	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2427	1			T2	2		T4	1		T5	3