Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20788

1

T2

21

T3

10

T5

23

auto[ADC_CTRL_FILTER_COND_OUT]

3481

1

T1

1

T2

14

T4

36

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18231

1

T2

10

T3

10

T4

36

auto[1]

6038

1

T1

1

T2

25

T5

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T43	1		T223	1		T224	12
values[0]	67	1			T225	30		T226	32		T24	5
values[1]	911	1			T6	26		T45	1		T144	8
values[2]	873	1			T4	36		T6	16		T78	1
values[3]	607	1			T2	14		T3	10		T5	6
values[4]	560	1			T43	23		T144	9		T155	9
values[5]	781	1			T2	11		T146	14		T35	2
values[6]	543	1			T146	3		T45	8		T150	11
values[7]	555	1			T158	14		T63	9		T159	13
values[8]	568	1			T56	1		T35	1		T45	16
values[9]	3497	1			T1	1		T2	10		T8	15
minimum	15293	1			T5	17		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1255	1			T6	26		T45	1		T144	8
values[1]	773	1			T3	10		T4	36		T6	16
values[2]	542	1			T2	14		T5	6		T146	1
values[3]	649	1			T146	14		T43	23		T144	9
values[4]	671	1			T2	11		T35	2		T45	8
values[5]	540	1			T146	3		T50	2		T157	28
values[6]	2768	1			T8	15		T11	1		T12	7
values[7]	659	1			T1	1		T56	1		T45	16
values[8]	926	1			T2	10		T13	1		T40	3
values[9]	193	1			T43	1		T62	24		T227	11
minimum	15293	1			T5	17		T7	20		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T6	13		T177	10		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	418	1			T6	13		T45	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	3		T6	16		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	18		T196	12		T148	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	5		T146	1		T179	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	14		T159	14		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T43	1		T158	1		T162	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T146	1		T43	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	11		T35	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T35	1		T45	8		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T146	1		T50	2		T157	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T51	4		T228	2		T207	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1497	1			T8	15		T11	1		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T35	1		T63	2		T229	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T45	16		T152	1		T164	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	1		T56	1		T230	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	10		T13	1		T144	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T40	3		T177	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T227	3		T231	1		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T43	1		T62	14		T203	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T177	9		T178	13		T233	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T144	7		T155	5		T151	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	7		T150	12		T233	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	18		T196	9		T148	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T5	1		T179	12		T160	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T157	12		T234	11		T235	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T43	11		T158	13		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T146	13		T43	10		T144	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T158	6		T150	10		T152	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T155	15		T230	6		T152	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T146	2		T157	14		T160	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T51	2		T228	6		T236	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T12	6		T158	13		T237	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T63	7		T238	6		T239	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T152	13		T164	12		T182	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T230	9		T163	15		T15	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T144	4		T145	15		T148	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T177	9		T150	5		T233	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T227	8		T240	12		T193	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T62	10		T241	3		T242	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T223	1		T224	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T43	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T225	15		T24	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T226	17		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	13		T177	10		T178	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T6	13		T45	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T6	16		T150	1		T64	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	18		T78	1		T196	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	3		T5	5		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	14		T159	14		T234	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T43	1		T162	7		T15	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T43	1		T144	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T2	11		T35	1		T158	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T146	1		T35	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T146	1		T150	1		T50	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T45	8		T163	13		T51	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T158	1		T159	13		T163	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T63	2		T243	12		T244	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T45	16		T178	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T56	1		T35	1		T230	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1666	1			T2	10		T8	15		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T1	1		T40	3		T62	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T224	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T225	15		T24	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T226	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T177	9		T178	13		T233	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T144	7		T155	5		T151	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T150	12		T64	8		T179	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	18		T196	9		T148	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	7		T5	1		T233	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T234	11		T149	2		T245	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T43	11		T162	6		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T43	10		T144	8		T155	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T158	19		T162	4		T152	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T146	13		T155	15		T178	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T146	2		T150	10		T160	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T51	2		T228	6		T170	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T158	13		T163	3		T166	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T63	7		T239	2		T246	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T178	2		T152	13		T164	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T230	9		T163	15		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1152	1			T12	6		T144	4		T145	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T62	10		T177	9		T150	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T6	1		T177	10		T178	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T6	1		T45	1		T144	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	8		T6	1		T150	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	20		T196	10		T148	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	3		T146	1		T179	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	1		T159	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T43	12		T158	14		T162	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T146	14		T43	11		T144	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	1		T35	1		T158	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T35	1		T45	1		T155	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T146	3		T50	2		T157	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T51	5		T228	7		T207	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T8	1		T11	1		T12	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T35	1		T63	8		T229	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T45	1		T152	14		T164	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	1		T56	1		T230	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T2	1		T13	1		T144	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T40	1		T177	10		T150	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T227	9		T231	1		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T43	1		T62	11		T203	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T6	12		T177	9		T233	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T6	12		T151	14		T165	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	2		T6	15		T233	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	16		T196	11		T148	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	3		T160	9		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	13		T159	13		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T162	19		T15	1		T25	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T64	2		T247	15		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T2	10		T153	5		T248	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T45	7		T159	12		T230	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T157	13		T160	3		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T51	1		T228	1		T244	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1159	1			T8	14		T55	19		T205	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T63	1		T243	11		T238	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T45	15		T164	22		T165	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T230	11		T163	5		T15	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	9		T144	7		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T40	2		T233	22		T26	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T227	2		T193	2		T249	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T62	13		T241	2		T250	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T223	1		T224	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T43	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T225	16		T24	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T226	16		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	1		T177	10		T178	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T6	1		T45	1		T144	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T6	1		T150	13		T64	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	20		T78	1		T196	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	8		T5	3		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T2	1		T159	1		T234	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T43	12		T162	7		T15	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T43	11		T144	9		T155	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T2	1		T35	1		T158	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T146	14		T35	1		T155	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T146	3		T150	11		T50	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T45	1		T163	1		T51	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T158	14		T159	1		T163	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T63	8		T243	1		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T45	1		T178	3		T152	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T56	1		T35	1		T230	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T2	1		T8	1		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T1	1		T40	1		T62	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T225	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T226	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	12		T177	9		T233	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T6	12		T151	14		T36	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	15		T64	10		T26	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	16		T196	11		T148	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	2		T5	3		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	13		T159	13		T149	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T162	6		T15	1		T251	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T64	2		T153	2		T157	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T2	10		T162	13		T153	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T159	12		T230	14		T252	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T160	3		T18	1		T221	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T45	7		T163	12		T51	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T159	12		T163	4		T166	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T63	1		T243	11		T244	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	15		T164	11		T165	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T230	11		T163	5		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T2	9		T8	14		T55	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T40	2		T62	13		T233	22

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20821

1

T1

1

T2

24

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3448

1

T2

11

T3

10

T4

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18147

1

T4

20

T5

23

T6

13

auto[1]

6122

1

T1

1

T2

35

T3

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	60	1			T146	3		T253	24		T238	5
values[0]	53	1			T43	11		T144	9		T254	6
values[1]	521	1			T146	1		T35	1		T144	12
values[2]	654	1			T1	1		T45	24		T151	1
values[3]	791	1			T35	1		T78	1		T158	14
values[4]	752	1			T13	1		T158	14		T153	28
values[5]	701	1			T3	10		T6	16		T40	3
values[6]	515	1			T2	24		T4	20		T6	13
values[7]	739	1			T4	16		T43	12		T144	8
values[8]	2817	1			T8	15		T11	1		T12	7
values[9]	1373	1			T2	11		T5	6		T6	13
minimum	15293	1			T5	17		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	695	1			T146	1		T35	1		T43	11
values[1]	608	1			T1	1		T45	16		T78	1
values[2]	874	1			T13	1		T158	28		T150	13
values[3]	794	1			T6	16		T35	1		T164	16
values[4]	497	1			T3	10		T6	13		T40	3
values[5]	685	1			T2	24		T144	8		T145	28
values[6]	2892	1			T4	36		T8	15		T11	1
values[7]	737	1			T6	13		T146	14		T62	24
values[8]	1024	1			T2	11		T5	6		T56	1
values[9]	135	1			T146	3		T255	15		T180	8
minimum	15328	1			T5	17		T7	20		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T146	1		T43	1		T45	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T35	1		T144	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	1		T45	16		T151	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T78	1		T163	6		T36	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	1		T158	2		T159	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T150	1		T178	1		T233	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T25	10		T160	10		T247	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	16		T35	1		T164	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	13		T155	2		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T3	3		T40	3		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	24		T230	12		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T144	1		T145	13		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1517	1			T4	9		T8	15		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	9		T43	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	13		T62	14		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T146	1		T177	10		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T35	1		T163	5		T50	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T2	11		T5	5		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T146	1		T180	8		T238	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T255	15		T256	10		T241	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15161	1			T5	13		T7	20		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T43	10		T144	4		T230	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T144	8		T158	6		T235	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T151	17		T26	10		T160	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T163	15		T248	13		T257	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T158	26		T235	7		T258	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T150	12		T178	2		T233	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T160	2		T247	15		T53	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T164	4		T153	23		T29	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T155	23		T150	10		T48	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T3	7		T63	7		T152	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T230	9		T152	5		T148	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T144	7		T145	15		T150	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T4	11		T12	6		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	7		T43	11		T155	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T62	10		T178	7		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T146	13		T177	9		T178	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T163	3		T227	8		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	1		T162	6		T64	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T146	2		T238	6		T259	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T241	3		T260	14		T261	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	4		T78	2		T148	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T146	1		T238	1		T262	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T253	13		T20	6		T263	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T43	1		T254	1		T264	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T144	1		T253	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T146	1		T144	8		T230	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T35	1		T158	1		T159	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	1		T45	24		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T163	6		T36	9		T248	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T158	1		T151	15		T159	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T35	1		T78	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T13	1		T158	1		T25	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T153	14		T157	18		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T155	2		T150	1		T48	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	3		T6	16		T40	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	24		T4	9		T6	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T43	1		T150	1		T179	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T177	1		T233	3		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T4	9		T43	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1530	1			T8	15		T11	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T177	10		T50	3		T265	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T6	13		T35	1		T62	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T2	11		T5	5		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T146	2		T238	4		T262	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T253	11		T20	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T43	10		T254	5		T264	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T144	8		T253	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T144	4		T230	6		T157	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T158	6		T235	14		T225	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T26	10		T160	9		T228	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T163	15		T248	13		T266	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T158	13		T151	17		T193	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T150	12		T178	2		T233	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T158	13		T160	2		T247	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T153	14		T157	12		T29	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T155	23		T150	10		T48	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	7		T63	7		T233	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T4	11		T230	9		T152	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T150	5		T179	12		T167	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T177	9		T233	3		T148	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	7		T43	11		T144	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T12	6		T237	17		T201	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T177	9		T50	2		T265	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T62	10		T178	7		T163	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T5	1		T146	13		T178	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2