Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20806

1

T1

1

T2

21

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3463

1

T2

14

T4

36

T6

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18317

1

T2

10

T3

10

T4

36

auto[1]

5952

1

T1

1

T2

25

T5

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	230	1			T62	24		T26	22		T168	1
values[0]	35	1			T17	3		T226	32		-	-
values[1]	951	1			T6	26		T45	1		T144	8
values[2]	865	1			T3	10		T4	16		T6	16
values[3]	570	1			T2	14		T4	20		T5	6
values[4]	606	1			T146	14		T43	23		T144	9
values[5]	786	1			T2	11		T35	2		T155	16
values[6]	511	1			T146	3		T45	8		T150	11
values[7]	548	1			T158	14		T63	9		T159	13
values[8]	570	1			T1	1		T56	1		T35	1
values[9]	3304	1			T2	10		T8	15		T11	1
minimum	15293	1			T5	17		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	914	1			T6	26		T45	1		T144	8
values[1]	782	1			T3	10		T4	36		T6	16
values[2]	536	1			T2	14		T5	6		T146	1
values[3]	635	1			T146	14		T43	23		T144	9
values[4]	714	1			T2	11		T35	2		T45	8
values[5]	521	1			T146	3		T163	13		T50	2
values[6]	2730	1			T8	15		T11	1		T12	7
values[7]	678	1			T1	1		T56	1		T45	16
values[8]	1068	1			T2	10		T13	1		T40	3
values[9]	59	1			T43	1		T62	24		T227	11
minimum	15632	1			T5	17		T7	20		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	13		T178	1		T233	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T6	13		T45	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	3		T6	16		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	18		T78	1		T196	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	5		T146	1		T165	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	14		T159	14		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T43	1		T158	1		T162	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T146	1		T43	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	11		T35	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T35	1		T45	8		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T146	1		T50	2		T160	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T163	13		T51	4		T228	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T8	15		T11	1		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T35	1		T63	2		T159	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	1		T45	16		T230	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T56	1		T163	6		T165	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T2	10		T40	3		T144	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T13	1		T177	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T227	3		T232	1		T240	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T43	1		T62	14		T241	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15223	1			T5	13		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T155	1		T177	10		T36	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T178	13		T233	3		T64	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T144	7		T151	17		T160	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	7		T150	12		T233	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	18		T196	9		T148	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T5	1		T16	1		T319	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T179	12		T157	12		T234	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T43	11		T158	13		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T146	13		T43	10		T144	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T158	6		T150	10		T152	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T155	15		T230	6		T152	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T146	2		T160	8		T235	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T51	2		T228	6		T170	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T12	6		T158	13		T237	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T63	7		T239	2		T246	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T230	9		T152	13		T164	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T163	15		T15	3		T154	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T144	4		T145	15		T148	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T177	9		T150	5		T233	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T227	8		T240	12		T320	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T62	10		T241	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	4		T78	2		T148	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T155	5		T177	9		T254	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T168	1		T170	3		T232	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T62	14		T26	12		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T17	3		T226	17		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	13		T178	1		T233	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T6	13		T45	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	3		T6	16		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	9		T78	1		T196	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	5		T146	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	14		T4	9		T153	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T43	1		T162	7		T153	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T146	1		T43	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T2	11		T35	1		T158	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T35	1		T155	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T146	1		T150	1		T50	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T45	8		T163	13		T51	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T158	1		T163	5		T166	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T63	2		T159	13		T50	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T45	16		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T56	1		T35	1		T163	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1671	1			T2	10		T8	15		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T13	1		T43	1		T177	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T170	9		T225	11		T240	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T62	10		T26	10		T294	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T226	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T178	13		T233	3		T64	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T144	7		T155	5		T177	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	7		T150	12		T64	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T4	7		T196	9		T148	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T5	1		T233	2		T153	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T4	11		T179	12		T234	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T43	11		T162	6		T153	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T146	13		T43	10		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T158	19		T162	4		T152	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T155	15		T178	7		T230	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T146	2		T150	10		T160	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T51	2		T228	6		T170	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T158	13		T163	3		T166	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T63	7		T239	2		T246	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T178	2		T230	9		T164	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T163	15		T15	3		T149	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1127	1			T12	6		T144	4		T145	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T177	9		T150	5		T233	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	1		T178	14		T233	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T6	1		T45	1		T144	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	8		T6	1		T150	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	20		T78	1		T196	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	3		T146	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	1		T159	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T43	12		T158	14		T162	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T146	14		T43	11		T144	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	1		T35	1		T158	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T35	1		T45	1		T155	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T146	3		T50	2		T160	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T163	1		T51	5		T228	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T8	1		T11	1		T12	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T35	1		T63	8		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	1		T45	1		T230	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T56	1		T163	16		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T2	1		T40	1		T144	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T13	1		T177	10		T150	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T227	9		T232	1		T240	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T43	1		T62	11		T241	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15373	1			T5	17		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T155	6		T177	10		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	12		T233	2		T230	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T6	12		T151	14		T165	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	2		T6	15		T233	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	16		T196	11		T148	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T5	3		T165	12		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	13		T159	13		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T162	19		T153	5		T15	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T64	2		T247	15		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T2	10		T157	13		T25	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T45	7		T159	12		T230	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T160	3		T221	9		T238	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T163	12		T51	1		T228	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1167	1			T8	14		T55	19		T205	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T63	1		T159	12		T239	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T45	15		T230	11		T164	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T163	5		T165	2		T15	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	9		T40	2		T144	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T233	22		T26	11		T255	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T227	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T62	13		T241	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T252	9		T225	14		T321	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T177	9		T36	8		T273	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T168	1		T170	10		T232	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T62	11		T26	11		T294	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T17	2		T226	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	1		T178	14		T233	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T6	1		T45	1		T144	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T3	8		T6	1		T150	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	8		T78	1		T196	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	3		T146	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	1		T4	12		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T43	12		T162	7		T153	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T146	14		T43	11		T144	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T2	1		T35	1		T158	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T35	1		T155	16		T178	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T146	3		T150	11		T50	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T45	1		T163	1		T51	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T158	14		T163	4		T166	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T63	8		T159	1		T50	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	1		T45	1		T178	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T56	1		T35	1		T163	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1488	1			T2	1		T8	1		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T13	1		T43	1		T177	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T170	2		T225	12		T20	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T62	13		T26	11		T306	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T17	1		T226	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	12		T233	2		T50	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T6	12		T177	9		T151	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	2		T6	15		T230	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	8		T196	11		T148	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	3		T233	12		T153	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	13		T4	8		T153	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T162	6		T153	5		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T159	13		T64	2		T157	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	10		T162	13		T157	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T159	12		T230	14		T252	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T160	3		T18	1		T221	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T45	7		T163	12		T51	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T163	4		T166	8		T245	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T63	1		T159	12		T243	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	15		T230	11		T164	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T163	5		T165	2		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T2	9		T8	14		T55	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T233	22		T255	14		T253	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16