Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18516

1

T1

1

T2

21

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

5753

1

T2

14

T4

16

T6

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18307

1

T2

11

T3

10

T4

36

auto[1]

5962

1

T1

1

T2

24

T5

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	286	1			T2	14		T3	10		T35	1
values[0]	22	1			T50	3		T15	7		T266	10
values[1]	519	1			T4	16		T56	1		T45	16
values[2]	760	1			T144	8		T158	14		T150	11
values[3]	768	1			T2	11		T4	20		T45	1
values[4]	585	1			T6	13		T43	1		T62	24
values[5]	782	1			T2	10		T35	1		T144	12
values[6]	646	1			T146	14		T43	23		T177	19
values[7]	528	1			T6	13		T146	4		T35	1
values[8]	674	1			T177	10		T163	13		T50	9
values[9]	3406	1			T1	1		T5	6		T6	16
minimum	15293	1			T5	17		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	574	1			T4	16		T45	16		T144	8
values[1]	3012	1			T2	11		T8	15		T11	1
values[2]	665	1			T4	20		T151	32		T159	13
values[3]	672	1			T6	13		T43	1		T145	28
values[4]	666	1			T2	10		T35	1		T43	12
values[5]	671	1			T146	14		T35	1		T43	11
values[6]	505	1			T6	13		T146	4		T45	8
values[7]	720	1			T13	1		T40	3		T162	13
values[8]	1148	1			T1	1		T2	14		T3	10
values[9]	165	1			T269	22		T170	28		T182	16
minimum	15471	1			T5	17		T7	20		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T158	1		T233	23		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T4	9		T45	16		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	11		T64	1		T163	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1591	1			T8	15		T11	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	9		T152	1		T234	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T151	15		T159	13		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	13		T155	1		T64	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T43	1		T145	13		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T2	10		T43	1		T144	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T35	1		T62	14		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T146	1		T162	14		T233	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T35	1		T43	1		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	13		T150	1		T159	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T146	2		T45	8		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T40	3		T163	13		T50	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T13	1		T162	7		T157	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T1	1		T3	3		T5	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T2	14		T6	16		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T269	12		T170	14		T182	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T240	1		T104	1		T263	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15213	1			T5	13		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T50	3		T15	4		T294	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T158	13		T233	20		T148	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T4	7		T144	7		T178	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T64	1		T163	15		T182	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1134	1			T12	6		T158	13		T237	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T4	11		T152	5		T234	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T151	17		T198	2		T48	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T155	15		T64	5		T58	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T145	15		T155	5		T158	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T43	11		T144	4		T155	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T62	10		T64	8		T153	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T146	13		T162	4		T233	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T43	10		T177	9		T160	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T150	5		T157	14		T29	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T146	2		T177	9		T167	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T16	1		T51	2		T278	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T162	6		T157	12		T247	29
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T3	7		T5	1		T144	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T50	2		T179	12		T265	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T269	10		T170	14		T182	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T240	12		T34	1		T314	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	4		T78	2		T148	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T15	3		T294	3		T266	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T3	3		T178	1		T165	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T2	14		T35	1		T251	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T315	1		T316	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T50	3		T15	4		T266	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T56	1		T158	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	9		T45	16		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T233	23		T64	1		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T144	1		T158	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	11		T4	9		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T45	1		T78	1		T159	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	13		T155	1		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T43	1		T62	14		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	10		T144	8		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T35	1		T145	13		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T146	1		T43	1		T233	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T43	1		T177	10		T50	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	13		T150	1		T162	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T146	2		T35	1		T45	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T163	13		T50	9		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T177	1		T157	18		T165	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	381	1			T1	1		T5	5		T40	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1666	1			T6	16		T8	15		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T3	7		T178	13		T53	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T34	3		T314	12		T320	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T15	3		T266	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T158	13		T148	8		T166	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T4	7		T178	7		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T233	20		T64	1		T235	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T144	7		T158	13		T150	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	11		T152	5		T163	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T148	15		T163	3		T48	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T155	15		T318	10		T272	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T62	10		T155	5		T151	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T144	4		T155	8		T230	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T145	15		T158	6		T150	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T146	13		T43	11		T233	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T43	10		T177	9		T160	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T150	5		T162	4		T157	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T146	2		T167	16		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T29	6		T53	1		T228	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T177	9		T157	12		T247	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T5	1		T144	8		T233	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1105	1			T12	6		T237	17		T201	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T158	14		T233	21		T148	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T4	8		T45	1		T144	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T2	1		T64	2		T163	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1483	1			T8	1		T11	1		T12	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	12		T152	6		T234	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T151	18		T159	1		T198	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	1		T155	16		T64	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T43	1		T145	16		T155	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	1		T43	12		T144	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T35	1		T62	11		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T146	14		T162	5		T233	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T35	1		T43	11		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T6	1		T150	6		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T146	4		T45	1		T177	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T40	1		T163	1		T50	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	1		T162	7		T157	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T1	1		T3	8		T5	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T2	1		T6	1		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T269	11		T170	15		T182	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T240	13		T104	1		T263	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15320	1			T5	17		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T50	3		T15	4		T294	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T233	22		T166	8		T248	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T4	8		T45	15		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T2	10		T163	5		T255	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1242	1			T8	14		T55	19		T205	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	8		T180	7		T252	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T151	14		T159	12		T153	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	12		T64	2		T58	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T145	12		T63	1		T230	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T2	9		T144	7		T230	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T62	13		T159	13		T64	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T162	13		T233	2		T153	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T177	9		T36	8		T160	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T6	12		T159	12		T157	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T45	7		T50	4		T244	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T40	2		T163	12		T50	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T162	6		T157	17		T165	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T3	2		T5	3		T233	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	13		T6	15		T50	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T269	11		T170	13		T182	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T314	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T160	9		T322	3		T284	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T15	3		T225	12		T241	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T3	8		T178	14		T165	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T2	1		T35	1		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T315	1		T316	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T50	3		T15	4		T266	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T56	1		T158	14		T148	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	8		T45	1		T178	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T233	21		T64	2		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T144	8		T158	14		T150	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	1		T4	12		T152	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T45	1		T78	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	1		T155	16		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T43	1		T62	11		T155	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	1		T144	5		T155	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T35	1		T145	16		T158	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T146	14		T43	12		T233	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T43	11		T177	10		T50	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T6	1		T150	6		T162	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T146	4		T35	1		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T163	1		T50	1		T29	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T177	10		T157	13		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T1	1		T5	3		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1466	1			T6	1		T8	1		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T3	2		T165	2		T279	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T2	13		T251	10		T311	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T15	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T166	8		T160	9		T248	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T4	8		T45	15		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T233	22		T255	19		T245	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T26	3		T19	1		T225	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	10		T4	8		T163	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T159	12		T148	13		T163	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	12		T252	14		T58	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T62	13		T151	14		T63	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	9		T144	7		T230	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T145	12		T159	13		T64	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T233	2		T164	11		T153	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T177	9		T36	8		T160	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	12		T162	13		T159	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T45	7		T50	4		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T163	12		T50	8		T228	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T157	17		T165	12		T247	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T5	3		T40	2		T233	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1305	1			T6	15		T8	14		T55	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16