Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20704

1

T2

25

T4

16

T5

17

auto[ADC_CTRL_FILTER_COND_OUT]

3565

1

T1

1

T2

10

T3

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18005

1

T2

24

T4

16

T5

17

auto[1]

6264

1

T1

1

T2

11

T3

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	757	1			T5	6		T6	29		T49	3
values[0]	53	1			T249	21		T309	5		T312	11
values[1]	725	1			T1	1		T146	14		T35	1
values[2]	2789	1			T4	16		T5	6		T8	15
values[3]	804	1			T3	10		T4	20		T35	1
values[4]	717	1			T43	12		T45	1		T144	8
values[5]	542	1			T43	1		T144	9		T233	6
values[6]	631	1			T2	24		T162	18		T233	43
values[7]	589	1			T2	11		T6	13		T13	1
values[8]	720	1			T155	16		T150	13		T151	32
values[9]	1011	1			T45	8		T144	12		T233	15
minimum	14931	1			T5	11		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	637	1			T5	6		T146	15		T145	28
values[1]	2862	1			T3	10		T4	16		T8	15
values[2]	845	1			T4	20		T144	8		T155	6
values[3]	602	1			T43	13		T45	1		T158	7
values[4]	703	1			T144	9		T162	18		T152	12
values[5]	583	1			T2	24		T6	13		T40	3
values[6]	513	1			T2	11		T13	1		T35	1
values[7]	829	1			T150	13		T151	32		T162	13
values[8]	948	1			T6	29		T146	3		T43	11
values[9]	239	1			T78	1		T294	4		T251	1
minimum	15508	1			T1	1		T5	17		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T146	1		T145	13		T64	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	5		T146	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1594	1			T4	9		T8	15		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T3	3		T56	1		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T144	1		T63	2		T230	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	9		T155	1		T15	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T158	1		T151	1		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T43	2		T45	1		T177	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T148	1		T164	12		T50	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T144	1		T162	14		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	14		T233	23		T159	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	10		T6	13		T40	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T2	11		T13	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T155	1		T157	18		T15	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T150	1		T162	7		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T151	15		T159	14		T163	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T6	29		T144	8		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T146	1		T43	1		T45	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T78	1		T58	1		T244	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T294	1		T251	1		T170	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15192	1			T5	13		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T1	1		T35	1		T278	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T145	15		T64	8		T26	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	1		T146	13		T158	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T4	7		T12	6		T62	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	7		T177	9		T150	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T144	7		T63	7		T153	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T4	11		T155	5		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T158	6		T178	2		T233	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T43	11		T177	9		T178	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T148	8		T164	4		T53	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T144	8		T162	4		T152	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T233	20		T160	8		T228	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T230	9		T50	2		T228	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T155	8		T178	7		T152	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T155	15		T157	12		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T150	12		T162	6		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T151	17		T163	15		T279	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T144	4		T152	13		T163	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T146	2		T43	10		T233	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T272	6		T323	2		T324	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T294	3		T170	9		T300	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	4		T78	2		T158	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T278	7		T235	14		T325	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	464	1			T5	6		T6	29		T49	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T146	1		T43	1		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T249	12		T262	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T309	5		T312	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T145	13		T158	1		T64	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	1		T146	1		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T4	9		T8	15		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T5	5		T56	1		T45	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T62	14		T63	2		T148	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	3		T4	9		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T144	1		T158	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T43	1		T45	1		T177	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T233	3		T164	12		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T43	1		T144	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	14		T233	23		T159	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	10		T162	14		T230	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	11		T13	1		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	13		T40	3		T157	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T150	1		T162	7		T167	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T155	1		T151	15		T163	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T144	8		T163	5		T50	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T45	8		T233	13		T159	27
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14791	1			T5	7		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T152	13		T252	10		T318	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T146	2		T43	10		T294	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T249	9		T262	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T145	15		T158	13		T64	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T146	13		T158	13		T164	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T4	7		T12	6		T237	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T5	1		T150	10		T154	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T62	10		T63	7		T148	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T3	7		T4	11		T155	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T144	7		T158	6		T178	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T43	11		T177	9		T178	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T233	3		T164	4		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T144	8		T152	11		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T233	20		T148	8		T160	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T162	4		T230	9		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T155	8		T178	7		T152	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T157	12		T248	11		T182	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T150	12		T162	6		T167	31
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T155	15		T151	17		T163	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T144	4		T163	3		T247	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T233	2		T64	5		T48	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T146	1		T145	16		T64	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	3		T146	14		T158	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T4	8		T8	1		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	8		T56	1		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T144	8		T63	8		T230	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T4	12		T155	6		T15	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T158	7		T151	1		T178	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T43	13		T45	1		T177	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T148	9		T164	5		T50	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T144	9		T162	5		T152	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T2	1		T233	21		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	1		T6	1		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	1		T13	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T155	16		T157	13		T15	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T150	13		T162	7		T198	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T151	18		T159	1		T163	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	2		T144	5		T152	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T146	3		T43	11		T45	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T78	1		T58	1		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T294	4		T251	1		T170	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15377	1			T5	17		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T1	1		T35	1		T278	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T145	12		T64	10		T26	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	3		T163	12		T164	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T4	8		T8	14		T55	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T3	2		T45	15		T248	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T63	1		T230	2		T153	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	8		T15	3		T252	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T233	2		T196	11		T148	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T177	9		T153	2		T50	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T164	11		T165	20		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T162	13		T18	1		T245	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	13		T233	22		T159	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	9		T6	12		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T2	10		T166	8		T26	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T157	17		T15	1		T244	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T162	6		T160	9		T247	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T151	14		T159	13		T163	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	27		T144	7		T163	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T45	7		T233	12		T159	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T244	8		T272	2		T323	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T170	2		T300	8		T298	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T21	3		T249	11		T326	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T255	14		T308	10		T311	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	479	1			T5	6		T6	2		T49	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T146	3		T43	11		T294	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T249	10		T262	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T309	1		T312	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T145	16		T158	14		T64	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	1		T146	14		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T4	8		T8	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T5	3		T56	1		T45	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T62	11		T63	8		T148	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T3	8		T4	12		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T144	8		T158	7		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T43	12		T45	1		T177	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T233	4		T164	5		T53	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T43	1		T144	9		T152	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	1		T233	21		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	1		T162	5		T230	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T2	1		T13	1		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	1		T40	1		T157	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T150	13		T162	7		T167	33
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T155	16		T151	18		T163	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T144	5		T163	4		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T45	1		T233	3		T159	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14931	1			T5	11		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T6	27		T252	7		T272	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T170	2		T58	1		T253	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T249	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T309	4		T312	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T145	12		T64	10		T26	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T163	12		T164	11		T165	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T4	8		T8	14		T55	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T5	3		T45	15		T149	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T62	13		T63	1		T148	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T3	2		T4	8		T15	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T230	2		T196	11		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T177	9		T153	2		T50	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T233	2		T164	11		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T18	1		T245	23		T221	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	13		T233	22		T159	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	9		T162	13		T230	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T2	10		T166	8		T26	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	12		T40	2		T157	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T162	6		T160	9		T38	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T151	14		T163	5		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T144	7		T163	4		T50	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T45	7		T233	12		T159	25

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16