Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20753

1

T1

1

T2

35

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3516

1

T4

20

T13

1

T146

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18367

1

T2

24

T4

16

T5

23

auto[1]

5902

1

T1

1

T2

11

T3

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	169	1			T63	9		T50	3		T170	28
values[0]	57	1			T151	1		T327	23		T328	8
values[1]	736	1			T1	1		T40	3		T158	7
values[2]	623	1			T13	1		T146	14		T144	20
values[3]	713	1			T2	14		T6	16		T45	1
values[4]	2919	1			T2	10		T6	13		T8	15
values[5]	708	1			T43	12		T78	1		T145	28
values[6]	722	1			T2	11		T5	6		T6	13
values[7]	661	1			T3	10		T4	16		T45	16
values[8]	657	1			T4	20		T56	1		T35	1
values[9]	1011	1			T35	1		T43	1		T162	13
minimum	15293	1			T5	17		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	709	1			T1	1		T13	1		T40	3
values[1]	676	1			T6	16		T146	14		T233	15
values[2]	671	1			T2	14		T45	1		T158	14
values[3]	2946	1			T2	10		T6	13		T8	15
values[4]	703	1			T146	1		T43	23		T78	1
values[5]	719	1			T2	11		T5	6		T6	13
values[6]	678	1			T3	10		T4	16		T45	16
values[7]	679	1			T4	20		T56	1		T35	1
values[8]	817	1			T35	1		T43	1		T63	9
values[9]	148	1			T153	15		T19	3		T329	1
minimum	15523	1			T5	17		T7	20		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T1	1		T144	1		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	1		T40	3		T144	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	16		T233	13		T50	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T146	1		T163	5		T165	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	14		T230	15		T50	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T45	1		T158	1		T151	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T2	10		T6	13		T8	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T150	1		T196	12		T163	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T146	1		T78	1		T145	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T43	2		T148	1		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	11		T5	5		T6	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T146	1		T144	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	3		T4	9		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T45	16		T164	12		T165	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T56	1		T35	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	9		T177	10		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T35	1		T63	2		T159	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T43	1		T164	12		T50	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T19	2		T330	19		T331	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T153	6		T329	1		T185	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15243	1			T5	13		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T234	1		T203	1		T327	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T144	7		T158	6		T150	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T144	4		T178	13		T247	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T233	2		T50	2		T160	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T146	13		T163	3		T235	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T230	9		T266	9		T252	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T158	13		T151	17		T162	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T12	6		T62	10		T155	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T150	10		T196	9		T163	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T145	15		T152	11		T64	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T43	21		T148	8		T167	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	1		T64	5		T279	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T146	2		T144	8		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	7		T4	7		T155	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T164	8		T15	3		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T155	15		T162	6		T179	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	11		T177	9		T178	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T63	7		T153	14		T157	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T164	4		T154	2		T265	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T19	1		T330	13		T331	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T153	9		T20	5		T293	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	4		T78	2		T148	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T234	11		T327	9		T328	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T63	2		T171	1		T238	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T50	3		T170	14		T171	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T332	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T151	1		T327	14		T328	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T1	1		T158	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T40	3		T178	1		T247	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T144	1		T50	3		T160	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	1		T146	1		T144	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	14		T6	16		T233	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T45	1		T158	1		T151	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1557	1			T2	10		T6	13		T8	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T150	1		T163	6		T153	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T78	1		T145	13		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T43	1		T196	12		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	11		T5	5		T6	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T146	1		T43	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	3		T4	9		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T45	16		T164	12		T165	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T56	1		T35	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	9		T177	10		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T35	1		T162	7		T159	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T43	1		T164	12		T153	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T63	7		T238	6		T263	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T170	14		T272	6		T333	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T332	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T327	9		T328	5		T320	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T158	6		T150	12		T148	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T178	13		T247	14		T234	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T144	7		T50	2		T160	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T146	13		T144	4		T269	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T233	2		T230	9		T252	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T158	13		T151	17		T162	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T12	6		T62	10		T237	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T150	10		T163	15		T294	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T145	15		T155	5		T64	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T43	11		T196	9		T148	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	1		T152	11		T279	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T146	2		T43	10		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T3	7		T4	7		T155	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T164	8		T15	3		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T155	15		T179	12		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	11		T177	9		T178	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T162	6		T153	14		T157	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T164	4		T153	9		T157	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	1		T144	8		T158	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	1		T40	1		T144	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	1		T233	3		T50	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T146	14		T163	4		T165	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T2	1		T230	11		T50	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T45	1		T158	14		T151	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T2	1		T6	1		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T150	11		T196	10		T163	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T146	1		T78	1		T145	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T43	23		T148	9		T167	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	1		T5	3		T6	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T146	3		T144	9		T158	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	8		T4	8		T155	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T45	1		T164	9		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T56	1		T35	1		T155	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	12		T177	10		T178	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T35	1		T63	8		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T43	1		T164	5		T50	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T19	2		T330	14		T331	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T153	10		T329	1		T185	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15377	1			T5	17		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T234	12		T203	1		T327	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T148	13		T26	3		T160	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T40	2		T144	7		T159	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T6	15		T233	12		T50	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T163	4		T165	14		T255	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	13		T230	13		T50	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T151	14		T162	13		T159	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T2	9		T6	12		T8	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T196	11		T163	5		T153	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T145	12		T273	11		T248	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T247	15		T221	11		T334	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T2	10		T5	3		T6	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T230	14		T64	10		T252	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	2		T4	8		T233	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T45	15		T164	11		T165	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T162	6		T15	1		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	8		T177	9		T157	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T63	1		T159	13		T153	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T164	11		T50	8		T265	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T19	1		T330	18		T331	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T153	5		T20	1		T293	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T51	1		T300	2		T299	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T327	13		T312	5		T296	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T63	8		T171	1		T238	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T50	3		T170	15		T171	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T332	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T151	1		T327	10		T328	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T1	1		T158	7		T150	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T40	1		T178	14		T247	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T144	8		T50	4		T160	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	1		T146	14		T144	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	1		T6	1		T233	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T45	1		T158	14		T151	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T2	1		T6	1		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T150	11		T163	16		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T78	1		T145	16		T155	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T43	12		T196	10		T148	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	1		T5	3		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T146	3		T43	11		T144	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	8		T4	8		T155	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T45	1		T164	9		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T56	1		T35	1		T155	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	12		T177	10		T178	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T35	1		T162	7		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T43	1		T164	5		T153	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T63	1		T238	4		T263	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T170	13		T272	2		T322	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T327	13		T328	2		T320	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T148	13		T26	3		T51	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T40	2		T247	8		T234	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T50	1		T160	18		T268	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T144	7		T159	12		T163	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	13		T6	15		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T151	14		T162	13		T159	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T2	9		T6	12		T8	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T163	5		T153	2		T248	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T145	12		T273	11		T248	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T196	11		T221	11		T268	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T2	10		T5	3		T6	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T230	14		T64	10		T247	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T3	2		T4	8		T233	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T45	15		T164	11		T165	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T15	1		T227	2		T251	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T4	8		T177	9		T149	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T162	6		T159	13		T153	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T164	11		T153	5		T50	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16