Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20760

1

T1

1

T2

25

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3509

1

T2

10

T3

10

T4

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18367

1

T1

1

T3

10

T4

36

auto[1]

5902

1

T2

35

T6

29

T8

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	342	1			T56	1		T150	6		T178	14
values[0]	46	1			T221	11		T286	18		T289	14
values[1]	364	1			T2	11		T43	1		T177	10
values[2]	2900	1			T2	14		T8	15		T11	1
values[3]	674	1			T13	1		T146	3		T35	1
values[4]	831	1			T4	20		T145	28		T162	18
values[5]	801	1			T1	1		T6	13		T146	1
values[6]	711	1			T5	6		T146	14		T158	14
values[7]	603	1			T4	16		T6	16		T40	3
values[8]	514	1			T2	10		T3	10		T35	2
values[9]	1190	1			T6	13		T45	16		T155	9
minimum	15293	1			T5	17		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	466	1			T2	25		T43	1		T62	24
values[1]	2853	1			T8	15		T11	1		T12	7
values[2]	683	1			T13	1		T146	3		T43	12
values[3]	935	1			T4	20		T145	28		T162	18
values[4]	746	1			T1	1		T5	6		T6	13
values[5]	620	1			T6	16		T146	14		T158	14
values[6]	618	1			T4	16		T35	1		T40	3
values[7]	577	1			T2	10		T3	10		T35	1
values[8]	1110	1			T6	13		T45	16		T155	9
values[9]	249	1			T56	1		T152	12		T153	3
minimum	15412	1			T5	17		T7	20		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	25		T150	1		T163	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T43	1		T62	14		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1518	1			T8	15		T11	1		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T35	1		T64	1		T25	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T146	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T45	8		T144	8		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	9		T162	14		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T145	13		T233	23		T159	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T1	1		T5	5		T6	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T146	1		T158	1		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	16		T146	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T160	4		T51	4		T278	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T35	1		T40	3		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T4	9		T43	1		T164	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T35	1		T45	1		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	10		T3	3		T162	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	13		T155	1		T163	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	419	1			T45	16		T150	2		T178	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T152	1		T179	1		T265	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T56	1		T153	3		T287	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15185	1			T5	13		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T177	1		T153	14		T192	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T150	12		T163	3		T167	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T62	10		T149	2		T289	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	979	1			T12	6		T237	17		T201	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T64	1		T16	1		T279	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T146	2		T43	11		T144	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T144	4		T235	7		T266	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T4	11		T162	4		T167	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T145	15		T233	20		T166	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	1		T144	7		T48	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T158	6		T178	7		T160	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T146	13		T158	13		T177	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T160	8		T51	2		T278	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T155	15		T233	3		T64	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T4	7		T43	10		T164	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T155	5		T158	13		T63	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	7		T162	6		T230	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T155	8		T157	12		T278	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T150	15		T178	15		T230	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T152	11		T179	12		T265	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T287	7		T225	11		T96	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	4		T78	2		T148	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T177	9		T153	14		T259	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T152	1		T179	1		T229	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T56	1		T150	1		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T221	6		T286	1		T288	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T289	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T2	11		T163	5		T243	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T43	1		T177	1		T153	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T2	14		T8	15		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T62	14		T64	1		T25	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	1		T146	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T35	1		T45	8		T144	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	9		T162	14		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T145	13		T233	23		T159	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T1	1		T6	13		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T146	1		T158	1		T26	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	5		T146	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T178	1		T160	4		T51	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	16		T40	3		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	9		T152	1		T164	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T35	2		T45	1		T78	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	10		T3	3		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	13		T155	1		T163	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	443	1			T45	16		T150	1		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T152	11		T179	12		T299	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T150	5		T178	13		T230	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T221	5		T286	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T289	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T163	3		T238	15		T240	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T177	9		T153	14		T149	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T12	6		T237	17		T150	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T62	10		T64	1		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T146	2		T43	11		T144	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T144	4		T235	7		T266	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	11		T162	4		T167	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T145	15		T233	20		T166	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T144	7		T50	2		T247	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T158	6		T26	10		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	1		T146	13		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T178	7		T160	8		T51	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T155	15		T233	3		T64	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	7		T152	13		T164	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T155	5		T158	13		T63	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T3	7		T43	10		T162	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T155	8		T163	15		T157	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T150	10		T178	2		T148	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	2		T150	13		T163	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T43	1		T62	11		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T8	1		T11	1		T12	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T35	1		T64	2		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	1		T146	3		T43	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T45	1		T144	5		T235	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T4	12		T162	5		T167	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T145	16		T233	21		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T1	1		T5	3		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T146	1		T158	7		T178	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	1		T146	14		T158	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T160	9		T51	5		T278	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T35	1		T40	1		T155	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	8		T43	11		T164	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T35	1		T45	1		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	1		T3	8		T162	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T6	1		T155	9		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T45	1		T150	17		T178	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T152	12		T179	13		T265	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T56	1		T153	1		T287	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15327	1			T5	17		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T177	10		T153	15		T192	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	23		T163	4		T180	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T62	13		T149	1		T90	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T8	14		T55	19		T205	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T25	9		T16	1		T253	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T153	5		T160	9		T90	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T45	7		T144	7		T273	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	8		T162	13		T247	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T145	12		T233	22		T159	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	3		T6	12		T50	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T160	9		T255	19		T269	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	15		T177	9		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T160	3		T51	1		T279	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	2		T233	2		T64	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	8		T164	11		T15	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T63	1		T163	5		T164	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	9		T3	2		T162	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	12		T163	12		T50	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T45	15		T230	14		T50	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T265	13		T239	11		T241	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T153	2		T225	12		T96	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T221	5		T22	4		T331	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T153	13		T259	5		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T152	12		T179	13		T229	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T56	1		T150	6		T178	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T221	6		T286	18		T288	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T289	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T2	1		T163	4		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T43	1		T177	10		T153	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T2	1		T8	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T62	11		T64	2		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	1		T146	3		T43	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T35	1		T45	1		T144	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T4	12		T162	5		T167	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T145	16		T233	21		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T6	1		T144	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T146	1		T158	7		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	3		T146	14		T158	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T178	8		T160	9		T51	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	1		T40	1		T155	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	8		T152	14		T164	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T35	2		T45	1		T78	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T2	1		T3	8		T43	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T6	1		T155	9		T163	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T45	1		T150	11		T178	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T299	13		T325	14		T249	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T230	14		T153	2		T165	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T221	5		T288	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T2	10		T163	4		T243	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T153	13		T149	1		T90	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T2	13		T8	14		T55	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T62	13		T25	9		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T153	5		T160	9		T247	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T45	7		T144	7		T273	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	8		T162	13		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T145	12		T233	22		T159	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	12		T50	1		T247	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T26	11		T160	9		T255	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	3		T177	9		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T160	3		T51	1		T279	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	15		T40	2		T233	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	8		T164	11		T15	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T63	1		T164	11		T36	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T2	9		T3	2		T162	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	12		T163	17		T50	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T45	15		T230	2		T50	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16