Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20307

1

T3

10

T5

17

T7

20

auto[ADC_CTRL_FILTER_COND_OUT]

3962

1

T1

1

T2

35

T4

36

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18302

1

T1

1

T2

21

T3

10

auto[1]

5967

1

T2

14

T4

36

T5

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	202	1			T15	4		T247	23		T154	3
values[0]	45	1			T6	13		T24	5		T274	25
values[1]	659	1			T4	16		T6	13		T146	1
values[2]	598	1			T4	20		T35	1		T43	12
values[3]	732	1			T1	1		T56	1		T35	1
values[4]	834	1			T144	9		T150	6		T152	12
values[5]	2989	1			T2	10		T5	6		T8	15
values[6]	656	1			T6	16		T146	14		T45	8
values[7]	506	1			T2	11		T146	3		T35	1
values[8]	726	1			T2	14		T45	1		T144	8
values[9]	1029	1			T3	10		T43	12		T158	14
minimum	15293	1			T5	17		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	543	1			T4	16		T6	13		T146	1
values[1]	723	1			T4	20		T56	1		T155	25
values[2]	804	1			T1	1		T35	1		T45	16
values[3]	3084	1			T5	6		T8	15		T11	1
values[4]	682	1			T2	10		T13	1		T40	3
values[5]	615	1			T6	16		T146	17		T159	27
values[6]	655	1			T2	25		T35	1		T151	33
values[7]	603	1			T45	1		T144	8		T62	24
values[8]	956	1			T3	10		T43	12		T158	14
values[9]	99	1			T15	4		T53	2		T269	22
minimum	15505	1			T5	17		T6	13		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T146	1		T64	1		T50	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	9		T6	13		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T56	1		T155	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T4	9		T155	1		T233	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T45	16		T158	1		T233	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	1		T35	1		T145	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1545	1			T8	15		T11	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T5	5		T144	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	1		T45	8		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	10		T40	3		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T146	1		T159	27		T50	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	16		T146	1		T230	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T151	1		T163	13		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	25		T35	1		T151	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T144	1		T164	12		T160	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T45	1		T62	14		T162	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	3		T43	2		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T178	1		T50	3		T165	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T53	1		T269	12		T244	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T15	3		T185	1		T111	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15197	1			T5	13		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T6	13		T29	1		T253	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T64	1		T278	3		T161	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T4	7		T43	11		T178	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T155	15		T158	13		T63	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	11		T155	8		T233	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T158	6		T233	2		T164	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T145	15		T177	9		T163	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T12	6		T237	17		T201	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T5	1		T144	8		T150	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T150	10		T230	9		T227	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T155	5		T177	9		T150	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T146	2		T278	4		T228	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T146	13		T230	6		T163	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T167	16		T279	9		T245	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T151	17		T166	9		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T144	7		T164	4		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T62	10		T162	4		T152	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	7		T43	10		T158	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T178	2		T50	2		T167	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T53	1		T269	10		T338	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T15	1		T111	11		T210	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	4		T144	4		T78	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T29	6		T253	13		T245	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T294	1		T254	1		T244	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T15	3		T247	9		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T274	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T6	13		T24	2		T339	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T146	1		T144	8		T64	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	9		T6	13		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T155	1		T158	1		T63	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	9		T35	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T56	1		T45	16		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	1		T35	1		T145	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T153	6		T157	18		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T144	1		T150	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1531	1			T8	15		T11	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	10		T5	5		T40	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T45	8		T150	1		T159	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	16		T146	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T146	1		T151	1		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	11		T35	1		T230	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T144	1		T163	13		T164	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	14		T45	1		T62	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T3	3		T43	2		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T178	1		T50	3		T165	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T294	3		T254	11		T327	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T15	1		T247	14		T154	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T274	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T24	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T144	4		T64	1		T278	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	7		T178	13		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T155	15		T158	13		T63	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T4	11		T43	11		T155	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T158	6		T233	2		T148	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T145	15		T177	9		T153	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T153	9		T157	12		T252	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T144	8		T150	5		T152	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T12	6		T237	17		T201	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	1		T177	9		T150	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T150	10		T278	4		T228	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T146	13		T155	5		T234	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T146	2		T167	16		T287	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T230	6		T163	3		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T144	7		T164	4		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T62	10		T151	17		T162	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	7		T43	10		T158	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T178	2		T50	2		T167	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T146	1		T64	2		T50	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	8		T6	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T56	1		T155	16		T158	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T4	12		T155	9		T233	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T45	1		T158	7		T233	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T1	1		T35	1		T145	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T8	1		T11	1		T12	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T5	3		T144	9		T150	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	1		T45	1		T150	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	1		T40	1		T155	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T146	3		T159	2		T50	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	1		T146	14		T230	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T151	1		T163	1		T167	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	2		T35	1		T151	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T144	8		T164	5		T160	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T45	1		T62	11		T162	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T3	8		T43	12		T158	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T178	3		T50	4		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T53	2		T269	11		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T15	3		T185	1		T111	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15349	1			T5	17		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T6	1		T29	7		T253	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T161	13		T18	1		T244	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	8		T6	12		T159	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T63	1		T162	6		T165	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	8		T233	22		T230	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T45	15		T233	12		T164	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T145	12		T177	9		T163	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T8	14		T55	19		T205	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	3		T196	11		T165	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T45	7		T230	11		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	9		T40	2		T64	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T159	25		T50	4		T228	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	15		T230	14		T163	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T163	12		T279	12		T245	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	23		T151	14		T166	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T164	11		T160	18		T243	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T62	13		T162	13		T238	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	2		T233	2		T64	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T50	1		T165	12		T247	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T269	11		T244	12		T338	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T15	1		T112	11		T309	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T144	7		T180	7		T149	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T6	12		T245	10		T340	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T294	4		T254	12		T244	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T15	3		T247	15		T154	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T274	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T6	1		T24	5		T339	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T146	1		T144	5		T64	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	8		T6	1		T178	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T155	16		T158	14		T63	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	12		T35	1		T43	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T56	1		T45	1		T158	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	1		T35	1		T145	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T153	10		T157	13		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T144	9		T150	6		T152	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T8	1		T11	1		T12	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T2	1		T5	3		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T45	1		T150	11		T159	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	1		T146	14		T155	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T146	3		T151	1		T167	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	1		T35	1		T230	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T144	8		T163	1		T164	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	1		T45	1		T62	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	8		T43	12		T158	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T178	3		T50	4		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T244	12		T327	13		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T15	1		T247	8		T209	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T274	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T6	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T144	7		T161	13		T180	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	8		T6	12		T153	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T63	1		T162	6		T165	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	8		T233	22		T159	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T45	15		T233	12		T164	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T145	12		T177	9		T153	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T153	5		T157	17		T273	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T163	5		T165	2		T15	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T8	14		T55	19		T205	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	9		T5	3		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T45	7		T159	25		T50	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	15		T36	8		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T244	8		T90	7		T115	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	10		T230	14		T163	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T163	12		T164	11		T160	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	13		T62	13		T151	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	2		T233	2		T64	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T50	1		T165	12		T290	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16