Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T146	1		T43	11		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T35	1		T144	9		T158	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	1		T45	1		T151	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T78	1		T163	16		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	1		T158	28		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T150	13		T178	3		T233	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T25	1		T160	3		T247	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T6	1		T35	1		T164	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	1		T155	25		T150	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T3	8		T40	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	2		T230	10		T152	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T144	8		T145	16		T150	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T4	12		T8	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T4	8		T43	12		T155	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	1		T62	11		T178	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T146	14		T177	10		T178	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T35	1		T163	4		T50	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T2	1		T5	3		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T146	3		T180	1		T238	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T255	1		T256	1		T241	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15324	1			T5	17		T7	20		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T45	7		T144	7		T230	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T159	12		T221	11		T267	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T45	15		T151	14		T165	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T163	5		T36	8		T248	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T159	13		T153	2		T50	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T233	22		T64	2		T196	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T25	9		T160	9		T247	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	15		T164	11		T153	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	12		T170	2		T268	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T3	2		T40	2		T63	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	22		T230	11		T269	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T145	12		T233	12		T148	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T4	8		T8	14		T55	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	8		T162	13		T64	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	12		T62	13		T15	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T177	9		T234	11		T270	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T163	4		T165	20		T227	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	10		T5	3		T162	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T180	7		T238	4		T259	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T255	14		T256	9		T241	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T271	2		T189	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T146	3		T238	5		T262	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T253	12		T20	10		T263	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T43	11		T254	6		T264	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T144	9		T253	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T146	1		T144	5		T230	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T35	1		T158	7		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	1		T45	2		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T163	16		T36	1		T248	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T158	14		T151	18		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T35	1		T78	1		T150	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	1		T158	14		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T153	15		T157	13		T29	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T155	25		T150	11		T48	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	8		T6	1		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T2	2		T4	12		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T43	1		T150	6		T179	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T177	10		T233	4		T148	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	8		T43	12		T144	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T8	1		T11	1		T12	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T177	10		T50	4		T265	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	388	1			T6	1		T35	1		T62	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T2	1		T5	3		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T253	12		T20	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T144	7		T230	14		T157	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T159	12		T267	11		T272	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T45	22		T50	8		T165	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T163	5		T36	8		T248	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T151	14		T159	13		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T233	22		T64	2		T196	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T25	9		T160	9		T247	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T153	13		T157	17		T243	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T170	2		T268	10		T208	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	2		T6	15		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	22		T4	8		T6	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T52	1		T273	11		T252	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T233	2		T165	12		T166	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	8		T145	12		T162	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T8	14		T55	19		T205	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T177	9		T50	1		T265	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T6	12		T62	13		T163	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T2	10		T5	3		T162	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16