Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20355

1

T3

10

T5

17

T7

20

auto[ADC_CTRL_FILTER_COND_OUT]

3914

1

T1

1

T2

35

T4

36

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18281

1

T1

1

T2

21

T3

10

auto[1]

5988

1

T2

14

T4

36

T5

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T188	1		-	-		-	-
values[0]	32	1			T24	5		T274	25		T275	2
values[1]	701	1			T4	16		T6	26		T144	12
values[2]	568	1			T4	20		T146	1		T35	1
values[3]	791	1			T1	1		T56	1		T45	16
values[4]	765	1			T5	6		T35	1		T144	9
values[5]	2980	1			T2	10		T8	15		T11	1
values[6]	680	1			T6	16		T146	14		T45	8
values[7]	581	1			T2	11		T146	3		T35	1
values[8]	652	1			T2	14		T45	1		T144	8
values[9]	1225	1			T3	10		T43	12		T158	14
minimum	15293	1			T5	17		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	704	1			T4	16		T6	26		T146	1
values[1]	789	1			T4	20		T56	1		T155	25
values[2]	769	1			T1	1		T35	1		T45	16
values[3]	3020	1			T5	6		T8	15		T11	1
values[4]	673	1			T2	10		T13	1		T40	3
values[5]	704	1			T2	11		T6	16		T146	17
values[6]	644	1			T2	14		T35	1		T62	24
values[7]	532	1			T144	8		T162	18		T152	6
values[8]	912	1			T3	10		T43	12		T45	1
values[9]	171	1			T53	2		T269	22		T171	1
minimum	15351	1			T5	17		T7	20		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T146	1		T144	8		T64	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T4	9		T6	26		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T56	1		T155	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T4	9		T155	1		T233	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T45	16		T158	1		T233	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	1		T35	1		T145	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T8	15		T11	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T5	5		T144	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	1		T45	8		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	10		T40	3		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T146	1		T159	14		T50	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	11		T6	16		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T62	14		T151	1		T163	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	14		T35	1		T151	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T144	1		T152	1		T164	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T162	14		T192	1		T276	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	3		T43	2		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T45	1		T178	1		T50	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T53	1		T269	12		T244	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T171	1		T185	1		T249	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15171	1			T5	13		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T277	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T144	4		T64	1		T278	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	7		T43	11		T178	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T155	15		T158	13		T63	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	11		T155	8		T233	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T158	6		T233	2		T164	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T145	15		T177	9		T163	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T12	6		T237	17		T201	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	1		T144	8		T150	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T150	10		T178	7		T230	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T155	5		T177	9		T150	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T146	2		T278	4		T228	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T146	13		T230	6		T163	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T62	10		T167	16		T279	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T151	17		T16	1		T265	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T144	7		T152	5		T164	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T162	4		T238	15		T208	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	7		T43	10		T158	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T178	2		T50	2		T167	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T53	1		T269	10		T221	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T249	9		T111	11		T210	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	4		T78	2		T148	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T277	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T188	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T274	11		T275	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T24	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T144	8		T64	1		T165	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T4	9		T6	26		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T146	1		T155	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T4	9		T35	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T56	1		T45	16		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	1		T145	13		T177	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T153	6		T157	18		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	5		T35	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T8	15		T11	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	10		T40	3		T177	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T45	8		T150	1		T159	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	16		T146	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T146	1		T151	1		T166	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	11		T35	1		T151	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T144	1		T62	14		T233	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	14		T45	1		T162	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T3	3		T43	2		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T178	1		T50	3		T165	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T274	14		T275	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T24	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T144	4		T64	1		T278	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	7		T178	13		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T155	15		T158	13		T63	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	11		T43	11		T155	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T158	6		T233	2		T148	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T145	15		T177	9		T150	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T153	9		T157	12		T252	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T5	1		T144	8		T152	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T12	6		T237	17		T201	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T177	9		T150	12		T64	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T150	10		T278	4		T228	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T146	13		T155	5		T234	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T146	2		T166	9		T167	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T151	17		T230	6		T163	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T144	7		T62	10		T233	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T162	4		T238	15		T280	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	7		T43	10		T158	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T178	2		T50	2		T167	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T146	1		T144	5		T64	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T4	8		T6	2		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T56	1		T155	16		T158	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T4	12		T155	9		T233	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T45	1		T158	7		T233	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T1	1		T35	1		T145	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T8	1		T11	1		T12	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T5	3		T144	9		T150	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T45	1		T150	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	1		T40	1		T155	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T146	3		T159	1		T50	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	1		T6	1		T146	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T62	11		T151	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	1		T35	1		T151	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T144	8		T152	6		T164	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T162	5		T192	1		T276	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	8		T43	12		T158	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T45	1		T178	3		T50	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T53	2		T269	11		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T171	1		T185	1		T249	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15311	1			T5	17		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T277	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T144	7		T161	13		T180	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	8		T6	24		T159	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T63	1		T162	6		T165	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	8		T233	22		T230	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T45	15		T233	12		T164	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T145	12		T177	9		T163	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T8	14		T55	19		T205	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	3		T196	11		T165	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T45	7		T159	12		T230	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	9		T40	2		T64	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T159	13		T50	4		T228	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	10		T6	15		T230	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T62	13		T163	12		T279	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	13		T151	14		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T164	11		T166	8		T160	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T162	13		T238	13		T208	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	2		T233	2		T64	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T50	1		T165	12		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T269	11		T244	12		T221	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T249	11		T112	11		T187	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T281	12		T282	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T277	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T188	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T274	15		T275	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T24	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T144	5		T64	2		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T4	8		T6	2		T178	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T146	1		T155	16		T158	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	12		T35	1		T43	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T56	1		T45	1		T158	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	1		T145	16		T177	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T153	10		T157	13		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T5	3		T35	1		T144	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T8	1		T11	1		T12	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T2	1		T40	1		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T45	1		T150	11		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	1		T146	14		T155	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T146	3		T151	1		T166	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	1		T35	1		T151	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T144	8		T62	11		T233	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	1		T45	1		T162	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	8		T43	12		T158	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T178	3		T50	4		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T274	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T144	7		T165	20		T161	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	8		T6	24		T153	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T63	1		T162	6		T255	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	8		T233	22		T159	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T45	15		T233	12		T164	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T145	12		T177	9		T153	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T153	5		T157	17		T273	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	3		T163	5		T165	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T8	14		T55	19		T205	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	9		T40	2		T64	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T45	7		T159	13		T50	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	15		T36	8		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T166	8		T244	8		T90	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	10		T151	14		T230	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T62	13		T233	2		T163	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T2	13		T162	13		T251	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T3	2		T64	10		T148	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T50	1		T165	12		T15	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16