Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20810

1

T1

1

T2

25

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3459

1

T2

10

T3

10

T4

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18396

1

T1

1

T3

10

T4

36

auto[1]

5873

1

T2

35

T6

29

T8

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	35	1			T283	7		T284	27		T285	1
values[0]	66	1			T221	11		T286	18		T259	20
values[1]	379	1			T2	11		T43	1		T177	10
values[2]	2838	1			T2	14		T8	15		T11	1
values[3]	733	1			T146	3		T43	12		T45	8
values[4]	848	1			T4	20		T13	1		T162	18
values[5]	792	1			T1	1		T6	13		T146	1
values[6]	605	1			T5	6		T146	14		T158	14
values[7]	699	1			T4	16		T6	16		T40	3
values[8]	478	1			T2	10		T6	13		T35	2
values[9]	1503	1			T3	10		T56	1		T45	16
minimum	15293	1			T5	17		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	564	1			T2	11		T43	1		T62	24
values[1]	2875	1			T2	14		T8	15		T11	1
values[2]	646	1			T4	20		T13	1		T146	3
values[3]	956	1			T45	8		T145	28		T162	18
values[4]	797	1			T1	1		T5	6		T6	13
values[5]	575	1			T6	16		T151	32		T178	8
values[6]	613	1			T4	16		T146	14		T35	1
values[7]	628	1			T2	10		T3	10		T35	1
values[8]	1017	1			T6	13		T155	9		T150	17
values[9]	304	1			T56	1		T45	16		T152	12
minimum	15294	1			T5	17		T7	20		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	11		T150	1		T163	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T43	1		T62	14		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1545	1			T2	14		T8	15		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T35	1		T64	1		T25	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	9		T13	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T144	8		T235	1		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T162	14		T167	1		T227	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T45	8		T145	13		T233	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T1	1		T5	5		T6	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T146	1		T158	1		T160	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	16		T151	15		T233	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T178	1		T160	4		T51	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T146	1		T35	1		T40	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	9		T15	4		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T35	1		T45	1		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	10		T3	3		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	13		T155	1		T163	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T150	2		T178	2		T230	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T152	1		T179	1		T278	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T56	1		T45	16		T153	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T38	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T150	12		T163	3		T167	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T62	10		T177	9		T153	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T12	6		T237	17		T201	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T64	1		T16	1		T279	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	11		T146	2		T43	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T144	4		T235	7		T266	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T162	4		T167	16		T227	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T145	15		T233	20		T166	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	1		T144	7		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T158	6		T160	9		T269	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T151	17		T233	2		T64	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T178	7		T160	8		T51	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T146	13		T155	20		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T4	7		T15	3		T254	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T158	13		T63	7		T152	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	7		T43	10		T162	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T155	8		T157	12		T161	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T150	15		T178	15		T230	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T152	11		T179	12		T278	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T287	7		T96	12		T209	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T283	1		T284	15		T285	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T221	6		T286	1		T288	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T259	6		T289	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T2	11		T163	5		T180	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T43	1		T177	1		T153	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1528	1			T2	14		T8	15		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T35	1		T62	14		T64	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T146	1		T43	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T45	8		T144	8		T235	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	9		T13	1		T162	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T233	23		T165	24		T166	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T1	1		T6	13		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T146	1		T145	13		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	5		T146	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T178	1		T51	4		T278	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	16		T40	3		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	9		T43	1		T230	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	13		T35	2		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	10		T162	7		T26	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T155	1		T151	1		T152	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	541	1			T3	3		T56	1		T45	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T283	6		T284	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T221	5		T286	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T259	14		T289	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T163	3		T238	15		T240	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T177	9		T153	14		T149	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T12	6		T237	17		T150	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T62	10		T64	1		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T146	2		T43	11		T144	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T144	4		T235	7		T228	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T4	11		T162	4		T50	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T233	20		T166	9		T248	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T144	7		T247	15		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T145	15		T158	6		T26	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T146	13		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T178	7		T51	2		T278	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T155	15		T177	9		T233	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	7		T43	10		T230	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T155	5		T158	13		T63	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T162	6		T26	3		T23	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T155	8		T152	16		T163	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	398	1			T3	7		T150	15		T178	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	1		T150	13		T163	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T43	1		T62	11		T177	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T2	1		T8	1		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T35	1		T64	2		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	12		T13	1		T146	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T144	5		T235	8		T266	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T162	5		T167	17		T227	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T45	1		T145	16		T233	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T1	1		T5	3		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T146	1		T158	7		T160	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	1		T151	18		T233	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T178	8		T160	9		T51	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T146	14		T35	1		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	8		T15	4		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T35	1		T45	1		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	1		T3	8		T43	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	1		T155	9		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T150	17		T178	17		T230	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T152	12		T179	13		T278	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T56	1		T45	1		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T38	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T2	10		T163	4		T180	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T62	13		T153	13		T149	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T2	13		T8	14		T55	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T25	9		T16	1		T253	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	8		T153	5		T160	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T144	7		T252	9		T58	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T162	13		T227	2		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T45	7		T145	12		T233	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	3		T6	12		T50	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T160	9		T255	19		T269	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T6	15		T151	14		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T160	3		T51	1		T279	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T40	2		T177	9		T233	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	8		T15	3		T225	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T63	1		T163	5		T164	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	9		T3	2		T162	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	12		T163	12		T50	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T230	14		T50	8		T157	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T265	13		T239	11		T241	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T45	15		T153	2		T96	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T283	7		T284	13		T285	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T221	6		T286	18		T288	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T259	15		T289	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	1		T163	4		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T43	1		T177	10		T153	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T2	1		T8	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T35	1		T62	11		T64	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T146	3		T43	12		T144	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T45	1		T144	5		T235	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T4	12		T13	1		T162	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T233	21		T165	2		T166	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	1		T6	1		T144	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T146	1		T145	16		T158	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	3		T146	14		T158	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T178	8		T51	5		T278	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	1		T40	1		T155	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	8		T43	11		T230	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	1		T35	2		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T2	1		T162	7		T26	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T155	9		T151	1		T152	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	489	1			T3	8		T56	1		T45	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T284	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T221	5		T288	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T259	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T2	10		T163	4		T180	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T153	13		T149	1		T90	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T2	13		T8	14		T55	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T62	13		T25	9		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T153	5		T160	9		T247	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T45	7		T144	7		T273	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	8		T162	13		T50	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T233	22		T165	22		T166	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	12		T247	15		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T145	12		T159	13		T26	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T5	3		T151	14		T233	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T51	1		T279	12		T290	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	15		T40	2		T177	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T4	8		T230	11		T164	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	12		T63	1		T164	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T2	9		T162	6		T26	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T163	17		T50	4		T157	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	450	1			T3	2		T45	15		T230	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16