Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20858

1

T1

1

T2

24

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3411

1

T2

11

T3

10

T4

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18159

1

T4

20

T5

23

T6

13

auto[1]

6110

1

T1

1

T2

35

T3

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	267	1			T5	6		T56	1		T45	1
values[0]	24	1			T253	14		T291	10		-	-
values[1]	556	1			T35	1		T43	11		T144	21
values[2]	608	1			T1	1		T146	1		T45	24
values[3]	805	1			T35	1		T158	14		T150	13
values[4]	817	1			T13	1		T158	14		T153	28
values[5]	671	1			T3	10		T6	16		T40	3
values[6]	496	1			T2	24		T4	20		T6	13
values[7]	768	1			T4	16		T43	12		T145	28
values[8]	2828	1			T8	15		T11	1		T12	7
values[9]	1136	1			T2	11		T6	13		T146	17
minimum	15293	1			T5	17		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	574	1			T146	1		T35	1		T45	8
values[1]	671	1			T1	1		T45	16		T78	1
values[2]	755	1			T13	1		T35	1		T158	28
values[3]	843	1			T6	16		T155	16		T164	16
values[4]	487	1			T3	10		T6	13		T40	3
values[5]	723	1			T2	24		T4	20		T144	8
values[6]	2863	1			T4	16		T8	15		T11	1
values[7]	710	1			T6	13		T177	19		T178	22
values[8]	1105	1			T2	11		T5	6		T56	1
values[9]	69	1			T64	2		T180	8		T260	15
minimum	15469	1			T5	17		T7	20		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T146	1		T45	8		T230	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T35	1		T158	1		T159	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T1	1		T45	16		T151	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T78	1		T233	23		T163	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	1		T158	2		T159	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T35	1		T150	1		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T155	1		T25	10		T160	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	16		T164	12		T153	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	13		T155	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T3	3		T40	3		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	24		T4	9		T145	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T144	1		T233	13		T148	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1503	1			T8	15		T11	1		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T4	9		T43	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	13		T198	1		T292	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T177	10		T178	2		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T35	1		T62	14		T163	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T2	11		T5	5		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T180	8		T259	6		T281	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T64	1		T260	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15187	1			T5	13		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T144	1		T253	1		T225	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T230	6		T157	14		T149	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T158	6		T235	14		T266	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T151	17		T26	10		T160	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T233	20		T163	15		T248	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T158	26		T53	1		T235	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T150	12		T178	2		T64	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T155	15		T160	2		T247	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T164	4		T153	9		T29	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T155	8		T150	10		T48	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T3	7		T150	5		T63	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T4	11		T145	15		T230	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T144	7		T233	2		T148	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T12	6		T177	9		T237	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	7		T43	11		T155	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T198	2		T292	7		T154	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T177	9		T178	20		T152	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T62	10		T163	3		T15	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	1		T146	15		T162	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T259	14		T281	5		T293	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T64	1		T260	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	4		T43	10		T144	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T144	8		T253	13		T225	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T163	5		T294	1		T268	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T5	5		T56	1		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T253	1		T291	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T43	1		T144	8		T230	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T35	1		T144	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	1		T146	1		T45	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T78	1		T163	6		T36	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T158	1		T151	15		T159	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T35	1		T150	1		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T13	1		T158	1		T25	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T153	14		T29	1		T278	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T155	2		T150	1		T159	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	3		T6	16		T40	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	24		T4	9		T6	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T43	1		T144	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T145	13		T177	1		T233	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T4	9		T43	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T8	15		T11	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T177	10		T152	1		T265	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T6	13		T35	1		T62	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T2	11		T146	2		T178	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T163	3		T294	16		T268	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T5	1		T64	1		T160	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T253	13		T291	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T43	10		T144	4		T230	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T144	8		T158	6		T235	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T26	10		T160	9		T228	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T163	15		T248	13		T266	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T158	13		T151	17		T193	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T150	12		T178	2		T233	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T158	13		T160	2		T247	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T153	14		T29	6		T278	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T155	23		T150	10		T48	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T3	7		T63	7		T233	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T4	11		T230	9		T152	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T144	7		T150	5		T179	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T145	15		T177	9		T233	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	7		T43	11		T155	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T12	6		T237	17		T201	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T177	9		T152	11		T265	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T62	10		T15	3		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T146	15		T178	20		T162	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T146	1		T45	1		T230	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T35	1		T158	7		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	1		T45	1		T151	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T78	1		T233	21		T163	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	1		T158	28		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T35	1		T150	13		T178	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T155	16		T25	1		T160	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T6	1		T164	5		T153	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	1		T155	9		T150	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	8		T40	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	2		T4	12		T145	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T144	8		T233	3		T148	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T8	1		T11	1		T12	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	8		T43	12		T155	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	1		T198	3		T292	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T177	10		T178	22		T152	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T35	1		T62	11		T163	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T2	1		T5	3		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T180	1		T259	15		T281	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T64	2		T260	15		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15359	1			T5	17		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T144	9		T253	14		T225	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T45	7		T230	14		T157	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T159	12		T221	11		T267	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T45	15		T151	14		T50	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T233	22		T163	5		T36	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T159	13		T153	2		T258	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T64	2		T196	11		T164	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T25	9		T160	9		T247	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	15		T164	11		T153	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	12		T159	12		T170	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T3	2		T40	2		T63	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	22		T4	8		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T233	12		T148	13		T52	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T8	14		T55	19		T205	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	8		T162	13		T64	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	12		T51	1		T149	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T177	9		T234	11		T270	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T62	13		T163	4		T165	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	10		T5	3		T162	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T180	7		T259	5		T281	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T144	7		T271	2		T295	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T21	3		T272	8		T296	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T163	4		T294	17		T268	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T5	3		T56	1		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T253	14		T291	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T43	11		T144	5		T230	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	1		T144	9		T158	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	1		T146	1		T45	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T78	1		T163	16		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T158	14		T151	18		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T35	1		T150	13		T178	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	1		T158	14		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T153	15		T29	7		T278	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T155	25		T150	11		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	8		T6	1		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T2	2		T4	12		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T43	1		T144	8		T150	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T145	16		T177	10		T233	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	8		T43	12		T155	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T8	1		T11	1		T12	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T177	10		T152	12		T265	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T6	1		T35	1		T62	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T2	1		T146	17		T178	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T163	4		T268	10		T208	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T5	3		T160	3		T255	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T144	7		T230	14		T157	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T159	12		T267	11		T21	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T45	22		T165	2		T26	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T163	5		T36	8		T248	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T151	14		T159	13		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T233	22		T64	2		T196	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T25	9		T160	9		T247	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T153	13		T17	1		T252	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T159	12		T170	2		T268	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	2		T6	15		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	22		T4	8		T6	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T52	1		T273	11		T252	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T145	12		T233	2		T165	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	8		T162	13		T64	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T8	14		T55	19		T205	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T177	9		T265	13		T270	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T6	12		T62	13		T165	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	10		T162	6		T163	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16