Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20559

1

T1

1

T2

25

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3710

1

T2

10

T3

10

T4

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18597

1

T1

1

T2

35

T3

10

auto[1]

5672

1

T4

16

T6

13

T8

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	5	1			T297	5		-	-		-	-
values[0]	32	1			T171	1		T298	20		T188	1
values[1]	549	1			T2	14		T5	6		T45	1
values[2]	597	1			T1	1		T43	11		T144	9
values[3]	617	1			T4	20		T35	2		T145	28
values[4]	620	1			T2	10		T146	1		T40	3
values[5]	2860	1			T4	16		T8	15		T11	1
values[6]	753	1			T146	3		T35	1		T78	1
values[7]	718	1			T3	10		T43	12		T177	19
values[8]	851	1			T6	13		T158	7		T150	11
values[9]	1374	1			T2	11		T6	29		T13	1
minimum	15293	1			T5	17		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	704	1			T1	1		T2	14		T5	6
values[1]	716	1			T4	20		T144	9		T145	28
values[2]	522	1			T35	1		T144	8		T177	10
values[3]	2903	1			T2	10		T8	15		T11	1
values[4]	570	1			T4	16		T43	1		T158	14
values[5]	793	1			T3	10		T146	3		T35	1
values[6]	780	1			T6	13		T43	12		T158	7
values[7]	681	1			T146	14		T144	12		T159	14
values[8]	901	1			T2	11		T13	1		T155	16
values[9]	372	1			T6	29		T56	1		T178	14
minimum	15327	1			T5	17		T7	20		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	1		T2	14		T43	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	5		T45	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	9		T144	1		T64	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T145	13		T167	1		T247	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T144	1		T48	6		T50	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T35	1		T177	1		T165	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1531	1			T8	15		T11	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	10		T35	1		T40	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T233	13		T153	14		T50	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	9		T43	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T146	1		T35	1		T159	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T3	3		T78	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	13		T177	10		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T43	1		T158	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T146	1		T144	8		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T159	14		T165	13		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	11		T162	14		T159	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T13	1		T155	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T6	13		T56	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T6	16		T162	7		T233	23
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T160	10		T252	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T43	10		T150	12		T233	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	1		T155	5		T158	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T4	11		T144	8		T64	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T145	15		T167	16		T247	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T144	7		T48	6		T26	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T177	9		T257	2		T299	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T12	6		T237	17		T201	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T62	10		T155	8		T29	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T233	2		T153	14		T50	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T4	7		T158	13		T63	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T146	2		T153	9		T157	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T3	7		T178	7		T230	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T177	9		T150	10		T64	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T43	11		T158	6		T265	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T146	13		T144	4		T152	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T51	2		T278	4		T300	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T162	4		T152	11		T64	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T155	15		T150	5		T151	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T178	13		T234	5		T238	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T162	6		T233	20		T181	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T160	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T297	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T171	1		T188	1		T301	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T298	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T2	14		T150	1		T233	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	5		T45	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T1	1		T43	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T167	1		T247	16		T278	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	9		T26	4		T16	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T35	2		T145	13		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T146	1		T144	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	10		T40	3		T63	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T8	15		T11	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	9		T43	1		T45	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T146	1		T35	1		T159	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T78	1		T178	1		T230	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T177	10		T64	11		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	3		T43	1		T230	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	13		T150	1		T230	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T158	1		T151	1		T159	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T2	11		T6	13		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T6	16		T13	1		T155	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T297	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T298	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T150	12		T233	3		T15	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T5	1		T155	5		T158	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T43	10		T144	8		T64	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T167	16		T247	15		T278	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T4	11		T26	3		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T145	15		T155	8		T177	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T144	7		T152	13		T48	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T63	7		T52	3		T302	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T12	6		T237	17		T201	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	7		T62	10		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T146	2		T153	23		T292	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T178	7		T230	9		T157	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T177	9		T64	8		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	7		T43	11		T230	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T150	10		T148	8		T163	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T158	6		T265	18		T303	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T146	13		T144	4		T178	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T155	15		T150	5		T151	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	1		T2	1		T43	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	3		T45	1		T155	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	12		T144	9		T64	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T145	16		T167	17		T247	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T144	8		T48	12		T50	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T35	1		T177	10		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T8	1		T11	1		T12	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	1		T35	1		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T233	3		T153	15		T50	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T4	8		T43	1		T158	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T146	3		T35	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T3	8		T78	1		T178	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T6	1		T177	10		T150	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T43	12		T158	7		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T146	14		T144	5		T152	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T159	1		T165	1		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	1		T162	5		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T13	1		T155	16		T150	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T6	1		T56	1		T178	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T6	1		T162	7		T233	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T160	10		T252	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T2	13		T233	2		T15	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	3		T196	11		T148	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T4	8		T164	11		T251	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T145	12		T247	15		T180	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T50	4		T26	3		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T165	20		T25	9		T58	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T8	14		T55	19		T45	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	9		T40	2		T45	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T233	12		T153	13		T50	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T4	8		T63	1		T165	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T159	12		T153	5		T157	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	2		T230	25		T153	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	12		T177	9		T230	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T163	12		T265	13		T252	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T144	7		T163	5		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T159	13		T165	12		T51	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	10		T162	13		T159	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T151	14		T15	1		T290	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T6	12		T234	11		T238	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T6	15		T162	6		T233	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T160	9		T252	14		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T297	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T171	1		T188	1		T301	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T298	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T2	1		T150	13		T233	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	3		T45	1		T155	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	1		T43	11		T144	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T167	17		T247	16		T278	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	12		T26	4		T16	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T35	2		T145	16		T155	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T146	1		T144	8		T152	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	1		T40	1		T63	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T8	1		T11	1		T12	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	8		T43	1		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T146	3		T35	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T78	1		T178	8		T230	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T177	10		T64	9		T198	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	8		T43	12		T230	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T6	1		T150	11		T230	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T158	7		T151	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T2	1		T6	1		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	427	1			T6	1		T13	1		T155	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T297	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T301	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T298	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T2	13		T233	2		T15	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	3		T196	11		T148	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T164	11		T247	8		T251	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T247	15		T170	13		T244	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	8		T26	3		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T145	12		T25	9		T58	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T50	12		T248	8		T269	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	9		T40	2		T63	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T8	14		T55	19		T45	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	8		T45	15		T62	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T159	12		T153	18		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T230	11		T153	2		T157	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T177	9		T64	10		T157	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	2		T230	14		T163	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	12		T230	2		T163	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T159	13		T165	12		T255	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T2	10		T6	12		T144	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T6	15		T151	14		T162	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16