Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20596

1

T1

1

T2

25

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3673

1

T2

10

T3

10

T4

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18786

1

T1

1

T2

35

T3

10

auto[1]

5483

1

T4

16

T5

6

T6

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	447	1			T6	16		T56	1		T178	14
values[0]	12	1			T171	1		T188	1		T301	10
values[1]	518	1			T2	14		T5	6		T45	1
values[2]	693	1			T1	1		T4	20		T43	11
values[3]	548	1			T35	2		T145	28		T177	10
values[4]	635	1			T2	10		T146	1		T40	3
values[5]	2835	1			T4	16		T8	15		T11	1
values[6]	781	1			T146	3		T35	1		T178	8
values[7]	701	1			T3	10		T43	12		T177	19
values[8]	864	1			T6	13		T146	14		T158	7
values[9]	942	1			T2	11		T6	13		T13	1
minimum	15293	1			T5	17		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	581	1			T1	1		T2	14		T43	11
values[1]	710	1			T4	20		T144	9		T145	28
values[2]	539	1			T35	2		T144	8		T177	10
values[3]	2884	1			T2	10		T8	15		T11	1
values[4]	627	1			T4	16		T43	1		T78	1
values[5]	761	1			T3	10		T146	3		T35	1
values[6]	759	1			T43	12		T158	7		T150	11
values[7]	736	1			T6	13		T146	14		T144	12
values[8]	1020	1			T2	11		T13	1		T56	1
values[9]	241	1			T6	29		T178	14		T233	43
minimum	15411	1			T5	23		T7	20		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T1	1		T2	14		T43	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T155	1		T196	12		T148	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T4	9		T64	1		T164	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T144	1		T145	13		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T144	1		T48	6		T50	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T35	2		T177	1		T25	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T8	15		T11	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	10		T40	3		T45	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T153	14		T50	3		T149	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	9		T43	1		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T146	1		T35	1		T177	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T3	3		T178	1		T230	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T43	1		T150	1		T230	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T158	1		T151	1		T64	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	13		T146	1		T144	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T159	14		T165	13		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T2	11		T56	1		T162	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T13	1		T155	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T6	13		T178	1		T234	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T6	16		T233	23		T238	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15188	1			T5	18		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T158	1		T252	15		T236	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T43	10		T150	12		T233	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T155	5		T196	9		T148	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T4	11		T64	1		T164	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T144	8		T145	15		T167	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T144	7		T48	6		T26	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T177	9		T257	2		T300	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T12	6		T237	17		T201	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T62	10		T155	8		T29	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T153	14		T50	2		T149	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	7		T158	13		T63	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T146	2		T177	9		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	7		T178	7		T230	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T43	11		T150	10		T198	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T158	6		T64	8		T265	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T146	13		T144	4		T152	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T51	2		T278	4		T240	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T162	4		T152	11		T64	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T155	15		T150	5		T151	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T178	13		T234	5		T261	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T233	20		T238	6		T304	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	5		T78	2		T148	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T158	13		T236	2		T305	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T56	1		T178	1		T162	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T6	16		T233	23		T231	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T171	1		T188	1		T301	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T2	14		T5	5		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T155	1		T158	1		T196	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	1		T4	9		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T144	1		T167	1		T247	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T26	4		T243	16		T221	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T35	2		T145	13		T177	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T146	1		T144	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	10		T40	3		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T8	15		T11	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T4	9		T43	1		T45	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T146	1		T35	1		T159	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T178	1		T230	12		T153	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T43	1		T177	10		T230	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	3		T230	15		T64	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T6	13		T146	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T158	1		T151	1		T159	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T2	11		T6	13		T144	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T13	1		T155	1		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15153	1			T5	13		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T178	13		T162	4		T152	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T233	20		T238	6		T236	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	1		T233	3		T15	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T155	5		T158	13		T196	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	11		T43	10		T150	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T144	8		T167	16		T247	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T26	3		T221	9		T238	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T145	15		T177	9		T257	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T144	7		T152	13		T48	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T155	8		T302	2		T228	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T12	6		T237	17		T201	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	7		T62	10		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T146	2		T153	23		T157	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T178	7		T230	9		T160	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T43	11		T177	9		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T3	7		T230	6		T64	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T146	13		T150	10		T148	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T158	6		T51	2		T278	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T144	4		T152	5		T64	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T155	15		T150	5		T151	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	1		T2	1		T43	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T155	6		T196	10		T148	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T4	12		T64	2		T164	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T144	9		T145	16		T167	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T144	8		T48	12		T50	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T35	2		T177	10		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T8	1		T11	1		T12	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	1		T40	1		T45	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T153	15		T50	4		T149	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	8		T43	1		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T146	3		T35	1		T177	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T3	8		T178	8		T230	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T43	12		T150	11		T230	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T158	7		T151	1		T64	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T6	1		T146	14		T144	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T159	1		T165	1		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T2	1		T56	1		T162	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T13	1		T155	16		T150	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T6	1		T178	14		T234	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T6	1		T233	21		T238	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15317	1			T5	20		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T158	14		T252	1		T236	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T2	13		T233	2		T15	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T196	11		T148	13		T160	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T4	8		T164	11		T238	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T145	12		T247	15		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T50	4		T165	20		T26	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T25	9		T58	1		T300	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T8	14		T55	19		T45	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	9		T40	2		T45	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T153	13		T50	1		T149	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	8		T63	1		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T177	9		T159	12		T153	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	2		T230	25		T153	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T230	2		T163	12		T166	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T64	10		T265	13		T252	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	12		T144	7		T163	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T159	13		T165	12		T51	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	10		T162	13		T159	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T151	14		T162	6		T290	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T6	12		T234	11		T261	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T6	15		T233	22		T238	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T5	3		T306	11		T307	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T252	14		T112	11		T305	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T56	1		T178	14		T162	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T6	1		T233	21		T231	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T171	1		T188	1		T301	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T2	1		T5	3		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T155	6		T158	14		T196	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	1		T4	12		T43	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T144	9		T167	17		T247	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T26	4		T243	1		T221	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T35	2		T145	16		T177	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T146	1		T144	8		T152	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T2	1		T40	1		T155	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T8	1		T11	1		T12	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	8		T43	1		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T146	3		T35	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T178	8		T230	10		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T43	12		T177	10		T230	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	8		T230	7		T64	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T6	1		T146	14		T150	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T158	7		T151	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	1		T6	1		T144	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T13	1		T155	16		T150	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15293	1			T5	17		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T162	13		T164	11		T234	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T6	15		T233	22		T238	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T301	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T2	13		T5	3		T233	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T196	11		T148	13		T160	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T4	8		T164	11		T247	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T247	15		T16	1		T180	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T26	3		T243	15		T221	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T145	12		T25	9		T58	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T50	12		T165	20		T248	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T2	9		T40	2		T36	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T8	14		T55	19		T45	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	8		T45	15		T62	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T159	12		T153	18		T157	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T230	11		T153	2		T165	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T177	9		T230	2		T163	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	2		T230	14		T64	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	12		T163	5		T227	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T159	13		T165	12		T51	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	10		T6	12		T144	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T151	14		T162	6		T290	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16