Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24269

1

T1

1

T2

35

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21018

1

T2

25

T4

20

T5

17

auto[ADC_CTRL_FILTER_COND_OUT]

3251

1

T1

1

T2

10

T3

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18274

1

T2

10

T5

17

T6

13

auto[1]

5995

1

T1

1

T2

25

T3

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20260

1

T1

1

T2

35

T3

3

auto[1]

4009

1

T3

7

T4

18

T5

5

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	376	1			T5	6		T49	3		T13	10
values[0]	104	1			T1	1		T255	20		T279	22
values[1]	649	1			T146	14		T35	1		T145	28
values[2]	2822	1			T4	16		T5	6		T8	15
values[3]	741	1			T3	10		T4	20		T35	1
values[4]	746	1			T43	12		T45	1		T144	8
values[5]	566	1			T43	1		T144	9		T177	19
values[6]	656	1			T2	24		T35	1		T162	18
values[7]	561	1			T6	13		T13	1		T40	3
values[8]	747	1			T2	11		T155	16		T150	13
values[9]	1370	1			T6	29		T146	3		T43	11
minimum	14931	1			T5	11		T7	20		T9	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	769	1			T1	1		T5	6		T146	15
values[1]	2880	1			T3	10		T4	16		T8	15
values[2]	827	1			T4	20		T144	8		T62	24
values[3]	634	1			T43	13		T45	1		T158	7
values[4]	679	1			T144	9		T162	18		T152	12
values[5]	574	1			T2	24		T6	13		T40	3
values[6]	538	1			T2	11		T13	1		T35	1
values[7]	861	1			T150	13		T151	32		T178	8
values[8]	828	1			T6	29		T45	8		T144	12
values[9]	335	1			T146	3		T43	11		T78	1
minimum	15344	1			T5	17		T7	20		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

4055

1

T2

32

T3

2

T4

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T146	2		T145	13		T64	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	1		T5	5		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T8	15		T11	1		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T3	3		T4	9		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T4	9		T144	1		T62	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T155	1		T234	1		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T43	1		T158	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T43	1		T45	1		T177	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T162	14		T164	12		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T144	1		T152	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	14		T6	13		T233	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	10		T40	3		T230	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	11		T13	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T35	1		T155	1		T157	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T151	15		T178	1		T162	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T150	1		T159	13		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	29		T144	8		T163	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T45	8		T233	13		T159	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T78	1		T302	1		T58	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T146	1		T43	1		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15189	1			T5	13		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T301	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T146	13		T145	15		T64	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	1		T158	26		T150	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T12	6		T177	9		T237	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	7		T4	7		T153	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T4	11		T144	7		T62	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T155	5		T234	11		T169	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T158	6		T233	3		T148	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T43	11		T177	9		T178	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T162	4		T164	4		T29	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T144	8		T152	11		T148	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T233	20		T160	8		T228	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T230	9		T228	6		T248	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T155	8		T152	5		T64	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T155	15		T157	12		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T151	17		T178	7		T162	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T150	12		T198	2		T163	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T144	4		T163	3		T48	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T233	2		T152	13		T64	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T302	2		T58	1		T272	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T146	2		T43	10		T294	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T5	6		T49	3		T13	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T152	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T255	20		T279	13		T308	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T1	1		T309	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T146	1		T145	13		T26	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	1		T158	2		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T8	15		T11	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	9		T5	5		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T4	9		T35	1		T62	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	3		T155	1		T50	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T144	1		T158	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T43	1		T45	1		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T43	1		T233	3		T164	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T144	1		T177	10		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	14		T162	14		T233	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	10		T35	1		T230	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	13		T13	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T40	3		T198	1		T157	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	11		T151	15		T50	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T155	1		T150	1		T163	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	399	1			T6	29		T144	8		T78	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T146	1		T43	1		T45	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14791	1			T5	7		T7	20		T9	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T152	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T279	9		T298	7		T262	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T146	13		T145	15		T26	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T158	26		T150	5		T164	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T12	6		T237	17		T150	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T4	7		T5	1		T153	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	11		T62	10		T177	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	7		T155	5		T179	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T144	7		T158	6		T178	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T43	11		T178	13		T196	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T233	3		T164	4		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T144	8		T177	9		T152	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T162	4		T233	20		T29	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T230	9		T148	8		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T155	8		T178	7		T152	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T198	2		T157	12		T248	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T151	17		T167	15		T160	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T155	15		T150	12		T163	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T144	4		T162	6		T163	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T146	2		T43	10		T233	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	4		T78	2		T148	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T146	15		T145	16		T64	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	1		T5	3		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T8	1		T11	1		T12	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	8		T4	8		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T4	12		T144	8		T62	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T155	6		T234	12		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T43	1		T158	7		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T43	12		T45	1		T177	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T162	5		T164	5		T29	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T144	9		T152	12		T148	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T2	1		T6	1		T233	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	1		T40	1		T230	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	1		T13	1		T155	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T35	1		T155	16		T157	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T151	18		T178	8		T162	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T150	13		T159	1		T198	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	2		T144	5		T163	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T45	1		T233	3		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T78	1		T302	3		T58	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T146	3		T43	11		T294	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15296	1			T5	17		T7	20		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T301	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T145	12		T64	10		T26	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	3		T163	12		T164	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T8	14		T55	19		T45	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T3	2		T4	8		T153	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	8		T62	13		T63	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T238	4		T300	3		T310	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T233	2		T148	13		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T177	9		T196	11		T50	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T162	13		T164	11		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T50	1		T58	1		T245	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T2	13		T6	12		T233	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	9		T40	2		T230	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T2	10		T166	8		T26	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T157	17		T15	1		T244	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T151	14		T162	6		T160	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T159	12		T163	5		T247	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	27		T144	7		T163	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T45	7		T233	12		T159	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T58	1		T244	8		T272	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T170	2		T300	8		T298	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T255	19		T311	4		T312	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T301	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T5	6		T49	3		T13	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T152	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T255	1		T279	10		T308	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T1	1		T309	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T146	14		T145	16		T26	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T35	1		T158	28		T150	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T8	1		T11	1		T12	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	8		T5	3		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T4	12		T35	1		T62	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	8		T155	6		T50	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T144	8		T158	7		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T43	12		T45	1		T178	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T43	1		T233	4		T164	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T144	9		T177	10		T152	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T2	1		T162	5		T233	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	1		T35	1		T230	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	1		T13	1		T155	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	1		T198	3		T157	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	1		T151	18		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T155	16		T150	13		T163	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T6	2		T144	5		T78	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	392	1			T146	3		T43	11		T45	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14931	1			T5	11		T7	20		T9	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T255	19		T279	12		T308	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T309	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T145	12		T26	3		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T163	12		T164	11		T165	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T8	14		T55	19		T45	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T4	8		T5	3		T153	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	8		T62	13		T63	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T3	2		T50	4		T265	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T230	2		T153	15		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T196	11		T252	9		T243	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T233	2		T164	11		T243	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T177	9		T245	10		T268	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	13		T162	13		T233	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	9		T230	11		T50	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T6	12		T166	8		T26	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T40	2		T157	17		T252	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	10		T151	14		T50	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T163	5		T15	1		T247	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T6	27		T144	7		T162	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T45	7		T233	12		T159	25

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20214

1

T1

1

T2

3

T3

8

auto[1]

auto[0]

4055

1

T2

32

T3

2

T4

16