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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.07 96.67 100.00 100.00 98.83 98.33 91.34


Total test records in report: 918
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T798 /workspace/coverage/default/15.adc_ctrl_fsm_reset.1177052141 May 09 02:51:31 PM PDT 24 May 09 03:00:40 PM PDT 24 141691786285 ps
T799 /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2677729715 May 09 02:52:11 PM PDT 24 May 09 02:59:04 PM PDT 24 169475923310 ps
T800 /workspace/coverage/default/8.adc_ctrl_poweron_counter.1816103481 May 09 02:51:03 PM PDT 24 May 09 02:51:12 PM PDT 24 3647652402 ps
T801 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2470214908 May 09 02:31:34 PM PDT 24 May 09 02:31:40 PM PDT 24 383525614 ps
T69 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.567907129 May 09 02:31:23 PM PDT 24 May 09 02:31:33 PM PDT 24 375210670 ps
T59 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.46454951 May 09 02:31:23 PM PDT 24 May 09 02:31:34 PM PDT 24 4522798688 ps
T138 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3029319130 May 09 02:31:27 PM PDT 24 May 09 02:31:35 PM PDT 24 512510845 ps
T65 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.148602771 May 09 02:31:18 PM PDT 24 May 09 02:31:30 PM PDT 24 8867498115 ps
T802 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2581209166 May 09 02:31:40 PM PDT 24 May 09 02:31:48 PM PDT 24 478742604 ps
T141 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1753548210 May 09 02:31:35 PM PDT 24 May 09 02:31:41 PM PDT 24 437578034 ps
T74 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3563317075 May 09 02:31:29 PM PDT 24 May 09 02:31:37 PM PDT 24 411694995 ps
T803 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.533219814 May 09 02:31:30 PM PDT 24 May 09 02:31:37 PM PDT 24 473755087 ps
T66 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1738191921 May 09 02:31:27 PM PDT 24 May 09 02:31:54 PM PDT 24 8042517548 ps
T67 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2127476926 May 09 02:31:26 PM PDT 24 May 09 02:31:44 PM PDT 24 8313194865 ps
T76 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2028791781 May 09 02:31:26 PM PDT 24 May 09 02:31:34 PM PDT 24 396685260 ps
T804 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2231773862 May 09 02:31:23 PM PDT 24 May 09 02:31:30 PM PDT 24 342726091 ps
T142 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2489624585 May 09 02:31:16 PM PDT 24 May 09 02:31:26 PM PDT 24 1266349120 ps
T75 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3430916565 May 09 02:31:16 PM PDT 24 May 09 02:31:25 PM PDT 24 312005628 ps
T70 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.557257930 May 09 02:31:14 PM PDT 24 May 09 02:31:46 PM PDT 24 9002257345 ps
T98 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3607591796 May 09 02:31:36 PM PDT 24 May 09 02:31:52 PM PDT 24 4211417008 ps
T99 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.233832053 May 09 02:31:20 PM PDT 24 May 09 02:31:29 PM PDT 24 476818578 ps
T77 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3196394460 May 09 02:31:25 PM PDT 24 May 09 02:31:33 PM PDT 24 406898777 ps
T119 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1656110729 May 09 02:31:36 PM PDT 24 May 09 02:31:42 PM PDT 24 393340477 ps
T60 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.558331034 May 09 02:31:25 PM PDT 24 May 09 02:31:47 PM PDT 24 4055405455 ps
T123 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3510951387 May 09 02:31:27 PM PDT 24 May 09 02:31:34 PM PDT 24 534828693 ps
T143 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1215885762 May 09 02:31:38 PM PDT 24 May 09 02:31:45 PM PDT 24 406676248 ps
T805 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2375938310 May 09 02:31:36 PM PDT 24 May 09 02:31:42 PM PDT 24 472835004 ps
T120 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3412675727 May 09 02:31:23 PM PDT 24 May 09 02:31:31 PM PDT 24 644200888 ps
T806 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1540947742 May 09 02:31:15 PM PDT 24 May 09 02:31:23 PM PDT 24 387541324 ps
T807 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.240084099 May 09 02:31:38 PM PDT 24 May 09 02:31:45 PM PDT 24 423459295 ps
T61 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.748781829 May 09 02:31:41 PM PDT 24 May 09 02:31:49 PM PDT 24 1858222503 ps
T121 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1450745886 May 09 02:31:25 PM PDT 24 May 09 02:31:32 PM PDT 24 1016497490 ps
T808 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.437613092 May 09 02:31:35 PM PDT 24 May 09 02:31:42 PM PDT 24 484519891 ps
T809 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1808547616 May 09 02:31:40 PM PDT 24 May 09 02:31:47 PM PDT 24 336486211 ps
T810 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2113852848 May 09 02:31:41 PM PDT 24 May 09 02:31:49 PM PDT 24 340934580 ps
T124 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3678814619 May 09 02:31:15 PM PDT 24 May 09 02:31:23 PM PDT 24 319557447 ps
T139 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2553474425 May 09 02:31:29 PM PDT 24 May 09 02:31:37 PM PDT 24 2549445352 ps
T125 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2217189803 May 09 02:31:14 PM PDT 24 May 09 02:31:25 PM PDT 24 1245152355 ps
T84 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2155132034 May 09 02:31:25 PM PDT 24 May 09 02:31:31 PM PDT 24 550209592 ps
T811 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1185760594 May 09 02:31:34 PM PDT 24 May 09 02:31:40 PM PDT 24 404802274 ps
T81 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1682104386 May 09 02:31:27 PM PDT 24 May 09 02:31:34 PM PDT 24 599282373 ps
T812 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3180097699 May 09 02:31:24 PM PDT 24 May 09 02:31:32 PM PDT 24 470925058 ps
T813 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.230594297 May 09 02:31:18 PM PDT 24 May 09 02:31:27 PM PDT 24 520542777 ps
T82 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2025933439 May 09 02:31:45 PM PDT 24 May 09 02:31:53 PM PDT 24 1244707986 ps
T126 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.531303061 May 09 02:31:16 PM PDT 24 May 09 02:31:24 PM PDT 24 1178479777 ps
T83 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3994450314 May 09 02:31:20 PM PDT 24 May 09 02:31:29 PM PDT 24 4639848210 ps
T814 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3071885514 May 09 02:31:29 PM PDT 24 May 09 02:31:36 PM PDT 24 412991921 ps
T815 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3324481266 May 09 02:31:17 PM PDT 24 May 09 02:31:25 PM PDT 24 503886902 ps
T140 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3129994441 May 09 02:31:18 PM PDT 24 May 09 02:31:26 PM PDT 24 676812635 ps
T816 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3060533495 May 09 02:31:35 PM PDT 24 May 09 02:31:41 PM PDT 24 507082703 ps
T817 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.202027576 May 09 02:31:25 PM PDT 24 May 09 02:31:32 PM PDT 24 454815060 ps
T85 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1691028100 May 09 02:31:17 PM PDT 24 May 09 02:31:46 PM PDT 24 8046225084 ps
T818 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1544142904 May 09 02:31:36 PM PDT 24 May 09 02:31:42 PM PDT 24 465254121 ps
T819 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1024038407 May 09 02:31:26 PM PDT 24 May 09 02:31:34 PM PDT 24 461864753 ps
T86 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2240180199 May 09 02:31:16 PM PDT 24 May 09 02:31:45 PM PDT 24 8109474213 ps
T820 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4105749333 May 09 02:31:26 PM PDT 24 May 09 02:31:44 PM PDT 24 8427950280 ps
T821 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1447066112 May 09 02:31:39 PM PDT 24 May 09 02:31:46 PM PDT 24 427052287 ps
T822 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1601801358 May 09 02:31:25 PM PDT 24 May 09 02:31:32 PM PDT 24 557262235 ps
T823 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3399330314 May 09 02:31:35 PM PDT 24 May 09 02:31:41 PM PDT 24 541692170 ps
T824 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.908788929 May 09 02:31:41 PM PDT 24 May 09 02:31:51 PM PDT 24 517935244 ps
T825 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2848780456 May 09 02:31:30 PM PDT 24 May 09 02:31:43 PM PDT 24 8769808546 ps
T826 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3907144643 May 09 02:31:38 PM PDT 24 May 09 02:31:45 PM PDT 24 345246778 ps
T127 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2019003541 May 09 02:31:27 PM PDT 24 May 09 02:31:34 PM PDT 24 595288416 ps
T827 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.853007291 May 09 02:31:15 PM PDT 24 May 09 02:31:25 PM PDT 24 833134584 ps
T128 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1078576496 May 09 02:31:28 PM PDT 24 May 09 02:31:35 PM PDT 24 521294793 ps
T828 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.377809021 May 09 02:31:39 PM PDT 24 May 09 02:31:49 PM PDT 24 9996073412 ps
T829 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.342228479 May 09 02:31:18 PM PDT 24 May 09 02:31:26 PM PDT 24 645173214 ps
T830 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.402198816 May 09 02:31:27 PM PDT 24 May 09 02:31:34 PM PDT 24 309186382 ps
T831 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3456135238 May 09 02:31:39 PM PDT 24 May 09 02:31:46 PM PDT 24 462391999 ps
T129 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1287351022 May 09 02:31:18 PM PDT 24 May 09 02:31:29 PM PDT 24 4227757572 ps
T832 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.563508872 May 09 02:31:33 PM PDT 24 May 09 02:31:40 PM PDT 24 411992206 ps
T833 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2279072512 May 09 02:31:15 PM PDT 24 May 09 02:31:23 PM PDT 24 296947631 ps
T834 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3508285133 May 09 02:31:16 PM PDT 24 May 09 02:31:27 PM PDT 24 1372402562 ps
T835 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2954996450 May 09 02:31:27 PM PDT 24 May 09 02:31:34 PM PDT 24 784141542 ps
T836 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.84202981 May 09 02:31:26 PM PDT 24 May 09 02:31:35 PM PDT 24 4799685862 ps
T837 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.504007445 May 09 02:31:17 PM PDT 24 May 09 02:31:27 PM PDT 24 3932563576 ps
T838 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3576220100 May 09 02:31:29 PM PDT 24 May 09 02:31:36 PM PDT 24 526999025 ps
T839 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2158896229 May 09 02:31:15 PM PDT 24 May 09 02:31:32 PM PDT 24 4396139766 ps
T840 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3526210137 May 09 02:31:13 PM PDT 24 May 09 02:31:22 PM PDT 24 460425089 ps
T841 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1146982382 May 09 02:31:29 PM PDT 24 May 09 02:31:43 PM PDT 24 2024056489 ps
T842 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3757533846 May 09 02:31:13 PM PDT 24 May 09 02:31:22 PM PDT 24 854840750 ps
T843 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1156818407 May 09 02:31:36 PM PDT 24 May 09 02:31:41 PM PDT 24 514244248 ps
T844 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1311978615 May 09 02:31:24 PM PDT 24 May 09 02:31:32 PM PDT 24 508782999 ps
T845 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.502562861 May 09 02:31:23 PM PDT 24 May 09 02:31:31 PM PDT 24 754169322 ps
T130 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.993369676 May 09 02:31:13 PM PDT 24 May 09 02:31:21 PM PDT 24 1193734916 ps
T846 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1878769375 May 09 02:31:36 PM PDT 24 May 09 02:31:42 PM PDT 24 306846619 ps
T847 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2158325641 May 09 02:31:28 PM PDT 24 May 09 02:31:37 PM PDT 24 384687398 ps
T848 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3580720108 May 09 02:31:16 PM PDT 24 May 09 02:31:24 PM PDT 24 469865532 ps
T849 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3262766857 May 09 02:31:40 PM PDT 24 May 09 02:31:46 PM PDT 24 409013809 ps
T850 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1079683132 May 09 02:31:40 PM PDT 24 May 09 02:31:46 PM PDT 24 409527811 ps
T851 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1266270406 May 09 02:31:27 PM PDT 24 May 09 02:31:40 PM PDT 24 8482096057 ps
T852 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1062809541 May 09 02:31:36 PM PDT 24 May 09 02:31:42 PM PDT 24 452073236 ps
T853 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3462809102 May 09 02:31:34 PM PDT 24 May 09 02:31:41 PM PDT 24 329686937 ps
T131 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4279652968 May 09 02:31:13 PM PDT 24 May 09 02:31:45 PM PDT 24 21707235430 ps
T854 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2375212768 May 09 02:31:28 PM PDT 24 May 09 02:31:36 PM PDT 24 559614743 ps
T855 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1172599823 May 09 02:31:15 PM PDT 24 May 09 02:31:25 PM PDT 24 616163493 ps
T856 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2805081507 May 09 02:31:29 PM PDT 24 May 09 02:31:48 PM PDT 24 3892310609 ps
T132 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.711625209 May 09 02:31:14 PM PDT 24 May 09 02:31:23 PM PDT 24 324447488 ps
T857 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2725820771 May 09 02:31:15 PM PDT 24 May 09 02:31:24 PM PDT 24 985369221 ps
T858 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1228165908 May 09 02:31:17 PM PDT 24 May 09 02:31:27 PM PDT 24 540390855 ps
T859 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1287081586 May 09 02:31:26 PM PDT 24 May 09 02:31:33 PM PDT 24 487926969 ps
T860 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1692098415 May 09 02:31:39 PM PDT 24 May 09 02:31:45 PM PDT 24 434445774 ps
T341 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2745518454 May 09 02:31:20 PM PDT 24 May 09 02:31:47 PM PDT 24 8275083440 ps
T861 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2465259134 May 09 02:31:41 PM PDT 24 May 09 02:31:48 PM PDT 24 511976215 ps
T862 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1940049904 May 09 02:31:35 PM PDT 24 May 09 02:31:42 PM PDT 24 590272317 ps
T863 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3533233484 May 09 02:31:27 PM PDT 24 May 09 02:31:43 PM PDT 24 4296940711 ps
T864 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3259469596 May 09 02:31:26 PM PDT 24 May 09 02:31:33 PM PDT 24 396215380 ps
T342 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3857398145 May 09 02:31:28 PM PDT 24 May 09 02:31:38 PM PDT 24 4653843120 ps
T865 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3354958954 May 09 02:31:12 PM PDT 24 May 09 02:31:22 PM PDT 24 463014694 ps
T866 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3370661360 May 09 02:31:30 PM PDT 24 May 09 02:31:38 PM PDT 24 583836004 ps
T867 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3464627909 May 09 02:31:23 PM PDT 24 May 09 02:31:31 PM PDT 24 448069687 ps
T868 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2810023424 May 09 02:31:38 PM PDT 24 May 09 02:31:44 PM PDT 24 443997511 ps
T869 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.615298834 May 09 02:31:15 PM PDT 24 May 09 02:31:24 PM PDT 24 611711521 ps
T870 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4100419935 May 09 02:31:30 PM PDT 24 May 09 02:31:37 PM PDT 24 558996180 ps
T871 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.325965915 May 09 02:31:17 PM PDT 24 May 09 02:31:51 PM PDT 24 54321692446 ps
T872 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.79023748 May 09 02:31:36 PM PDT 24 May 09 02:31:52 PM PDT 24 4468633459 ps
T873 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2781806992 May 09 02:31:25 PM PDT 24 May 09 02:31:38 PM PDT 24 8977877242 ps
T874 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.881243848 May 09 02:31:28 PM PDT 24 May 09 02:31:35 PM PDT 24 291896758 ps
T875 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2276794300 May 09 02:31:35 PM PDT 24 May 09 02:31:41 PM PDT 24 493944766 ps
T876 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2039473581 May 09 02:31:17 PM PDT 24 May 09 02:31:28 PM PDT 24 3339963603 ps
T877 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3383683397 May 09 02:31:23 PM PDT 24 May 09 02:31:31 PM PDT 24 599948867 ps
T133 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1794338840 May 09 02:31:17 PM PDT 24 May 09 02:31:27 PM PDT 24 704049469 ps
T343 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.736160032 May 09 02:31:39 PM PDT 24 May 09 02:31:48 PM PDT 24 4357827517 ps
T878 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1185912398 May 09 02:31:36 PM PDT 24 May 09 02:31:42 PM PDT 24 542195893 ps
T879 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.200151558 May 09 02:31:26 PM PDT 24 May 09 02:31:38 PM PDT 24 8533457015 ps
T880 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2632464786 May 09 02:31:29 PM PDT 24 May 09 02:31:41 PM PDT 24 4772205881 ps
T881 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1377930076 May 09 02:31:15 PM PDT 24 May 09 02:31:23 PM PDT 24 418318753 ps
T882 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2678470812 May 09 02:31:25 PM PDT 24 May 09 02:31:32 PM PDT 24 437842527 ps
T883 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3416121109 May 09 02:31:15 PM PDT 24 May 09 02:31:31 PM PDT 24 2654243638 ps
T134 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1206843107 May 09 02:31:16 PM PDT 24 May 09 02:31:51 PM PDT 24 26537589190 ps
T884 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.869582098 May 09 02:31:15 PM PDT 24 May 09 02:31:27 PM PDT 24 4223089770 ps
T885 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3381603024 May 09 02:31:13 PM PDT 24 May 09 02:31:24 PM PDT 24 4065648533 ps
T886 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.4167201008 May 09 02:31:35 PM PDT 24 May 09 02:31:41 PM PDT 24 373038641 ps
T887 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3238915925 May 09 02:31:39 PM PDT 24 May 09 02:31:46 PM PDT 24 481804783 ps
T888 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.286414145 May 09 02:31:34 PM PDT 24 May 09 02:31:42 PM PDT 24 2243279325 ps
T889 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3151159729 May 09 02:31:30 PM PDT 24 May 09 02:31:36 PM PDT 24 456433812 ps
T890 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4097933125 May 09 02:31:14 PM PDT 24 May 09 02:31:22 PM PDT 24 568266414 ps
T891 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1586435304 May 09 02:31:38 PM PDT 24 May 09 02:31:45 PM PDT 24 456373964 ps
T892 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3895896570 May 09 02:31:30 PM PDT 24 May 09 02:31:37 PM PDT 24 438139737 ps
T893 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1491148182 May 09 02:31:14 PM PDT 24 May 09 02:31:22 PM PDT 24 400490060 ps
T894 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.920897611 May 09 02:31:38 PM PDT 24 May 09 02:31:44 PM PDT 24 505953513 ps
T895 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2662219858 May 09 02:31:16 PM PDT 24 May 09 02:31:27 PM PDT 24 4708049425 ps
T896 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3277679167 May 09 02:31:17 PM PDT 24 May 09 02:31:25 PM PDT 24 496296968 ps
T897 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3711797715 May 09 02:31:18 PM PDT 24 May 09 02:31:28 PM PDT 24 975804285 ps
T898 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.984348813 May 09 02:31:30 PM PDT 24 May 09 02:31:38 PM PDT 24 4474599042 ps
T899 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2179634821 May 09 02:31:22 PM PDT 24 May 09 02:31:30 PM PDT 24 502255992 ps
T135 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1468880572 May 09 02:31:25 PM PDT 24 May 09 02:31:32 PM PDT 24 531393076 ps
T900 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4174621340 May 09 02:31:23 PM PDT 24 May 09 02:31:31 PM PDT 24 494960614 ps
T136 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4167821900 May 09 02:31:20 PM PDT 24 May 09 02:31:29 PM PDT 24 372445232 ps
T901 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1462795391 May 09 02:31:35 PM PDT 24 May 09 02:31:41 PM PDT 24 385351804 ps
T902 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1648091514 May 09 02:31:27 PM PDT 24 May 09 02:31:34 PM PDT 24 325071424 ps
T903 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.841454728 May 09 02:31:23 PM PDT 24 May 09 02:31:32 PM PDT 24 548923499 ps
T904 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.197214927 May 09 02:31:14 PM PDT 24 May 09 02:31:25 PM PDT 24 2062284900 ps
T905 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1527066880 May 09 02:31:45 PM PDT 24 May 09 02:31:52 PM PDT 24 403149339 ps
T906 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.184317338 May 09 02:31:26 PM PDT 24 May 09 02:31:33 PM PDT 24 475571299 ps
T907 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.59936940 May 09 02:31:36 PM PDT 24 May 09 02:31:43 PM PDT 24 515750820 ps
T908 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3738251060 May 09 02:31:18 PM PDT 24 May 09 02:31:27 PM PDT 24 490102496 ps
T909 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3360208675 May 09 02:31:44 PM PDT 24 May 09 02:31:51 PM PDT 24 525353069 ps
T910 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3404321446 May 09 02:31:39 PM PDT 24 May 09 02:31:45 PM PDT 24 479057519 ps
T911 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3072740497 May 09 02:31:27 PM PDT 24 May 09 02:31:34 PM PDT 24 442721328 ps
T912 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3042789292 May 09 02:31:22 PM PDT 24 May 09 02:31:32 PM PDT 24 3940864243 ps
T913 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3621952807 May 09 02:31:26 PM PDT 24 May 09 02:31:40 PM PDT 24 4428539824 ps
T914 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1356047958 May 09 02:31:37 PM PDT 24 May 09 02:31:43 PM PDT 24 533851115 ps
T915 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1617858302 May 09 02:31:41 PM PDT 24 May 09 02:31:55 PM PDT 24 2079654014 ps
T916 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2287122302 May 09 02:31:26 PM PDT 24 May 09 02:31:33 PM PDT 24 289758129 ps
T137 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3808012565 May 09 02:31:14 PM PDT 24 May 09 02:31:47 PM PDT 24 52551379309 ps
T917 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3687670107 May 09 02:31:38 PM PDT 24 May 09 02:31:44 PM PDT 24 322326548 ps
T918 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3147989721 May 09 02:31:27 PM PDT 24 May 09 02:31:34 PM PDT 24 390793561 ps

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1619812366
Short name T5
Test name
Test status
Simulation time 119831876442 ps
CPU time 72.45 seconds
Started May 09 02:53:35 PM PDT 24
Finished May 09 02:54:48 PM PDT 24
Peak memory 211092 kb
Host smart-66fe5069-5940-4e8f-83f8-be70ce317b3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619812366 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1619812366
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1596229294
Short name T56
Test name
Test status
Simulation time 240133461060 ps
CPU time 729.79 seconds
Started May 09 02:52:21 PM PDT 24
Finished May 09 03:04:34 PM PDT 24
Peak memory 219000 kb
Host smart-7edbdafa-e0d9-4237-93b7-df8b7e430969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596229294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1596229294
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1544657804
Short name T4
Test name
Test status
Simulation time 354476824617 ps
CPU time 104.87 seconds
Started May 09 02:52:12 PM PDT 24
Finished May 09 02:53:58 PM PDT 24
Peak memory 202172 kb
Host smart-7ac66086-c9b0-43ca-8b6d-dd38e1ed210a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544657804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1544657804
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2386004107
Short name T50
Test name
Test status
Simulation time 600600425880 ps
CPU time 255.28 seconds
Started May 09 02:51:02 PM PDT 24
Finished May 09 02:55:22 PM PDT 24
Peak memory 218304 kb
Host smart-69caddaa-9905-476c-844e-9a9b62638814
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386004107 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2386004107
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.911527291
Short name T18
Test name
Test status
Simulation time 42831069540 ps
CPU time 100.98 seconds
Started May 09 02:51:20 PM PDT 24
Finished May 09 02:53:05 PM PDT 24
Peak memory 202904 kb
Host smart-cc163dac-4d98-4508-8ace-6114f4a76dc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911527291 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.911527291
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1013534647
Short name T64
Test name
Test status
Simulation time 531509045509 ps
CPU time 418.25 seconds
Started May 09 02:53:34 PM PDT 24
Finished May 09 03:00:33 PM PDT 24
Peak memory 202304 kb
Host smart-bcedae86-e109-4a29-84d9-ab1d4c457cae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013534647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1013534647
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2876465555
Short name T163
Test name
Test status
Simulation time 551165710778 ps
CPU time 1094.5 seconds
Started May 09 02:51:04 PM PDT 24
Finished May 09 03:09:26 PM PDT 24
Peak memory 202556 kb
Host smart-f2d89b0c-8e37-48e4-b489-98c2cdc50ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876465555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2876465555
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3636820141
Short name T160
Test name
Test status
Simulation time 499335279920 ps
CPU time 209.56 seconds
Started May 09 02:53:06 PM PDT 24
Finished May 09 02:56:37 PM PDT 24
Peak memory 202348 kb
Host smart-079b378d-a88e-453e-9476-ef730f9d4d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636820141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3636820141
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.4069504726
Short name T2
Test name
Test status
Simulation time 554409736750 ps
CPU time 652.12 seconds
Started May 09 02:54:14 PM PDT 24
Finished May 09 03:05:07 PM PDT 24
Peak memory 202268 kb
Host smart-016e427b-8e1a-45b2-847c-c442cdc70ff3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069504726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.4069504726
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1586397503
Short name T153
Test name
Test status
Simulation time 533164055986 ps
CPU time 102.89 seconds
Started May 09 02:51:23 PM PDT 24
Finished May 09 02:53:08 PM PDT 24
Peak memory 202340 kb
Host smart-54019d46-e31e-41d0-84fa-48197694dd71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586397503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1586397503
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.567907129
Short name T69
Test name
Test status
Simulation time 375210670 ps
CPU time 3.29 seconds
Started May 09 02:31:23 PM PDT 24
Finished May 09 02:31:33 PM PDT 24
Peak memory 201460 kb
Host smart-793dbf66-770a-4cb8-a5b8-b743046a80bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567907129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.567907129
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1490082696
Short name T233
Test name
Test status
Simulation time 598485874006 ps
CPU time 1339.26 seconds
Started May 09 02:51:18 PM PDT 24
Finished May 09 03:13:42 PM PDT 24
Peak memory 202344 kb
Host smart-4dce75ed-00ae-46ed-a218-948a47e776c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490082696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1490082696
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3401359420
Short name T252
Test name
Test status
Simulation time 509151573687 ps
CPU time 619.45 seconds
Started May 09 02:51:30 PM PDT 24
Finished May 09 03:01:54 PM PDT 24
Peak memory 202352 kb
Host smart-78da17ca-f140-4220-8d4d-177415fc7289
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401359420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3401359420
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2424463454
Short name T170
Test name
Test status
Simulation time 369705643702 ps
CPU time 495.91 seconds
Started May 09 02:52:43 PM PDT 24
Finished May 09 03:01:00 PM PDT 24
Peak memory 202356 kb
Host smart-172973ab-88dd-47d2-84c2-ef67db0229b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424463454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2424463454
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1383278321
Short name T221
Test name
Test status
Simulation time 682474942465 ps
CPU time 476.17 seconds
Started May 09 02:54:20 PM PDT 24
Finished May 09 03:02:18 PM PDT 24
Peak memory 218396 kb
Host smart-1290cb40-efe1-4ee7-bde6-479189702159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383278321 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1383278321
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1914656165
Short name T199
Test name
Test status
Simulation time 526458056 ps
CPU time 1 seconds
Started May 09 02:51:10 PM PDT 24
Finished May 09 02:51:19 PM PDT 24
Peak memory 201884 kb
Host smart-00ccfbde-bf83-4e48-b279-9571e83e7f66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914656165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1914656165
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.793445246
Short name T15
Test name
Test status
Simulation time 121669748026 ps
CPU time 166.14 seconds
Started May 09 02:51:26 PM PDT 24
Finished May 09 02:54:15 PM PDT 24
Peak memory 219172 kb
Host smart-c19a010f-5266-479a-9f13-a72b71aa8253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793445246 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.793445246
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3678814619
Short name T124
Test name
Test status
Simulation time 319557447 ps
CPU time 1.64 seconds
Started May 09 02:31:15 PM PDT 24
Finished May 09 02:31:23 PM PDT 24
Peak memory 201248 kb
Host smart-d5e3928d-1208-4f61-b7bf-ae8acc986387
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678814619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3678814619
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1294299403
Short name T158
Test name
Test status
Simulation time 500745259913 ps
CPU time 1155.5 seconds
Started May 09 02:51:31 PM PDT 24
Finished May 09 03:10:50 PM PDT 24
Peak memory 202328 kb
Host smart-c9a1bed9-f987-46d4-9a00-69e3479b0a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294299403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1294299403
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2025603648
Short name T72
Test name
Test status
Simulation time 7844077355 ps
CPU time 5.79 seconds
Started May 09 02:50:52 PM PDT 24
Finished May 09 02:51:02 PM PDT 24
Peak memory 218900 kb
Host smart-8f8f2938-e053-4108-b9f3-4b51b62a6312
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025603648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2025603648
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.600600141
Short name T152
Test name
Test status
Simulation time 491892433230 ps
CPU time 221.76 seconds
Started May 09 02:50:52 PM PDT 24
Finished May 09 02:54:38 PM PDT 24
Peak memory 202408 kb
Host smart-7226afdd-c25a-4563-89d3-e4e5f9491fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600600141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.600600141
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.952631681
Short name T157
Test name
Test status
Simulation time 344980802582 ps
CPU time 111.52 seconds
Started May 09 02:53:36 PM PDT 24
Finished May 09 02:55:28 PM PDT 24
Peak memory 202272 kb
Host smart-303a31e1-c67b-483f-9fad-cddbf442a913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952631681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.952631681
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3995196304
Short name T237
Test name
Test status
Simulation time 332521477765 ps
CPU time 108.1 seconds
Started May 09 02:51:58 PM PDT 24
Finished May 09 02:53:47 PM PDT 24
Peak memory 202324 kb
Host smart-f4858582-5b74-4814-86e2-07b7c2f33a67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995196304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3995196304
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.77461188
Short name T300
Test name
Test status
Simulation time 531033944107 ps
CPU time 412.55 seconds
Started May 09 02:51:07 PM PDT 24
Finished May 09 02:58:07 PM PDT 24
Peak memory 202336 kb
Host smart-907e3374-09de-4a11-8c9e-aa2138d49f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77461188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.77461188
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1879045875
Short name T320
Test name
Test status
Simulation time 499871698708 ps
CPU time 202.88 seconds
Started May 09 02:51:00 PM PDT 24
Finished May 09 02:54:27 PM PDT 24
Peak memory 202324 kb
Host smart-bac023d7-b49d-4c7b-bff6-7aa26c35a441
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879045875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1879045875
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3972238387
Short name T241
Test name
Test status
Simulation time 496799329092 ps
CPU time 623.15 seconds
Started May 09 02:51:47 PM PDT 24
Finished May 09 03:02:13 PM PDT 24
Peak memory 202300 kb
Host smart-916e9a8e-b37a-4331-9601-fb6f1af55758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972238387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3972238387
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.942205524
Short name T244
Test name
Test status
Simulation time 590762076436 ps
CPU time 738.93 seconds
Started May 09 02:51:03 PM PDT 24
Finished May 09 03:03:28 PM PDT 24
Peak memory 202388 kb
Host smart-0636396d-6136-4d59-9cb7-c0837bfffd26
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942205524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.942205524
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2955449581
Short name T238
Test name
Test status
Simulation time 554493710490 ps
CPU time 583.52 seconds
Started May 09 02:53:04 PM PDT 24
Finished May 09 03:02:49 PM PDT 24
Peak memory 202348 kb
Host smart-8de4c84f-7933-4fa8-9e08-9bf9d4e407d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955449581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2955449581
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.182632616
Short name T234
Test name
Test status
Simulation time 330347935300 ps
CPU time 231.7 seconds
Started May 09 02:51:45 PM PDT 24
Finished May 09 02:55:38 PM PDT 24
Peak memory 202424 kb
Host smart-4ab5ce41-6363-4304-b345-09e284d3a1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182632616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.182632616
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.4286853544
Short name T253
Test name
Test status
Simulation time 368261602588 ps
CPU time 218.95 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:55:10 PM PDT 24
Peak memory 202316 kb
Host smart-cfb1588f-0c2a-4c18-9e30-ad2c5c9c4e7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286853544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.4286853544
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1562055916
Short name T281
Test name
Test status
Simulation time 569392806780 ps
CPU time 1336.76 seconds
Started May 09 02:52:42 PM PDT 24
Finished May 09 03:15:01 PM PDT 24
Peak memory 202340 kb
Host smart-d767fa62-47e5-4b3b-9693-9a4ff2cabbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562055916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1562055916
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1691028100
Short name T85
Test name
Test status
Simulation time 8046225084 ps
CPU time 22.08 seconds
Started May 09 02:31:17 PM PDT 24
Finished May 09 02:31:46 PM PDT 24
Peak memory 201520 kb
Host smart-20f985ee-de10-4247-bb49-6dfc18446dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691028100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1691028100
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.577435071
Short name T312
Test name
Test status
Simulation time 570223298318 ps
CPU time 1157.71 seconds
Started May 09 02:51:31 PM PDT 24
Finished May 09 03:10:52 PM PDT 24
Peak memory 202312 kb
Host smart-8ff61796-761b-451f-baf4-96f3c043cf28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577435071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.577435071
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2724074415
Short name T226
Test name
Test status
Simulation time 203482014523 ps
CPU time 75.11 seconds
Started May 09 02:51:14 PM PDT 24
Finished May 09 02:52:37 PM PDT 24
Peak memory 202300 kb
Host smart-b68b31dd-7615-43bd-9b48-25d37ad4b9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724074415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2724074415
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3090055794
Short name T34
Test name
Test status
Simulation time 146176315486 ps
CPU time 176.94 seconds
Started May 09 02:51:28 PM PDT 24
Finished May 09 02:54:28 PM PDT 24
Peak memory 210980 kb
Host smart-34a36542-124e-4cd2-8171-4f5fb072331e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090055794 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3090055794
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3682611086
Short name T171
Test name
Test status
Simulation time 491892920935 ps
CPU time 189.43 seconds
Started May 09 02:51:39 PM PDT 24
Finished May 09 02:54:49 PM PDT 24
Peak memory 202312 kb
Host smart-d3faab19-55e6-4877-9e36-6fd7f5cb4375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682611086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3682611086
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1305223076
Short name T284
Test name
Test status
Simulation time 564122212653 ps
CPU time 239.13 seconds
Started May 09 02:51:38 PM PDT 24
Finished May 09 02:55:38 PM PDT 24
Peak memory 202312 kb
Host smart-7f6d5cf9-fa80-451b-9af7-76260eeed114
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305223076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1305223076
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1692327271
Short name T182
Test name
Test status
Simulation time 522049834044 ps
CPU time 141.64 seconds
Started May 09 02:51:19 PM PDT 24
Finished May 09 02:53:45 PM PDT 24
Peak memory 202296 kb
Host smart-13cf69ee-1119-4c79-937b-815fed69509c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692327271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1692327271
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3863584014
Short name T274
Test name
Test status
Simulation time 327188675132 ps
CPU time 192.56 seconds
Started May 09 02:51:41 PM PDT 24
Finished May 09 02:54:55 PM PDT 24
Peak memory 202328 kb
Host smart-4c64525b-4412-4509-8d31-e036716a86b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863584014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3863584014
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2005117895
Short name T249
Test name
Test status
Simulation time 498645034835 ps
CPU time 572.11 seconds
Started May 09 02:51:33 PM PDT 24
Finished May 09 03:01:08 PM PDT 24
Peak memory 202300 kb
Host smart-8df1cb2a-0707-4ae1-b1c7-c9e860b691d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005117895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2005117895
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4279652968
Short name T131
Test name
Test status
Simulation time 21707235430 ps
CPU time 25.24 seconds
Started May 09 02:31:13 PM PDT 24
Finished May 09 02:31:45 PM PDT 24
Peak memory 201576 kb
Host smart-7a9531ff-74e0-45e3-bcf9-e3e528534739
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279652968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.4279652968
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.114743975
Short name T230
Test name
Test status
Simulation time 533673283880 ps
CPU time 340.92 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:57:00 PM PDT 24
Peak memory 202452 kb
Host smart-5df20753-d64e-4509-85d9-7202efa3a155
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114743975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.114743975
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1121678523
Short name T24
Test name
Test status
Simulation time 141972933851 ps
CPU time 83.2 seconds
Started May 09 02:51:01 PM PDT 24
Finished May 09 02:52:29 PM PDT 24
Peak memory 202408 kb
Host smart-74924ab1-d2a7-4271-bc4d-103dd896807c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121678523 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1121678523
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1897847744
Short name T278
Test name
Test status
Simulation time 493198325371 ps
CPU time 552.24 seconds
Started May 09 02:50:37 PM PDT 24
Finished May 09 03:00:01 PM PDT 24
Peak memory 202452 kb
Host smart-0405e633-38e8-4e75-8b91-91fabde6195d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897847744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1897847744
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.534167374
Short name T43
Test name
Test status
Simulation time 490848569424 ps
CPU time 1128.94 seconds
Started May 09 02:51:21 PM PDT 24
Finished May 09 03:10:13 PM PDT 24
Peak memory 202372 kb
Host smart-a606cd79-064c-4775-a480-dfc5c9a0157e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534167374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.534167374
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.401028395
Short name T289
Test name
Test status
Simulation time 659424238310 ps
CPU time 1606.58 seconds
Started May 09 02:51:22 PM PDT 24
Finished May 09 03:18:12 PM PDT 24
Peak memory 202408 kb
Host smart-109b417a-9608-4654-93c5-e49ec79a98c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401028395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
401028395
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2439837325
Short name T16
Test name
Test status
Simulation time 201062455460 ps
CPU time 452.53 seconds
Started May 09 02:51:41 PM PDT 24
Finished May 09 02:59:15 PM PDT 24
Peak memory 211072 kb
Host smart-ed3d8796-f9d2-40d9-b023-413e0c3350b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439837325 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2439837325
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2551430902
Short name T63
Test name
Test status
Simulation time 175044000584 ps
CPU time 113.34 seconds
Started May 09 02:52:00 PM PDT 24
Finished May 09 02:53:56 PM PDT 24
Peak memory 202380 kb
Host smart-82ec18bf-8201-4309-a54c-7ba0f67e1fed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551430902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2551430902
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3928144838
Short name T332
Test name
Test status
Simulation time 324822057906 ps
CPU time 728.01 seconds
Started May 09 02:51:02 PM PDT 24
Finished May 09 03:03:16 PM PDT 24
Peak memory 202636 kb
Host smart-e469e637-47d6-4124-b7ac-3447a7308e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928144838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3928144838
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3632366702
Short name T297
Test name
Test status
Simulation time 96061791640 ps
CPU time 70.66 seconds
Started May 09 02:51:05 PM PDT 24
Finished May 09 02:52:22 PM PDT 24
Peak memory 210940 kb
Host smart-dac1d8cb-8c4a-430e-9d7f-37844c523547
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632366702 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3632366702
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1373666757
Short name T301
Test name
Test status
Simulation time 557823176516 ps
CPU time 512.19 seconds
Started May 09 02:50:51 PM PDT 24
Finished May 09 02:59:28 PM PDT 24
Peak memory 202328 kb
Host smart-a460cbe7-42b5-4286-adb4-171583a4c38c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373666757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1373666757
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.4272369364
Short name T13
Test name
Test status
Simulation time 95855495111 ps
CPU time 302.42 seconds
Started May 09 02:51:36 PM PDT 24
Finished May 09 02:56:40 PM PDT 24
Peak memory 211060 kb
Host smart-5e4f372e-d02b-4f46-ae1c-a8ccd2171a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272369364 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.4272369364
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2506640348
Short name T219
Test name
Test status
Simulation time 73402367045 ps
CPU time 239.36 seconds
Started May 09 02:51:59 PM PDT 24
Finished May 09 02:56:00 PM PDT 24
Peak memory 202680 kb
Host smart-b0b8d5c0-3676-4fa2-8abe-e9e1519511e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506640348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2506640348
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3548533661
Short name T267
Test name
Test status
Simulation time 320930570179 ps
CPU time 203.75 seconds
Started May 09 02:53:18 PM PDT 24
Finished May 09 02:56:42 PM PDT 24
Peak memory 202300 kb
Host smart-e7fab654-9022-4a94-ab95-be643227df48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548533661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3548533661
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2912711288
Short name T277
Test name
Test status
Simulation time 519851116516 ps
CPU time 222.67 seconds
Started May 09 02:54:11 PM PDT 24
Finished May 09 02:57:55 PM PDT 24
Peak memory 202332 kb
Host smart-2163b39b-6b37-4f27-b211-ba0ba93321f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912711288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2912711288
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2419406356
Short name T298
Test name
Test status
Simulation time 362196422094 ps
CPU time 872.95 seconds
Started May 09 02:51:01 PM PDT 24
Finished May 09 03:05:40 PM PDT 24
Peak memory 202332 kb
Host smart-699a8a5c-58f1-4f68-b569-ab6327eeb9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419406356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2419406356
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2744328334
Short name T26
Test name
Test status
Simulation time 327687744900 ps
CPU time 591.22 seconds
Started May 09 02:50:49 PM PDT 24
Finished May 09 03:00:46 PM PDT 24
Peak memory 202348 kb
Host smart-66284c80-e1e7-4d21-8c7e-691c47cd2115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744328334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2744328334
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3474385461
Short name T292
Test name
Test status
Simulation time 165237442042 ps
CPU time 129.08 seconds
Started May 09 02:53:35 PM PDT 24
Finished May 09 02:55:45 PM PDT 24
Peak memory 202276 kb
Host smart-af91b07d-ca76-4a96-b2d8-80bb220f2df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474385461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3474385461
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.368907245
Short name T271
Test name
Test status
Simulation time 523295530720 ps
CPU time 331.06 seconds
Started May 09 02:51:08 PM PDT 24
Finished May 09 02:56:47 PM PDT 24
Peak memory 202412 kb
Host smart-9f779182-f505-4e71-b8bf-296aa6f167ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368907245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.368907245
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1113881638
Short name T299
Test name
Test status
Simulation time 344146182645 ps
CPU time 213.33 seconds
Started May 09 02:51:19 PM PDT 24
Finished May 09 02:54:57 PM PDT 24
Peak memory 202400 kb
Host smart-84c9823a-b243-480b-a5cb-11b644dc090d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113881638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1113881638
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2968374544
Short name T309
Test name
Test status
Simulation time 652353842322 ps
CPU time 741.65 seconds
Started May 09 02:51:37 PM PDT 24
Finished May 09 03:04:00 PM PDT 24
Peak memory 202264 kb
Host smart-dbc80f14-13a6-416a-a502-91f429af3de0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968374544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2968374544
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2505546213
Short name T188
Test name
Test status
Simulation time 494406142340 ps
CPU time 291 seconds
Started May 09 02:51:41 PM PDT 24
Finished May 09 02:56:34 PM PDT 24
Peak memory 202312 kb
Host smart-9d613a7a-8e14-4b91-866e-f841989bac97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505546213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2505546213
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3984108433
Short name T224
Test name
Test status
Simulation time 490037016759 ps
CPU time 329.66 seconds
Started May 09 02:52:33 PM PDT 24
Finished May 09 02:58:04 PM PDT 24
Peak memory 202388 kb
Host smart-a377d0b4-bb3d-4fc8-bcd3-a30f4ea35981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984108433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3984108433
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.677073365
Short name T248
Test name
Test status
Simulation time 527401679476 ps
CPU time 1339.81 seconds
Started May 09 02:54:11 PM PDT 24
Finished May 09 03:16:32 PM PDT 24
Peak memory 202340 kb
Host smart-c3037887-2b6c-47be-80df-441147d8b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677073365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.677073365
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.4146789270
Short name T315
Test name
Test status
Simulation time 496226288349 ps
CPU time 1026.79 seconds
Started May 09 02:51:17 PM PDT 24
Finished May 09 03:08:30 PM PDT 24
Peak memory 202328 kb
Host smart-dfc25956-5b21-452d-ac77-b439a29cbcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146789270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.4146789270
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1299834871
Short name T324
Test name
Test status
Simulation time 180700375719 ps
CPU time 423.91 seconds
Started May 09 02:51:41 PM PDT 24
Finished May 09 02:58:46 PM PDT 24
Peak memory 202264 kb
Host smart-b9199da3-f9b8-4ee4-8f67-ebe3ec2b8c22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299834871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1299834871
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1857739534
Short name T38
Test name
Test status
Simulation time 504750554790 ps
CPU time 306.19 seconds
Started May 09 02:51:46 PM PDT 24
Finished May 09 02:56:54 PM PDT 24
Peak memory 202292 kb
Host smart-56fb7346-e491-4352-8d11-1fa76933aa4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857739534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1857739534
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.485162997
Short name T314
Test name
Test status
Simulation time 199451215756 ps
CPU time 499.44 seconds
Started May 09 02:50:52 PM PDT 24
Finished May 09 02:59:16 PM PDT 24
Peak memory 202332 kb
Host smart-7ff22539-22fe-433f-b2af-f5bcb94f8080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485162997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.485162997
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.761087365
Short name T159
Test name
Test status
Simulation time 518441082723 ps
CPU time 661 seconds
Started May 09 02:53:59 PM PDT 24
Finished May 09 03:05:02 PM PDT 24
Peak memory 202360 kb
Host smart-fa852a5e-3eb2-4a38-abef-3886983a6bac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761087365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.761087365
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.736160032
Short name T343
Test name
Test status
Simulation time 4357827517 ps
CPU time 4.13 seconds
Started May 09 02:31:39 PM PDT 24
Finished May 09 02:31:48 PM PDT 24
Peak memory 201484 kb
Host smart-1039195a-ee52-4bd2-8699-c2256b6931b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736160032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.736160032
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3082869970
Short name T214
Test name
Test status
Simulation time 88344685219 ps
CPU time 500.94 seconds
Started May 09 02:51:03 PM PDT 24
Finished May 09 02:59:30 PM PDT 24
Peak memory 202736 kb
Host smart-a6d8102b-0321-4135-830d-0ff6d29b55e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082869970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3082869970
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2924886241
Short name T676
Test name
Test status
Simulation time 727151832863 ps
CPU time 741.72 seconds
Started May 09 02:51:13 PM PDT 24
Finished May 09 03:03:42 PM PDT 24
Peak memory 202432 kb
Host smart-0606beeb-10a7-41f8-b19e-843fc446d265
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924886241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2924886241
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1161580391
Short name T550
Test name
Test status
Simulation time 87949025114 ps
CPU time 365.32 seconds
Started May 09 02:51:15 PM PDT 24
Finished May 09 02:57:27 PM PDT 24
Peak memory 202632 kb
Host smart-8be38fe1-e567-4562-a090-341faf01889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161580391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1161580391
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3500654707
Short name T44
Test name
Test status
Simulation time 72044725018 ps
CPU time 266.8 seconds
Started May 09 02:51:16 PM PDT 24
Finished May 09 02:55:49 PM PDT 24
Peak memory 202696 kb
Host smart-ffab05c9-4b5c-423c-a80e-6acf24462a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500654707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3500654707
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3981091232
Short name T344
Test name
Test status
Simulation time 84948555221 ps
CPU time 355.52 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:57:26 PM PDT 24
Peak memory 202700 kb
Host smart-07637738-cd28-45ba-8635-1714d7f50ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981091232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3981091232
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.797342920
Short name T259
Test name
Test status
Simulation time 243718907549 ps
CPU time 156.32 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:54:07 PM PDT 24
Peak memory 202420 kb
Host smart-3285798c-78ad-4835-985c-73e7b1c715b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797342920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
797342920
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4247654826
Short name T337
Test name
Test status
Simulation time 162488994632 ps
CPU time 93.96 seconds
Started May 09 02:50:50 PM PDT 24
Finished May 09 02:52:30 PM PDT 24
Peak memory 202352 kb
Host smart-3776847a-0e76-42c5-a667-8fbad5847ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247654826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4247654826
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2376693827
Short name T225
Test name
Test status
Simulation time 547358615853 ps
CPU time 361.83 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:57:32 PM PDT 24
Peak memory 202320 kb
Host smart-4b879c0f-d190-4034-b038-7afd89865ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376693827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2376693827
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.4255691278
Short name T53
Test name
Test status
Simulation time 22600053912 ps
CPU time 63.99 seconds
Started May 09 02:51:53 PM PDT 24
Finished May 09 02:52:59 PM PDT 24
Peak memory 211032 kb
Host smart-697b03dc-c1b2-4fd8-a799-2e5beafded64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255691278 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.4255691278
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.754333913
Short name T6
Test name
Test status
Simulation time 526465025191 ps
CPU time 1221.1 seconds
Started May 09 02:52:21 PM PDT 24
Finished May 09 03:12:45 PM PDT 24
Peak memory 202328 kb
Host smart-0eecf365-0592-4bb4-80f9-e67fc7a5c657
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754333913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.754333913
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.863313372
Short name T350
Test name
Test status
Simulation time 111179757454 ps
CPU time 383.87 seconds
Started May 09 02:52:22 PM PDT 24
Finished May 09 02:58:49 PM PDT 24
Peak memory 202632 kb
Host smart-2ccafd0c-d647-4393-ad44-aad05f400a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863313372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.863313372
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1448991235
Short name T311
Test name
Test status
Simulation time 541687672074 ps
CPU time 579.61 seconds
Started May 09 02:53:35 PM PDT 24
Finished May 09 03:03:16 PM PDT 24
Peak memory 202316 kb
Host smart-2ff86e72-dfc8-439d-a84a-ebf16fa58162
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448991235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1448991235
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1254152674
Short name T220
Test name
Test status
Simulation time 87153822861 ps
CPU time 337.95 seconds
Started May 09 02:53:48 PM PDT 24
Finished May 09 02:59:27 PM PDT 24
Peak memory 202708 kb
Host smart-8edc3374-4f62-440b-a04d-b9ea4d6283c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254152674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1254152674
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.603769779
Short name T227
Test name
Test status
Simulation time 341741022832 ps
CPU time 694.47 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 03:02:54 PM PDT 24
Peak memory 202320 kb
Host smart-fac6c7f2-1f8c-4108-99b3-de0808d311c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603769779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.603769779
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3508285133
Short name T834
Test name
Test status
Simulation time 1372402562 ps
CPU time 4.34 seconds
Started May 09 02:31:16 PM PDT 24
Finished May 09 02:31:27 PM PDT 24
Peak memory 201384 kb
Host smart-7819aceb-744a-497c-b40c-daf7d4ef58b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508285133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3508285133
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.325965915
Short name T871
Test name
Test status
Simulation time 54321692446 ps
CPU time 27.14 seconds
Started May 09 02:31:17 PM PDT 24
Finished May 09 02:31:51 PM PDT 24
Peak memory 201480 kb
Host smart-7ecbe0cc-75e1-4ccc-82ac-67aacb0f8d8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325965915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.325965915
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.531303061
Short name T126
Test name
Test status
Simulation time 1178479777 ps
CPU time 1.54 seconds
Started May 09 02:31:16 PM PDT 24
Finished May 09 02:31:24 PM PDT 24
Peak memory 201196 kb
Host smart-7667d220-cb44-430f-890c-c5787e0abd2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531303061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.531303061
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.615298834
Short name T869
Test name
Test status
Simulation time 611711521 ps
CPU time 1.15 seconds
Started May 09 02:31:15 PM PDT 24
Finished May 09 02:31:24 PM PDT 24
Peak memory 201280 kb
Host smart-aba17a80-4270-4718-b1e2-7b8596afe6fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615298834 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.615298834
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.711625209
Short name T132
Test name
Test status
Simulation time 324447488 ps
CPU time 1.06 seconds
Started May 09 02:31:14 PM PDT 24
Finished May 09 02:31:23 PM PDT 24
Peak memory 201248 kb
Host smart-854a16fc-fb2d-44ba-a400-5db0b3fc0056
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711625209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.711625209
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4097933125
Short name T890
Test name
Test status
Simulation time 568266414 ps
CPU time 0.82 seconds
Started May 09 02:31:14 PM PDT 24
Finished May 09 02:31:22 PM PDT 24
Peak memory 201228 kb
Host smart-b83ae5c2-2691-4a6d-ad24-85c92085e742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097933125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.4097933125
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2662219858
Short name T895
Test name
Test status
Simulation time 4708049425 ps
CPU time 4.04 seconds
Started May 09 02:31:16 PM PDT 24
Finished May 09 02:31:27 PM PDT 24
Peak memory 201440 kb
Host smart-56a3bdfb-d00f-48ff-a901-95dfa19fa629
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662219858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2662219858
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4174621340
Short name T900
Test name
Test status
Simulation time 494960614 ps
CPU time 1.72 seconds
Started May 09 02:31:23 PM PDT 24
Finished May 09 02:31:31 PM PDT 24
Peak memory 201480 kb
Host smart-03811657-e80b-4294-a15f-460dd0022cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174621340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.4174621340
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.869582098
Short name T884
Test name
Test status
Simulation time 4223089770 ps
CPU time 5.19 seconds
Started May 09 02:31:15 PM PDT 24
Finished May 09 02:31:27 PM PDT 24
Peak memory 201448 kb
Host smart-e4c68cec-7a7b-440b-8893-271b2b367c66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869582098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.869582098
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2725820771
Short name T857
Test name
Test status
Simulation time 985369221 ps
CPU time 2.01 seconds
Started May 09 02:31:15 PM PDT 24
Finished May 09 02:31:24 PM PDT 24
Peak memory 201404 kb
Host smart-ce6508f4-980f-4ba7-a177-0e62e1de77c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725820771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2725820771
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3808012565
Short name T137
Test name
Test status
Simulation time 52551379309 ps
CPU time 26.48 seconds
Started May 09 02:31:14 PM PDT 24
Finished May 09 02:31:47 PM PDT 24
Peak memory 201476 kb
Host smart-9a22af84-3a4c-4333-b54f-f6b8312dc883
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808012565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3808012565
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.853007291
Short name T827
Test name
Test status
Simulation time 833134584 ps
CPU time 2.76 seconds
Started May 09 02:31:15 PM PDT 24
Finished May 09 02:31:25 PM PDT 24
Peak memory 201200 kb
Host smart-49c220d7-c200-46ce-ae3c-e57fe2f9ee2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853007291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.853007291
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.342228479
Short name T829
Test name
Test status
Simulation time 645173214 ps
CPU time 1.74 seconds
Started May 09 02:31:18 PM PDT 24
Finished May 09 02:31:26 PM PDT 24
Peak memory 201312 kb
Host smart-4d372e75-bddc-4265-a7c7-b13be0248afe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342228479 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.342228479
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4167821900
Short name T136
Test name
Test status
Simulation time 372445232 ps
CPU time 1.15 seconds
Started May 09 02:31:20 PM PDT 24
Finished May 09 02:31:29 PM PDT 24
Peak memory 201244 kb
Host smart-ef34f092-4347-40a3-bdb5-381bbcb7b962
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167821900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.4167821900
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1377930076
Short name T881
Test name
Test status
Simulation time 418318753 ps
CPU time 1.6 seconds
Started May 09 02:31:15 PM PDT 24
Finished May 09 02:31:23 PM PDT 24
Peak memory 201104 kb
Host smart-a91cfb10-d8fe-4bb4-b39b-e192eac4677d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377930076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1377930076
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.197214927
Short name T904
Test name
Test status
Simulation time 2062284900 ps
CPU time 3.43 seconds
Started May 09 02:31:14 PM PDT 24
Finished May 09 02:31:25 PM PDT 24
Peak memory 201236 kb
Host smart-5d81fd4d-327b-4891-9ee0-053572e71892
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197214927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.197214927
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3430916565
Short name T75
Test name
Test status
Simulation time 312005628 ps
CPU time 1.82 seconds
Started May 09 02:31:16 PM PDT 24
Finished May 09 02:31:25 PM PDT 24
Peak memory 201488 kb
Host smart-b261a154-aaa2-4548-9637-51d5cc07c2c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430916565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3430916565
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2240180199
Short name T86
Test name
Test status
Simulation time 8109474213 ps
CPU time 22.09 seconds
Started May 09 02:31:16 PM PDT 24
Finished May 09 02:31:45 PM PDT 24
Peak memory 201376 kb
Host smart-0565c117-832a-4caa-babf-b3326ba4122c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240180199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2240180199
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3259469596
Short name T864
Test name
Test status
Simulation time 396215380 ps
CPU time 1.05 seconds
Started May 09 02:31:26 PM PDT 24
Finished May 09 02:31:33 PM PDT 24
Peak memory 201272 kb
Host smart-c2ec60d9-da18-458f-ae79-b14c9aa43fe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259469596 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3259469596
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1287081586
Short name T859
Test name
Test status
Simulation time 487926969 ps
CPU time 1.72 seconds
Started May 09 02:31:26 PM PDT 24
Finished May 09 02:31:33 PM PDT 24
Peak memory 201256 kb
Host smart-8066449f-f231-42d8-a708-df52b2d46d27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287081586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1287081586
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2287122302
Short name T916
Test name
Test status
Simulation time 289758129 ps
CPU time 1.41 seconds
Started May 09 02:31:26 PM PDT 24
Finished May 09 02:31:33 PM PDT 24
Peak memory 201256 kb
Host smart-9af67aa2-b051-45d9-b0eb-f1ef7ff1fd2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287122302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2287122302
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3621952807
Short name T913
Test name
Test status
Simulation time 4428539824 ps
CPU time 9.1 seconds
Started May 09 02:31:26 PM PDT 24
Finished May 09 02:31:40 PM PDT 24
Peak memory 201496 kb
Host smart-2942bef1-2f5d-4249-ad80-eb4983bd7a09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621952807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3621952807
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2678470812
Short name T882
Test name
Test status
Simulation time 437842527 ps
CPU time 1.59 seconds
Started May 09 02:31:25 PM PDT 24
Finished May 09 02:31:32 PM PDT 24
Peak memory 201496 kb
Host smart-e1400b30-ddcc-4a57-a7f6-e9bdc2df75dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678470812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2678470812
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.200151558
Short name T879
Test name
Test status
Simulation time 8533457015 ps
CPU time 7.36 seconds
Started May 09 02:31:26 PM PDT 24
Finished May 09 02:31:38 PM PDT 24
Peak memory 201612 kb
Host smart-e436dfd0-3cb9-4199-a918-6b8924929a63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200151558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.200151558
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1024038407
Short name T819
Test name
Test status
Simulation time 461864753 ps
CPU time 2.2 seconds
Started May 09 02:31:26 PM PDT 24
Finished May 09 02:31:34 PM PDT 24
Peak memory 201228 kb
Host smart-c0df0ec9-1468-4c8b-8d6f-76962540d4fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024038407 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1024038407
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1648091514
Short name T902
Test name
Test status
Simulation time 325071424 ps
CPU time 1.06 seconds
Started May 09 02:31:27 PM PDT 24
Finished May 09 02:31:34 PM PDT 24
Peak memory 200992 kb
Host smart-e99cf38d-4d66-4c84-bb17-65c5834091fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648091514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1648091514
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.202027576
Short name T817
Test name
Test status
Simulation time 454815060 ps
CPU time 1.21 seconds
Started May 09 02:31:25 PM PDT 24
Finished May 09 02:31:32 PM PDT 24
Peak memory 201264 kb
Host smart-fdae7552-cd7e-4ddc-92c0-a9df97297d9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202027576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.202027576
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.984348813
Short name T898
Test name
Test status
Simulation time 4474599042 ps
CPU time 2.32 seconds
Started May 09 02:31:30 PM PDT 24
Finished May 09 02:31:38 PM PDT 24
Peak memory 201700 kb
Host smart-b774ca4c-7fd4-491a-910d-1fc01f3650a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984348813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.984348813
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2028791781
Short name T76
Test name
Test status
Simulation time 396685260 ps
CPU time 2.55 seconds
Started May 09 02:31:26 PM PDT 24
Finished May 09 02:31:34 PM PDT 24
Peak memory 217700 kb
Host smart-de9d3c62-5457-45d8-a0d9-2cd52ff8d79c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028791781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2028791781
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2848780456
Short name T825
Test name
Test status
Simulation time 8769808546 ps
CPU time 6.9 seconds
Started May 09 02:31:30 PM PDT 24
Finished May 09 02:31:43 PM PDT 24
Peak memory 201512 kb
Host smart-d250a78c-6fe2-4715-beaf-0f98acee9a16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848780456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2848780456
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2155132034
Short name T84
Test name
Test status
Simulation time 550209592 ps
CPU time 1.11 seconds
Started May 09 02:31:25 PM PDT 24
Finished May 09 02:31:31 PM PDT 24
Peak memory 201276 kb
Host smart-1a8bc7ee-a0e1-4f77-80f4-02c33fdd2f7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155132034 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2155132034
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2019003541
Short name T127
Test name
Test status
Simulation time 595288416 ps
CPU time 0.99 seconds
Started May 09 02:31:27 PM PDT 24
Finished May 09 02:31:34 PM PDT 24
Peak memory 201200 kb
Host smart-2fd8d9a5-219a-4329-8b37-80154ca96893
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019003541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2019003541
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.402198816
Short name T830
Test name
Test status
Simulation time 309186382 ps
CPU time 0.8 seconds
Started May 09 02:31:27 PM PDT 24
Finished May 09 02:31:34 PM PDT 24
Peak memory 200920 kb
Host smart-2b62ff0b-094b-4a81-8fd2-0700279d3d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402198816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.402198816
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.84202981
Short name T836
Test name
Test status
Simulation time 4799685862 ps
CPU time 3.84 seconds
Started May 09 02:31:26 PM PDT 24
Finished May 09 02:31:35 PM PDT 24
Peak memory 201552 kb
Host smart-fa8770db-fa7d-435a-9375-34fe2466bf26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84202981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ct
rl_same_csr_outstanding.84202981
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1311978615
Short name T844
Test name
Test status
Simulation time 508782999 ps
CPU time 2.23 seconds
Started May 09 02:31:24 PM PDT 24
Finished May 09 02:31:32 PM PDT 24
Peak memory 201336 kb
Host smart-b5541f9a-baa8-4ea7-a43e-e4fe7b24a066
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311978615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1311978615
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2632464786
Short name T880
Test name
Test status
Simulation time 4772205881 ps
CPU time 6.35 seconds
Started May 09 02:31:29 PM PDT 24
Finished May 09 02:31:41 PM PDT 24
Peak memory 201440 kb
Host smart-365cf99b-0b5f-453a-83b5-671b936d85d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632464786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2632464786
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1450745886
Short name T121
Test name
Test status
Simulation time 1016497490 ps
CPU time 1.09 seconds
Started May 09 02:31:25 PM PDT 24
Finished May 09 02:31:32 PM PDT 24
Peak memory 201228 kb
Host smart-a67c65ce-1ed9-4f43-976b-52e1b45ed2c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450745886 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1450745886
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3029319130
Short name T138
Test name
Test status
Simulation time 512510845 ps
CPU time 1.41 seconds
Started May 09 02:31:27 PM PDT 24
Finished May 09 02:31:35 PM PDT 24
Peak memory 201268 kb
Host smart-5c2a8ba5-5c74-4440-9080-b29085869303
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029319130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3029319130
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3151159729
Short name T889
Test name
Test status
Simulation time 456433812 ps
CPU time 0.92 seconds
Started May 09 02:31:30 PM PDT 24
Finished May 09 02:31:36 PM PDT 24
Peak memory 201192 kb
Host smart-3b48da9f-b92e-4c1f-9913-6d58bd963569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151159729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3151159729
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1146982382
Short name T841
Test name
Test status
Simulation time 2024056489 ps
CPU time 8.34 seconds
Started May 09 02:31:29 PM PDT 24
Finished May 09 02:31:43 PM PDT 24
Peak memory 201456 kb
Host smart-9b317c69-40e4-4296-ae52-0d9a52ed5970
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146982382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1146982382
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2375212768
Short name T854
Test name
Test status
Simulation time 559614743 ps
CPU time 1.89 seconds
Started May 09 02:31:28 PM PDT 24
Finished May 09 02:31:36 PM PDT 24
Peak memory 201540 kb
Host smart-1e150e34-c1e6-46ec-8211-d5ad91de105c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375212768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2375212768
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1266270406
Short name T851
Test name
Test status
Simulation time 8482096057 ps
CPU time 6.83 seconds
Started May 09 02:31:27 PM PDT 24
Finished May 09 02:31:40 PM PDT 24
Peak memory 201572 kb
Host smart-15308ffc-bdc4-42cd-8741-93a69af15f06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266270406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1266270406
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3563317075
Short name T74
Test name
Test status
Simulation time 411694995 ps
CPU time 1.83 seconds
Started May 09 02:31:29 PM PDT 24
Finished May 09 02:31:37 PM PDT 24
Peak memory 201248 kb
Host smart-07a4e74e-9840-4caf-ada7-b677696c5cfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563317075 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3563317075
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1078576496
Short name T128
Test name
Test status
Simulation time 521294793 ps
CPU time 1 seconds
Started May 09 02:31:28 PM PDT 24
Finished May 09 02:31:35 PM PDT 24
Peak memory 201456 kb
Host smart-6c018f53-0f73-43de-a38a-3f49e0c8f4a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078576496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1078576496
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3576220100
Short name T838
Test name
Test status
Simulation time 526999025 ps
CPU time 1.05 seconds
Started May 09 02:31:29 PM PDT 24
Finished May 09 02:31:36 PM PDT 24
Peak memory 201200 kb
Host smart-9f013aaf-8dfc-47c8-901b-044f67885015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576220100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3576220100
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3533233484
Short name T863
Test name
Test status
Simulation time 4296940711 ps
CPU time 9.54 seconds
Started May 09 02:31:27 PM PDT 24
Finished May 09 02:31:43 PM PDT 24
Peak memory 201560 kb
Host smart-d6f5e238-87fe-4620-9c9b-844936511543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533233484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3533233484
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3196394460
Short name T77
Test name
Test status
Simulation time 406898777 ps
CPU time 2.2 seconds
Started May 09 02:31:25 PM PDT 24
Finished May 09 02:31:33 PM PDT 24
Peak memory 201464 kb
Host smart-c2101101-bf2d-487a-946c-099258a574b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196394460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3196394460
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4105749333
Short name T820
Test name
Test status
Simulation time 8427950280 ps
CPU time 12.49 seconds
Started May 09 02:31:26 PM PDT 24
Finished May 09 02:31:44 PM PDT 24
Peak memory 201492 kb
Host smart-3287b6a1-a6f5-482f-b1cb-d15d1ba52f87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105749333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.4105749333
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3071885514
Short name T814
Test name
Test status
Simulation time 412991921 ps
CPU time 1.23 seconds
Started May 09 02:31:29 PM PDT 24
Finished May 09 02:31:36 PM PDT 24
Peak memory 201236 kb
Host smart-bfdf725c-6e9a-4c82-baa4-5704cdf1c150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071885514 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3071885514
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3895896570
Short name T892
Test name
Test status
Simulation time 438139737 ps
CPU time 0.97 seconds
Started May 09 02:31:30 PM PDT 24
Finished May 09 02:31:37 PM PDT 24
Peak memory 201244 kb
Host smart-f0d51d17-fc5a-4981-8c9f-c4988f2b5158
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895896570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3895896570
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.533219814
Short name T803
Test name
Test status
Simulation time 473755087 ps
CPU time 0.9 seconds
Started May 09 02:31:30 PM PDT 24
Finished May 09 02:31:37 PM PDT 24
Peak memory 201240 kb
Host smart-3da80602-7624-4aeb-8920-0b328c33e67d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533219814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.533219814
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2805081507
Short name T856
Test name
Test status
Simulation time 3892310609 ps
CPU time 13.94 seconds
Started May 09 02:31:29 PM PDT 24
Finished May 09 02:31:48 PM PDT 24
Peak memory 201484 kb
Host smart-20ff8486-e83d-459b-9ce2-bf7a5d5244e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805081507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2805081507
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3370661360
Short name T866
Test name
Test status
Simulation time 583836004 ps
CPU time 2.14 seconds
Started May 09 02:31:30 PM PDT 24
Finished May 09 02:31:38 PM PDT 24
Peak memory 201500 kb
Host smart-076ca60d-6eb0-4aba-bb1a-5998cb0a74bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370661360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3370661360
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2127476926
Short name T67
Test name
Test status
Simulation time 8313194865 ps
CPU time 11.99 seconds
Started May 09 02:31:26 PM PDT 24
Finished May 09 02:31:44 PM PDT 24
Peak memory 201472 kb
Host smart-02b0010b-9aa0-48c5-836d-c669ded77c65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127476926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2127476926
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.437613092
Short name T808
Test name
Test status
Simulation time 484519891 ps
CPU time 1.28 seconds
Started May 09 02:31:35 PM PDT 24
Finished May 09 02:31:42 PM PDT 24
Peak memory 201296 kb
Host smart-a75e3ef8-f3e8-4db8-b7e8-41aec44a20e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437613092 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.437613092
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3072740497
Short name T911
Test name
Test status
Simulation time 442721328 ps
CPU time 1.19 seconds
Started May 09 02:31:27 PM PDT 24
Finished May 09 02:31:34 PM PDT 24
Peak memory 201264 kb
Host smart-b7d6528c-3fa4-4bc6-9cd7-0ef589440f60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072740497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3072740497
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.881243848
Short name T874
Test name
Test status
Simulation time 291896758 ps
CPU time 1.31 seconds
Started May 09 02:31:28 PM PDT 24
Finished May 09 02:31:35 PM PDT 24
Peak memory 201220 kb
Host smart-bc6cb0ef-7fff-4c46-b87e-06de9ec88ef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881243848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.881243848
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.79023748
Short name T872
Test name
Test status
Simulation time 4468633459 ps
CPU time 11.54 seconds
Started May 09 02:31:36 PM PDT 24
Finished May 09 02:31:52 PM PDT 24
Peak memory 201544 kb
Host smart-5b38f30e-3baf-4188-8098-626032010aec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79023748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ct
rl_same_csr_outstanding.79023748
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2954996450
Short name T835
Test name
Test status
Simulation time 784141542 ps
CPU time 1.92 seconds
Started May 09 02:31:27 PM PDT 24
Finished May 09 02:31:34 PM PDT 24
Peak memory 201532 kb
Host smart-375aae91-4ea8-419d-a543-f1af44aaf68f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954996450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2954996450
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1738191921
Short name T66
Test name
Test status
Simulation time 8042517548 ps
CPU time 21.23 seconds
Started May 09 02:31:27 PM PDT 24
Finished May 09 02:31:54 PM PDT 24
Peak memory 201412 kb
Host smart-93bee541-3b46-48e2-8946-cd298cac1cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738191921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1738191921
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2465259134
Short name T861
Test name
Test status
Simulation time 511976215 ps
CPU time 1.24 seconds
Started May 09 02:31:41 PM PDT 24
Finished May 09 02:31:48 PM PDT 24
Peak memory 201304 kb
Host smart-c4cbbe72-a667-48ff-a505-113f0341c429
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465259134 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2465259134
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1753548210
Short name T141
Test name
Test status
Simulation time 437578034 ps
CPU time 1.2 seconds
Started May 09 02:31:35 PM PDT 24
Finished May 09 02:31:41 PM PDT 24
Peak memory 201280 kb
Host smart-1446bc9a-889c-4429-8094-fdee5a14449d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753548210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1753548210
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3907144643
Short name T826
Test name
Test status
Simulation time 345246778 ps
CPU time 1.08 seconds
Started May 09 02:31:38 PM PDT 24
Finished May 09 02:31:45 PM PDT 24
Peak memory 201176 kb
Host smart-49c56e40-ff60-4afc-b323-607f670622e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907144643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3907144643
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.286414145
Short name T888
Test name
Test status
Simulation time 2243279325 ps
CPU time 2.75 seconds
Started May 09 02:31:34 PM PDT 24
Finished May 09 02:31:42 PM PDT 24
Peak memory 201316 kb
Host smart-0721da5d-ad96-447a-9e32-83e95c9ebf00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286414145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.286414145
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1940049904
Short name T862
Test name
Test status
Simulation time 590272317 ps
CPU time 2.11 seconds
Started May 09 02:31:35 PM PDT 24
Finished May 09 02:31:42 PM PDT 24
Peak memory 201464 kb
Host smart-03670ca8-75bb-4950-a4d8-1bdde2dccea5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940049904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1940049904
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3607591796
Short name T98
Test name
Test status
Simulation time 4211417008 ps
CPU time 11.05 seconds
Started May 09 02:31:36 PM PDT 24
Finished May 09 02:31:52 PM PDT 24
Peak memory 201508 kb
Host smart-765d7f59-b5cc-4c02-9720-eb67f09e7122
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607591796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3607591796
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2276794300
Short name T875
Test name
Test status
Simulation time 493944766 ps
CPU time 1.25 seconds
Started May 09 02:31:35 PM PDT 24
Finished May 09 02:31:41 PM PDT 24
Peak memory 201304 kb
Host smart-39df658a-4c59-4f0b-bcef-0a412739c2b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276794300 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2276794300
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1215885762
Short name T143
Test name
Test status
Simulation time 406676248 ps
CPU time 1.31 seconds
Started May 09 02:31:38 PM PDT 24
Finished May 09 02:31:45 PM PDT 24
Peak memory 201248 kb
Host smart-c515ba56-34ca-4ecc-8cb7-985343164814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215885762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1215885762
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.563508872
Short name T832
Test name
Test status
Simulation time 411992206 ps
CPU time 0.88 seconds
Started May 09 02:31:33 PM PDT 24
Finished May 09 02:31:40 PM PDT 24
Peak memory 201260 kb
Host smart-93103ea7-26f7-4814-b266-0bde46cf0e5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563508872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.563508872
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.748781829
Short name T61
Test name
Test status
Simulation time 1858222503 ps
CPU time 1.95 seconds
Started May 09 02:31:41 PM PDT 24
Finished May 09 02:31:49 PM PDT 24
Peak memory 201252 kb
Host smart-4f84b16d-a2af-4040-b3df-007e224efa9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748781829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.748781829
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.908788929
Short name T824
Test name
Test status
Simulation time 517935244 ps
CPU time 3.54 seconds
Started May 09 02:31:41 PM PDT 24
Finished May 09 02:31:51 PM PDT 24
Peak memory 209688 kb
Host smart-636364f6-c7b7-434f-87e0-ee83939c6ebf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908788929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.908788929
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1656110729
Short name T119
Test name
Test status
Simulation time 393340477 ps
CPU time 1.85 seconds
Started May 09 02:31:36 PM PDT 24
Finished May 09 02:31:42 PM PDT 24
Peak memory 201264 kb
Host smart-a3404a40-62e0-4ae3-bb1d-c41810924913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656110729 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1656110729
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3687670107
Short name T917
Test name
Test status
Simulation time 322326548 ps
CPU time 1.49 seconds
Started May 09 02:31:38 PM PDT 24
Finished May 09 02:31:44 PM PDT 24
Peak memory 201220 kb
Host smart-9b497e04-82f3-4e67-94bd-765288a067a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687670107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3687670107
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1447066112
Short name T821
Test name
Test status
Simulation time 427052287 ps
CPU time 1.68 seconds
Started May 09 02:31:39 PM PDT 24
Finished May 09 02:31:46 PM PDT 24
Peak memory 201312 kb
Host smart-f9d3a5de-ae24-41cc-8d25-97d7297db1cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447066112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1447066112
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1617858302
Short name T915
Test name
Test status
Simulation time 2079654014 ps
CPU time 8.18 seconds
Started May 09 02:31:41 PM PDT 24
Finished May 09 02:31:55 PM PDT 24
Peak memory 201252 kb
Host smart-700da87e-fda8-4d9b-9e3b-775099765b6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617858302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1617858302
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2025933439
Short name T82
Test name
Test status
Simulation time 1244707986 ps
CPU time 2.4 seconds
Started May 09 02:31:45 PM PDT 24
Finished May 09 02:31:53 PM PDT 24
Peak memory 201488 kb
Host smart-9fbe6377-7b82-4899-a5ae-45756b149997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025933439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2025933439
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.377809021
Short name T828
Test name
Test status
Simulation time 9996073412 ps
CPU time 4.98 seconds
Started May 09 02:31:39 PM PDT 24
Finished May 09 02:31:49 PM PDT 24
Peak memory 201584 kb
Host smart-25379cf5-4903-41fc-8708-64141994695e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377809021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.377809021
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2217189803
Short name T125
Test name
Test status
Simulation time 1245152355 ps
CPU time 3.89 seconds
Started May 09 02:31:14 PM PDT 24
Finished May 09 02:31:25 PM PDT 24
Peak memory 201468 kb
Host smart-54506e99-47fb-4285-8369-64741790326e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217189803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2217189803
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1206843107
Short name T134
Test name
Test status
Simulation time 26537589190 ps
CPU time 28.28 seconds
Started May 09 02:31:16 PM PDT 24
Finished May 09 02:31:51 PM PDT 24
Peak memory 201472 kb
Host smart-5f8ee6f3-0a9f-438c-b725-167ba2efed58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206843107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1206843107
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.993369676
Short name T130
Test name
Test status
Simulation time 1193734916 ps
CPU time 1.76 seconds
Started May 09 02:31:13 PM PDT 24
Finished May 09 02:31:21 PM PDT 24
Peak memory 201252 kb
Host smart-ecfd7e86-be8b-4272-ba23-e9a06b7d73c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993369676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.993369676
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3464627909
Short name T867
Test name
Test status
Simulation time 448069687 ps
CPU time 1.91 seconds
Started May 09 02:31:23 PM PDT 24
Finished May 09 02:31:31 PM PDT 24
Peak memory 201244 kb
Host smart-829b73e1-da61-49da-939b-88b9b9b3c82c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464627909 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3464627909
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2279072512
Short name T833
Test name
Test status
Simulation time 296947631 ps
CPU time 1.46 seconds
Started May 09 02:31:15 PM PDT 24
Finished May 09 02:31:23 PM PDT 24
Peak memory 201272 kb
Host smart-fd1f0c34-c69e-4ce4-ad02-02c38b249425
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279072512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2279072512
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1540947742
Short name T806
Test name
Test status
Simulation time 387541324 ps
CPU time 1.52 seconds
Started May 09 02:31:15 PM PDT 24
Finished May 09 02:31:23 PM PDT 24
Peak memory 201256 kb
Host smart-58ba1ebe-718b-481b-8b38-311b74ab5452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540947742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1540947742
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.504007445
Short name T837
Test name
Test status
Simulation time 3932563576 ps
CPU time 3.27 seconds
Started May 09 02:31:17 PM PDT 24
Finished May 09 02:31:27 PM PDT 24
Peak memory 201568 kb
Host smart-2d44dfda-4821-407c-bd63-81e85bbc8649
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504007445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.504007445
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1172599823
Short name T855
Test name
Test status
Simulation time 616163493 ps
CPU time 2.29 seconds
Started May 09 02:31:15 PM PDT 24
Finished May 09 02:31:25 PM PDT 24
Peak memory 201492 kb
Host smart-2c37abe9-a4ec-47f5-990f-4ed1234968c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172599823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1172599823
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1692098415
Short name T860
Test name
Test status
Simulation time 434445774 ps
CPU time 0.85 seconds
Started May 09 02:31:39 PM PDT 24
Finished May 09 02:31:45 PM PDT 24
Peak memory 201172 kb
Host smart-b6c908e0-9303-4989-88c2-9a7fc68a3cf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692098415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1692098415
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1586435304
Short name T891
Test name
Test status
Simulation time 456373964 ps
CPU time 1.14 seconds
Started May 09 02:31:38 PM PDT 24
Finished May 09 02:31:45 PM PDT 24
Peak memory 201308 kb
Host smart-baf20675-c83e-4ba1-a6e3-80bf7c95f3b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586435304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1586435304
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1544142904
Short name T818
Test name
Test status
Simulation time 465254121 ps
CPU time 1.19 seconds
Started May 09 02:31:36 PM PDT 24
Finished May 09 02:31:42 PM PDT 24
Peak memory 201244 kb
Host smart-f08a8c7a-ae78-4859-be51-46d9732cebbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544142904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1544142904
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3399330314
Short name T823
Test name
Test status
Simulation time 541692170 ps
CPU time 0.75 seconds
Started May 09 02:31:35 PM PDT 24
Finished May 09 02:31:41 PM PDT 24
Peak memory 201264 kb
Host smart-2a6fe29b-4fc5-4749-a971-9390ca681db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399330314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3399330314
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2470214908
Short name T801
Test name
Test status
Simulation time 383525614 ps
CPU time 0.84 seconds
Started May 09 02:31:34 PM PDT 24
Finished May 09 02:31:40 PM PDT 24
Peak memory 201248 kb
Host smart-29ae59e3-e5d2-446d-a1bf-c4cf31bffeb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470214908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2470214908
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1527066880
Short name T905
Test name
Test status
Simulation time 403149339 ps
CPU time 1.44 seconds
Started May 09 02:31:45 PM PDT 24
Finished May 09 02:31:52 PM PDT 24
Peak memory 201240 kb
Host smart-314579ad-817d-40c5-8bb1-d838893a919b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527066880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1527066880
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.59936940
Short name T907
Test name
Test status
Simulation time 515750820 ps
CPU time 1.54 seconds
Started May 09 02:31:36 PM PDT 24
Finished May 09 02:31:43 PM PDT 24
Peak memory 201200 kb
Host smart-eef4e47b-e4bd-4709-8ea6-c289c24e1a60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59936940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.59936940
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1062809541
Short name T852
Test name
Test status
Simulation time 452073236 ps
CPU time 0.89 seconds
Started May 09 02:31:36 PM PDT 24
Finished May 09 02:31:42 PM PDT 24
Peak memory 201272 kb
Host smart-4bb40367-31a6-4100-95d5-52ccf4989230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062809541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1062809541
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3456135238
Short name T831
Test name
Test status
Simulation time 462391999 ps
CPU time 1.15 seconds
Started May 09 02:31:39 PM PDT 24
Finished May 09 02:31:46 PM PDT 24
Peak memory 201200 kb
Host smart-ac190952-d1ce-4d97-8051-5e9cb7dea6f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456135238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3456135238
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.920897611
Short name T894
Test name
Test status
Simulation time 505953513 ps
CPU time 1.34 seconds
Started May 09 02:31:38 PM PDT 24
Finished May 09 02:31:44 PM PDT 24
Peak memory 201232 kb
Host smart-600e0c12-72f5-4b95-8386-f5b3549afdca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920897611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.920897611
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1794338840
Short name T133
Test name
Test status
Simulation time 704049469 ps
CPU time 3.46 seconds
Started May 09 02:31:17 PM PDT 24
Finished May 09 02:31:27 PM PDT 24
Peak memory 201480 kb
Host smart-7aefc0bd-9f3a-492b-97ab-c2d4576a1314
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794338840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1794338840
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3757533846
Short name T842
Test name
Test status
Simulation time 854840750 ps
CPU time 1.7 seconds
Started May 09 02:31:13 PM PDT 24
Finished May 09 02:31:22 PM PDT 24
Peak memory 201232 kb
Host smart-1774ac44-929b-48d0-a6a6-39c18c09298e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757533846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3757533846
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3526210137
Short name T840
Test name
Test status
Simulation time 460425089 ps
CPU time 1.97 seconds
Started May 09 02:31:13 PM PDT 24
Finished May 09 02:31:22 PM PDT 24
Peak memory 201272 kb
Host smart-19023efb-ef20-441c-b2a8-73985cf9b5c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526210137 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3526210137
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3580720108
Short name T848
Test name
Test status
Simulation time 469865532 ps
CPU time 1.89 seconds
Started May 09 02:31:16 PM PDT 24
Finished May 09 02:31:24 PM PDT 24
Peak memory 201292 kb
Host smart-0d3ee724-ffc1-4ae6-9214-9bb322036e70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580720108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3580720108
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3324481266
Short name T815
Test name
Test status
Simulation time 503886902 ps
CPU time 0.94 seconds
Started May 09 02:31:17 PM PDT 24
Finished May 09 02:31:25 PM PDT 24
Peak memory 201224 kb
Host smart-3376bfbe-e147-42c9-9668-a09f80f29afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324481266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3324481266
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3416121109
Short name T883
Test name
Test status
Simulation time 2654243638 ps
CPU time 8.77 seconds
Started May 09 02:31:15 PM PDT 24
Finished May 09 02:31:31 PM PDT 24
Peak memory 201256 kb
Host smart-0105a84c-0364-4d46-9cf1-0ebe9384179e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416121109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3416121109
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1228165908
Short name T858
Test name
Test status
Simulation time 540390855 ps
CPU time 3.17 seconds
Started May 09 02:31:17 PM PDT 24
Finished May 09 02:31:27 PM PDT 24
Peak memory 201540 kb
Host smart-36fc337b-6bce-4fda-bc7f-d539f610d343
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228165908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1228165908
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.557257930
Short name T70
Test name
Test status
Simulation time 9002257345 ps
CPU time 25.28 seconds
Started May 09 02:31:14 PM PDT 24
Finished May 09 02:31:46 PM PDT 24
Peak memory 201576 kb
Host smart-bafb632e-b006-4265-8f55-c7313fd651aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557257930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.557257930
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1156818407
Short name T843
Test name
Test status
Simulation time 514244248 ps
CPU time 0.96 seconds
Started May 09 02:31:36 PM PDT 24
Finished May 09 02:31:41 PM PDT 24
Peak memory 201284 kb
Host smart-0b21a17e-8bad-4a3e-bac2-98ac3f91e479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156818407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1156818407
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.4167201008
Short name T886
Test name
Test status
Simulation time 373038641 ps
CPU time 0.87 seconds
Started May 09 02:31:35 PM PDT 24
Finished May 09 02:31:41 PM PDT 24
Peak memory 201260 kb
Host smart-96a86a74-2494-4619-b35c-71e59e1fe53f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167201008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.4167201008
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2810023424
Short name T868
Test name
Test status
Simulation time 443997511 ps
CPU time 1.65 seconds
Started May 09 02:31:38 PM PDT 24
Finished May 09 02:31:44 PM PDT 24
Peak memory 201444 kb
Host smart-e5696c6a-af62-4992-b5a6-401d8460dbea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810023424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2810023424
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1878769375
Short name T846
Test name
Test status
Simulation time 306846619 ps
CPU time 1.32 seconds
Started May 09 02:31:36 PM PDT 24
Finished May 09 02:31:42 PM PDT 24
Peak memory 201216 kb
Host smart-857a3ae9-88ae-481f-970c-f4f00457137b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878769375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1878769375
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1185760594
Short name T811
Test name
Test status
Simulation time 404802274 ps
CPU time 0.86 seconds
Started May 09 02:31:34 PM PDT 24
Finished May 09 02:31:40 PM PDT 24
Peak memory 201220 kb
Host smart-5db6a1c8-f5c0-495f-bab4-0118ebff71b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185760594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1185760594
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1462795391
Short name T901
Test name
Test status
Simulation time 385351804 ps
CPU time 1.4 seconds
Started May 09 02:31:35 PM PDT 24
Finished May 09 02:31:41 PM PDT 24
Peak memory 201224 kb
Host smart-6fce26e5-f795-4d98-822b-93a7d817f830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462795391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1462795391
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3060533495
Short name T816
Test name
Test status
Simulation time 507082703 ps
CPU time 1.09 seconds
Started May 09 02:31:35 PM PDT 24
Finished May 09 02:31:41 PM PDT 24
Peak memory 201240 kb
Host smart-8ea6fed9-811b-4baf-ab56-1a09a25e3555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060533495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3060533495
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1185912398
Short name T878
Test name
Test status
Simulation time 542195893 ps
CPU time 0.9 seconds
Started May 09 02:31:36 PM PDT 24
Finished May 09 02:31:42 PM PDT 24
Peak memory 201264 kb
Host smart-558566de-3d83-4b44-bb01-c18160c45b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185912398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1185912398
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1808547616
Short name T809
Test name
Test status
Simulation time 336486211 ps
CPU time 1.33 seconds
Started May 09 02:31:40 PM PDT 24
Finished May 09 02:31:47 PM PDT 24
Peak memory 201200 kb
Host smart-1f55b5ac-29cf-4ce4-9355-a48a5cd703f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808547616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1808547616
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2375938310
Short name T805
Test name
Test status
Simulation time 472835004 ps
CPU time 0.85 seconds
Started May 09 02:31:36 PM PDT 24
Finished May 09 02:31:42 PM PDT 24
Peak memory 201284 kb
Host smart-acf3af46-5d96-4d12-938a-355eeea5c688
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375938310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2375938310
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2489624585
Short name T142
Test name
Test status
Simulation time 1266349120 ps
CPU time 3.17 seconds
Started May 09 02:31:16 PM PDT 24
Finished May 09 02:31:26 PM PDT 24
Peak memory 201488 kb
Host smart-387e7cef-7f8d-4155-9add-adfc48c105f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489624585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2489624585
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1287351022
Short name T129
Test name
Test status
Simulation time 4227757572 ps
CPU time 4.31 seconds
Started May 09 02:31:18 PM PDT 24
Finished May 09 02:31:29 PM PDT 24
Peak memory 201572 kb
Host smart-0e84c443-a3ab-490d-9318-669d388dd0da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287351022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1287351022
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3711797715
Short name T897
Test name
Test status
Simulation time 975804285 ps
CPU time 3.1 seconds
Started May 09 02:31:18 PM PDT 24
Finished May 09 02:31:28 PM PDT 24
Peak memory 201188 kb
Host smart-c9ae58e8-9d2d-4c19-bc03-808f4b800dac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711797715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3711797715
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3412675727
Short name T120
Test name
Test status
Simulation time 644200888 ps
CPU time 1.21 seconds
Started May 09 02:31:23 PM PDT 24
Finished May 09 02:31:31 PM PDT 24
Peak memory 201244 kb
Host smart-b49cd5aa-5de3-4bfc-ba37-1e7f07a23acd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412675727 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3412675727
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3129994441
Short name T140
Test name
Test status
Simulation time 676812635 ps
CPU time 0.87 seconds
Started May 09 02:31:18 PM PDT 24
Finished May 09 02:31:26 PM PDT 24
Peak memory 201268 kb
Host smart-2fd9a8c1-b3fe-4f9d-8a94-a66a5e9db2da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129994441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3129994441
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1491148182
Short name T893
Test name
Test status
Simulation time 400490060 ps
CPU time 1.49 seconds
Started May 09 02:31:14 PM PDT 24
Finished May 09 02:31:22 PM PDT 24
Peak memory 201252 kb
Host smart-b642d6a6-7c4d-452b-bf41-8e2084648139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491148182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1491148182
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.46454951
Short name T59
Test name
Test status
Simulation time 4522798688 ps
CPU time 4.28 seconds
Started May 09 02:31:23 PM PDT 24
Finished May 09 02:31:34 PM PDT 24
Peak memory 201412 kb
Host smart-bd224af0-9897-4cd4-bdc4-9bef9ed78441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46454951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctr
l_same_csr_outstanding.46454951
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3354958954
Short name T865
Test name
Test status
Simulation time 463014694 ps
CPU time 3.5 seconds
Started May 09 02:31:12 PM PDT 24
Finished May 09 02:31:22 PM PDT 24
Peak memory 201628 kb
Host smart-5a5b0c35-d7c5-4c0d-b245-17f0d8bd8787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354958954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3354958954
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3381603024
Short name T885
Test name
Test status
Simulation time 4065648533 ps
CPU time 3.79 seconds
Started May 09 02:31:13 PM PDT 24
Finished May 09 02:31:24 PM PDT 24
Peak memory 201496 kb
Host smart-541700d5-8341-4cc2-b6ef-dd8795930c62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381603024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3381603024
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1079683132
Short name T850
Test name
Test status
Simulation time 409527811 ps
CPU time 0.85 seconds
Started May 09 02:31:40 PM PDT 24
Finished May 09 02:31:46 PM PDT 24
Peak memory 201244 kb
Host smart-2c3cfb32-413c-4921-b6ce-ae845408453f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079683132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1079683132
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3360208675
Short name T909
Test name
Test status
Simulation time 525353069 ps
CPU time 0.89 seconds
Started May 09 02:31:44 PM PDT 24
Finished May 09 02:31:51 PM PDT 24
Peak memory 201240 kb
Host smart-61eed542-31fa-44a3-b4cf-7e65bbb680ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360208675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3360208675
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2113852848
Short name T810
Test name
Test status
Simulation time 340934580 ps
CPU time 1.5 seconds
Started May 09 02:31:41 PM PDT 24
Finished May 09 02:31:49 PM PDT 24
Peak memory 201252 kb
Host smart-5653acc1-e1f7-4dfc-8da4-44c5fad8dd2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113852848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2113852848
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3238915925
Short name T887
Test name
Test status
Simulation time 481804783 ps
CPU time 1.72 seconds
Started May 09 02:31:39 PM PDT 24
Finished May 09 02:31:46 PM PDT 24
Peak memory 201240 kb
Host smart-5f78c7df-97fc-44f5-b433-e93ae290c84e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238915925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3238915925
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3262766857
Short name T849
Test name
Test status
Simulation time 409013809 ps
CPU time 0.85 seconds
Started May 09 02:31:40 PM PDT 24
Finished May 09 02:31:46 PM PDT 24
Peak memory 201200 kb
Host smart-6cd01760-00a9-4ccf-8fc4-3e1140be09eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262766857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3262766857
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.240084099
Short name T807
Test name
Test status
Simulation time 423459295 ps
CPU time 1.68 seconds
Started May 09 02:31:38 PM PDT 24
Finished May 09 02:31:45 PM PDT 24
Peak memory 201276 kb
Host smart-d8de81b6-d459-4cbb-a381-9651cb573d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240084099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.240084099
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2581209166
Short name T802
Test name
Test status
Simulation time 478742604 ps
CPU time 1.9 seconds
Started May 09 02:31:40 PM PDT 24
Finished May 09 02:31:48 PM PDT 24
Peak memory 201244 kb
Host smart-50788eaa-9550-4d62-a039-200c75eefa65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581209166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2581209166
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1356047958
Short name T914
Test name
Test status
Simulation time 533851115 ps
CPU time 0.98 seconds
Started May 09 02:31:37 PM PDT 24
Finished May 09 02:31:43 PM PDT 24
Peak memory 201272 kb
Host smart-6bca2087-aadf-4bf1-8528-d30eea84d5b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356047958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1356047958
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3462809102
Short name T853
Test name
Test status
Simulation time 329686937 ps
CPU time 1.37 seconds
Started May 09 02:31:34 PM PDT 24
Finished May 09 02:31:41 PM PDT 24
Peak memory 201220 kb
Host smart-8f9d55c1-6464-4d4d-9c8a-1652d8dd2ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462809102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3462809102
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3404321446
Short name T910
Test name
Test status
Simulation time 479057519 ps
CPU time 0.9 seconds
Started May 09 02:31:39 PM PDT 24
Finished May 09 02:31:45 PM PDT 24
Peak memory 201216 kb
Host smart-5cdf1e6a-de3e-4ffb-9be6-746bf3dbc91f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404321446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3404321446
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2179634821
Short name T899
Test name
Test status
Simulation time 502255992 ps
CPU time 1.32 seconds
Started May 09 02:31:22 PM PDT 24
Finished May 09 02:31:30 PM PDT 24
Peak memory 201244 kb
Host smart-db2be672-a0b5-488d-b0a9-115f6cc49eb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179634821 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2179634821
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.841454728
Short name T903
Test name
Test status
Simulation time 548923499 ps
CPU time 2.1 seconds
Started May 09 02:31:23 PM PDT 24
Finished May 09 02:31:32 PM PDT 24
Peak memory 201200 kb
Host smart-e46d46e8-fcc6-4eff-ba5a-68aa0e4b4ca6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841454728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.841454728
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3277679167
Short name T896
Test name
Test status
Simulation time 496296968 ps
CPU time 1.15 seconds
Started May 09 02:31:17 PM PDT 24
Finished May 09 02:31:25 PM PDT 24
Peak memory 201280 kb
Host smart-f5321eb4-ba4f-4e14-873e-ad3a31a57a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277679167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3277679167
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2039473581
Short name T876
Test name
Test status
Simulation time 3339963603 ps
CPU time 4.96 seconds
Started May 09 02:31:17 PM PDT 24
Finished May 09 02:31:28 PM PDT 24
Peak memory 201512 kb
Host smart-cbc0f252-3e45-49b1-9de3-b44ffa46be53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039473581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2039473581
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.230594297
Short name T813
Test name
Test status
Simulation time 520542777 ps
CPU time 1.93 seconds
Started May 09 02:31:18 PM PDT 24
Finished May 09 02:31:27 PM PDT 24
Peak memory 201440 kb
Host smart-bf84d120-c28c-4e98-89e7-a21f0e3c081a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230594297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.230594297
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.148602771
Short name T65
Test name
Test status
Simulation time 8867498115 ps
CPU time 5.83 seconds
Started May 09 02:31:18 PM PDT 24
Finished May 09 02:31:30 PM PDT 24
Peak memory 201556 kb
Host smart-56744658-da01-485a-a219-39bfa90e1085
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148602771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.148602771
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3383683397
Short name T877
Test name
Test status
Simulation time 599948867 ps
CPU time 1.64 seconds
Started May 09 02:31:23 PM PDT 24
Finished May 09 02:31:31 PM PDT 24
Peak memory 201272 kb
Host smart-e36b0421-91a3-4770-84e6-49c62375b917
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383683397 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3383683397
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3510951387
Short name T123
Test name
Test status
Simulation time 534828693 ps
CPU time 1.29 seconds
Started May 09 02:31:27 PM PDT 24
Finished May 09 02:31:34 PM PDT 24
Peak memory 201212 kb
Host smart-476ad040-7ab1-48d9-8c88-6784735ca767
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510951387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3510951387
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2231773862
Short name T804
Test name
Test status
Simulation time 342726091 ps
CPU time 1.07 seconds
Started May 09 02:31:23 PM PDT 24
Finished May 09 02:31:30 PM PDT 24
Peak memory 201212 kb
Host smart-1fbba75f-b506-4f33-87ee-3ff1285546ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231773862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2231773862
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3042789292
Short name T912
Test name
Test status
Simulation time 3940864243 ps
CPU time 3.41 seconds
Started May 09 02:31:22 PM PDT 24
Finished May 09 02:31:32 PM PDT 24
Peak memory 201468 kb
Host smart-fc73eb39-fa14-442f-8d2b-fca72830e49e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042789292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3042789292
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3994450314
Short name T83
Test name
Test status
Simulation time 4639848210 ps
CPU time 2.43 seconds
Started May 09 02:31:20 PM PDT 24
Finished May 09 02:31:29 PM PDT 24
Peak memory 201508 kb
Host smart-ee79d603-d5f3-48bb-808d-0a4ca5575633
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994450314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3994450314
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.233832053
Short name T99
Test name
Test status
Simulation time 476818578 ps
CPU time 2.07 seconds
Started May 09 02:31:20 PM PDT 24
Finished May 09 02:31:29 PM PDT 24
Peak memory 201296 kb
Host smart-86ca058c-1509-411f-bcc5-23d5d444f064
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233832053 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.233832053
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3738251060
Short name T908
Test name
Test status
Simulation time 490102496 ps
CPU time 1.8 seconds
Started May 09 02:31:18 PM PDT 24
Finished May 09 02:31:27 PM PDT 24
Peak memory 201244 kb
Host smart-f0d208bd-eba4-4339-99a0-e58a3b139fb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738251060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3738251060
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2158896229
Short name T839
Test name
Test status
Simulation time 4396139766 ps
CPU time 9.72 seconds
Started May 09 02:31:15 PM PDT 24
Finished May 09 02:31:32 PM PDT 24
Peak memory 201540 kb
Host smart-d5754084-5995-4c95-87f3-d3a8eeccc5bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158896229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2158896229
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.502562861
Short name T845
Test name
Test status
Simulation time 754169322 ps
CPU time 1.98 seconds
Started May 09 02:31:23 PM PDT 24
Finished May 09 02:31:31 PM PDT 24
Peak memory 201428 kb
Host smart-a7772310-a5df-46de-b9f3-7bce2e749b04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502562861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.502562861
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2745518454
Short name T341
Test name
Test status
Simulation time 8275083440 ps
CPU time 19.81 seconds
Started May 09 02:31:20 PM PDT 24
Finished May 09 02:31:47 PM PDT 24
Peak memory 201508 kb
Host smart-bbbed4d5-c19d-48ff-bb57-1444606f8ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745518454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2745518454
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3180097699
Short name T812
Test name
Test status
Simulation time 470925058 ps
CPU time 1.79 seconds
Started May 09 02:31:24 PM PDT 24
Finished May 09 02:31:32 PM PDT 24
Peak memory 201244 kb
Host smart-6b2041fc-5156-4ce4-bd4d-2e5c2d0122a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180097699 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3180097699
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1468880572
Short name T135
Test name
Test status
Simulation time 531393076 ps
CPU time 1.08 seconds
Started May 09 02:31:25 PM PDT 24
Finished May 09 02:31:32 PM PDT 24
Peak memory 201256 kb
Host smart-7539e1bf-60b0-4b77-97ab-bd11e51c3e3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468880572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1468880572
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.184317338
Short name T906
Test name
Test status
Simulation time 475571299 ps
CPU time 1.18 seconds
Started May 09 02:31:26 PM PDT 24
Finished May 09 02:31:33 PM PDT 24
Peak memory 201176 kb
Host smart-6bd85471-738a-495f-b228-19960d33e064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184317338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.184317338
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2553474425
Short name T139
Test name
Test status
Simulation time 2549445352 ps
CPU time 2.35 seconds
Started May 09 02:31:29 PM PDT 24
Finished May 09 02:31:37 PM PDT 24
Peak memory 201308 kb
Host smart-e2c6dcbe-8e71-42db-9ee8-dbec948d8aab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553474425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2553474425
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1682104386
Short name T81
Test name
Test status
Simulation time 599282373 ps
CPU time 1.82 seconds
Started May 09 02:31:27 PM PDT 24
Finished May 09 02:31:34 PM PDT 24
Peak memory 201332 kb
Host smart-85232100-f71d-4493-a13a-c38a7257af93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682104386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1682104386
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2781806992
Short name T873
Test name
Test status
Simulation time 8977877242 ps
CPU time 7.15 seconds
Started May 09 02:31:25 PM PDT 24
Finished May 09 02:31:38 PM PDT 24
Peak memory 201500 kb
Host smart-d7db980c-9a0b-4818-bfaf-a9adfe3f9401
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781806992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2781806992
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1601801358
Short name T822
Test name
Test status
Simulation time 557262235 ps
CPU time 1.49 seconds
Started May 09 02:31:25 PM PDT 24
Finished May 09 02:31:32 PM PDT 24
Peak memory 201304 kb
Host smart-ba78886c-9bf3-4574-bffb-76fabd723b4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601801358 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1601801358
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3147989721
Short name T918
Test name
Test status
Simulation time 390793561 ps
CPU time 0.94 seconds
Started May 09 02:31:27 PM PDT 24
Finished May 09 02:31:34 PM PDT 24
Peak memory 201276 kb
Host smart-0f486c26-ee58-4d77-ae96-88b5cc76b16a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147989721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3147989721
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4100419935
Short name T870
Test name
Test status
Simulation time 558996180 ps
CPU time 0.99 seconds
Started May 09 02:31:30 PM PDT 24
Finished May 09 02:31:37 PM PDT 24
Peak memory 201460 kb
Host smart-d8aa5d04-1456-49cc-81f6-0333b7ce8273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100419935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4100419935
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.558331034
Short name T60
Test name
Test status
Simulation time 4055405455 ps
CPU time 16.09 seconds
Started May 09 02:31:25 PM PDT 24
Finished May 09 02:31:47 PM PDT 24
Peak memory 201568 kb
Host smart-7c2d5160-fa09-49de-b406-98e9e92e2f62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558331034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.558331034
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2158325641
Short name T847
Test name
Test status
Simulation time 384687398 ps
CPU time 3.16 seconds
Started May 09 02:31:28 PM PDT 24
Finished May 09 02:31:37 PM PDT 24
Peak memory 217916 kb
Host smart-7c668bd5-2c9e-4b03-863e-a7b330d80219
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158325641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2158325641
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3857398145
Short name T342
Test name
Test status
Simulation time 4653843120 ps
CPU time 4.52 seconds
Started May 09 02:31:28 PM PDT 24
Finished May 09 02:31:38 PM PDT 24
Peak memory 201524 kb
Host smart-0f78f1c5-90e4-4c9c-8aea-c75b8db36930
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857398145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3857398145
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.431358165
Short name T374
Test name
Test status
Simulation time 499762056 ps
CPU time 1.68 seconds
Started May 09 02:50:40 PM PDT 24
Finished May 09 02:50:52 PM PDT 24
Peak memory 201952 kb
Host smart-6e9006ee-f1e3-439f-8972-9c2151ca11f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431358165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.431358165
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.516348027
Short name T246
Test name
Test status
Simulation time 190595701976 ps
CPU time 237.39 seconds
Started May 09 02:50:34 PM PDT 24
Finished May 09 02:54:44 PM PDT 24
Peak memory 202364 kb
Host smart-ac12b2af-51fe-4b00-94f7-9cfd07fc2ed9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516348027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.516348027
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.787554925
Short name T721
Test name
Test status
Simulation time 162618927996 ps
CPU time 92.66 seconds
Started May 09 02:50:36 PM PDT 24
Finished May 09 02:52:20 PM PDT 24
Peak memory 202328 kb
Host smart-e4bbfa76-51f4-4132-8668-5aa1a60aa645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787554925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.787554925
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.4260321548
Short name T469
Test name
Test status
Simulation time 490670781221 ps
CPU time 1095.96 seconds
Started May 09 02:50:37 PM PDT 24
Finished May 09 03:09:05 PM PDT 24
Peak memory 202240 kb
Host smart-40f9c433-499a-407a-b5b9-675fbbe51760
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260321548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.4260321548
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2808689474
Short name T638
Test name
Test status
Simulation time 320421567918 ps
CPU time 169.9 seconds
Started May 09 02:50:38 PM PDT 24
Finished May 09 02:53:39 PM PDT 24
Peak memory 202340 kb
Host smart-bca44c10-7cfe-4339-86ff-2ff7835534cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808689474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2808689474
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3864043235
Short name T616
Test name
Test status
Simulation time 161381878892 ps
CPU time 371.24 seconds
Started May 09 02:50:39 PM PDT 24
Finished May 09 02:57:01 PM PDT 24
Peak memory 202320 kb
Host smart-19287d95-a074-4c03-88a4-1d87f951deab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864043235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3864043235
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.600416586
Short name T573
Test name
Test status
Simulation time 247061480239 ps
CPU time 147.58 seconds
Started May 09 02:50:36 PM PDT 24
Finished May 09 02:53:15 PM PDT 24
Peak memory 202332 kb
Host smart-bcaeb5ff-aded-4e36-a7da-fac84eaa4d02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600416586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.600416586
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2144433674
Short name T626
Test name
Test status
Simulation time 576085408625 ps
CPU time 706.55 seconds
Started May 09 02:50:36 PM PDT 24
Finished May 09 03:02:34 PM PDT 24
Peak memory 202292 kb
Host smart-9f45afc7-14ae-4a44-96f4-ef889b7f065b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144433674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2144433674
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1031401876
Short name T722
Test name
Test status
Simulation time 80816740750 ps
CPU time 224.8 seconds
Started May 09 02:50:37 PM PDT 24
Finished May 09 02:54:34 PM PDT 24
Peak memory 202728 kb
Host smart-49b5123f-879b-4c22-b5d8-5e9572f18a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031401876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1031401876
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1102406827
Short name T477
Test name
Test status
Simulation time 36846535282 ps
CPU time 90.45 seconds
Started May 09 02:50:38 PM PDT 24
Finished May 09 02:52:19 PM PDT 24
Peak memory 202140 kb
Host smart-b8b6b8f3-e8fd-4a0a-a14b-599bdab0b5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102406827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1102406827
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.4048242730
Short name T551
Test name
Test status
Simulation time 4169447223 ps
CPU time 1.73 seconds
Started May 09 02:50:41 PM PDT 24
Finished May 09 02:50:53 PM PDT 24
Peak memory 202084 kb
Host smart-ce1b288a-d131-4917-8089-888ac6190b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048242730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4048242730
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1099537465
Short name T426
Test name
Test status
Simulation time 5841624962 ps
CPU time 14.28 seconds
Started May 09 02:50:36 PM PDT 24
Finished May 09 02:51:02 PM PDT 24
Peak memory 202160 kb
Host smart-36ba59b2-af84-45df-9b84-d7f079fe71fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099537465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1099537465
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.4126256259
Short name T735
Test name
Test status
Simulation time 175408405481 ps
CPU time 421.92 seconds
Started May 09 02:50:40 PM PDT 24
Finished May 09 02:57:53 PM PDT 24
Peak memory 202352 kb
Host smart-102da324-4f78-40ed-9d38-50c06ec79867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126256259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
4126256259
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1080100012
Short name T598
Test name
Test status
Simulation time 74666110127 ps
CPU time 215.68 seconds
Started May 09 02:50:39 PM PDT 24
Finished May 09 02:54:26 PM PDT 24
Peak memory 210968 kb
Host smart-a018779f-a67f-44f4-b8fd-ef62a85cf3e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080100012 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1080100012
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1139913387
Short name T784
Test name
Test status
Simulation time 422742354 ps
CPU time 1.57 seconds
Started May 09 02:50:51 PM PDT 24
Finished May 09 02:50:57 PM PDT 24
Peak memory 202000 kb
Host smart-23a0c6ed-d619-4876-a395-666804a29aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139913387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1139913387
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2183622098
Short name T782
Test name
Test status
Simulation time 163292397868 ps
CPU time 8.22 seconds
Started May 09 02:50:52 PM PDT 24
Finished May 09 02:51:05 PM PDT 24
Peak memory 202348 kb
Host smart-73e3aa16-c907-4efb-b91f-01f638a50312
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183622098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2183622098
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1028381145
Short name T321
Test name
Test status
Simulation time 190513543355 ps
CPU time 463.68 seconds
Started May 09 02:50:41 PM PDT 24
Finished May 09 02:58:35 PM PDT 24
Peak memory 202304 kb
Host smart-73ae1a2f-23aa-41d3-a0e6-e6250af6da35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028381145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1028381145
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.927016312
Short name T528
Test name
Test status
Simulation time 166260359206 ps
CPU time 197.57 seconds
Started May 09 02:50:39 PM PDT 24
Finished May 09 02:54:07 PM PDT 24
Peak memory 202352 kb
Host smart-843bbb8b-2c1d-4e78-8c89-5c28cb32388e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927016312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.927016312
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1750529632
Short name T586
Test name
Test status
Simulation time 334103232997 ps
CPU time 208.9 seconds
Started May 09 02:50:38 PM PDT 24
Finished May 09 02:54:18 PM PDT 24
Peak memory 202252 kb
Host smart-edfcefdb-4bf8-42d9-a98d-2a6fca5e7cf8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750529632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1750529632
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.303066323
Short name T580
Test name
Test status
Simulation time 330519453946 ps
CPU time 815.42 seconds
Started May 09 02:50:40 PM PDT 24
Finished May 09 03:04:26 PM PDT 24
Peak memory 202424 kb
Host smart-b899b056-7475-4f5f-b11b-1ef6f7de8e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303066323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.303066323
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3805018623
Short name T583
Test name
Test status
Simulation time 490892477793 ps
CPU time 554.3 seconds
Started May 09 02:50:40 PM PDT 24
Finished May 09 03:00:05 PM PDT 24
Peak memory 202256 kb
Host smart-9e5f9023-83e4-49e6-add2-fcce9077fc45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805018623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3805018623
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3899253
Short name T570
Test name
Test status
Simulation time 199234978335 ps
CPU time 244.14 seconds
Started May 09 02:50:41 PM PDT 24
Finished May 09 02:54:55 PM PDT 24
Peak memory 202308 kb
Host smart-54e77a33-6f35-4145-8cfa-aa34d45bb05d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wak
eup.3899253
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1399608528
Short name T436
Test name
Test status
Simulation time 198756097471 ps
CPU time 477.9 seconds
Started May 09 02:50:43 PM PDT 24
Finished May 09 02:58:50 PM PDT 24
Peak memory 202384 kb
Host smart-98df8cc0-9af0-4767-9963-d1c3600801fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399608528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1399608528
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3216951964
Short name T491
Test name
Test status
Simulation time 77447061122 ps
CPU time 377.11 seconds
Started May 09 02:50:41 PM PDT 24
Finished May 09 02:57:08 PM PDT 24
Peak memory 202732 kb
Host smart-3867ee2a-a4ac-4518-8559-4b3d10c3df15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216951964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3216951964
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1520032785
Short name T680
Test name
Test status
Simulation time 21702348950 ps
CPU time 24.51 seconds
Started May 09 02:50:39 PM PDT 24
Finished May 09 02:51:14 PM PDT 24
Peak memory 202132 kb
Host smart-e7fd7d61-0904-462d-9e1c-3a2e907e8e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520032785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1520032785
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3340507292
Short name T479
Test name
Test status
Simulation time 4403234106 ps
CPU time 9.73 seconds
Started May 09 02:50:51 PM PDT 24
Finished May 09 02:51:06 PM PDT 24
Peak memory 202140 kb
Host smart-e15f078e-9693-411d-a444-da76e7d6268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340507292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3340507292
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2821738522
Short name T71
Test name
Test status
Simulation time 7500654939 ps
CPU time 5.28 seconds
Started May 09 02:50:37 PM PDT 24
Finished May 09 02:50:54 PM PDT 24
Peak memory 218948 kb
Host smart-d3b9603e-1e5a-49a5-bbc7-fbe3fa7f44b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821738522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2821738522
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2245675749
Short name T636
Test name
Test status
Simulation time 6014005155 ps
CPU time 14.27 seconds
Started May 09 02:50:39 PM PDT 24
Finished May 09 02:51:04 PM PDT 24
Peak memory 202084 kb
Host smart-240e5cef-460d-43d4-add3-4c0c2170a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245675749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2245675749
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1210267193
Short name T519
Test name
Test status
Simulation time 5273532969 ps
CPU time 3.42 seconds
Started May 09 02:50:50 PM PDT 24
Finished May 09 02:50:59 PM PDT 24
Peak memory 202172 kb
Host smart-cfdccc83-c0fa-4775-8b3f-0e512f852277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210267193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1210267193
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.800011573
Short name T257
Test name
Test status
Simulation time 29181039980 ps
CPU time 40.3 seconds
Started May 09 02:50:39 PM PDT 24
Finished May 09 02:51:30 PM PDT 24
Peak memory 210932 kb
Host smart-fa6aacf1-f156-4386-8b66-98c0f7ff4661
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800011573 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.800011573
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2428921929
Short name T739
Test name
Test status
Simulation time 512019091172 ps
CPU time 390.4 seconds
Started May 09 02:51:03 PM PDT 24
Finished May 09 02:57:39 PM PDT 24
Peak memory 202380 kb
Host smart-b9113f48-2c6e-446a-92dc-0f7bf8184cb5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428921929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2428921929
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.381402769
Short name T282
Test name
Test status
Simulation time 541423331800 ps
CPU time 1329.52 seconds
Started May 09 02:51:10 PM PDT 24
Finished May 09 03:13:28 PM PDT 24
Peak memory 202372 kb
Host smart-8605dbf3-a583-4b20-916b-9f9ff8f6d2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381402769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.381402769
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3756305821
Short name T703
Test name
Test status
Simulation time 329263683808 ps
CPU time 169.71 seconds
Started May 09 02:51:08 PM PDT 24
Finished May 09 02:54:06 PM PDT 24
Peak memory 202348 kb
Host smart-35f21ea5-ae05-4eed-b060-39ec553b89aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756305821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3756305821
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.276343147
Short name T419
Test name
Test status
Simulation time 320845945539 ps
CPU time 725.49 seconds
Started May 09 02:51:07 PM PDT 24
Finished May 09 03:03:20 PM PDT 24
Peak memory 202280 kb
Host smart-8b325310-d6bf-47fb-a450-a7262d6345ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=276343147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.276343147
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3021114436
Short name T504
Test name
Test status
Simulation time 327449403184 ps
CPU time 809.38 seconds
Started May 09 02:51:10 PM PDT 24
Finished May 09 03:04:47 PM PDT 24
Peak memory 202340 kb
Host smart-cf309a06-3ce2-420b-8324-37a8171c6a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021114436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3021114436
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.905214637
Short name T746
Test name
Test status
Simulation time 326682250055 ps
CPU time 111.07 seconds
Started May 09 02:51:07 PM PDT 24
Finished May 09 02:53:06 PM PDT 24
Peak memory 202284 kb
Host smart-1eeb1d81-d8d5-43e3-a4d1-94af2eaefd87
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=905214637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.905214637
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1071230010
Short name T450
Test name
Test status
Simulation time 609255949357 ps
CPU time 722.89 seconds
Started May 09 02:51:03 PM PDT 24
Finished May 09 03:03:11 PM PDT 24
Peak memory 202340 kb
Host smart-433ff8f1-0231-46d1-91ad-f17a627c12fa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071230010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1071230010
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.171558618
Short name T365
Test name
Test status
Simulation time 33469630464 ps
CPU time 70.35 seconds
Started May 09 02:51:04 PM PDT 24
Finished May 09 02:52:21 PM PDT 24
Peak memory 202184 kb
Host smart-bc8fa7a9-f6ed-4c49-a3e7-2daa20398fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171558618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.171558618
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.401983669
Short name T552
Test name
Test status
Simulation time 5533815580 ps
CPU time 8.23 seconds
Started May 09 02:51:10 PM PDT 24
Finished May 09 02:51:26 PM PDT 24
Peak memory 202072 kb
Host smart-5b52a560-39f6-4589-ae3a-7ab1809a83db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401983669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.401983669
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1610068222
Short name T113
Test name
Test status
Simulation time 5744521236 ps
CPU time 2.18 seconds
Started May 09 02:51:09 PM PDT 24
Finished May 09 02:51:19 PM PDT 24
Peak memory 202172 kb
Host smart-7465edd8-aaf1-4400-b8e7-9948bf4dcbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610068222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1610068222
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2158132960
Short name T154
Test name
Test status
Simulation time 341752056055 ps
CPU time 1199.85 seconds
Started May 09 02:51:06 PM PDT 24
Finished May 09 03:11:14 PM PDT 24
Peak memory 210908 kb
Host smart-293b5cac-a329-4c22-a3e1-dd756795f082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158132960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2158132960
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.290860858
Short name T461
Test name
Test status
Simulation time 316168766 ps
CPU time 0.79 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:51:20 PM PDT 24
Peak memory 202016 kb
Host smart-97763a4f-c19b-4641-96b1-7d97fe023b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290860858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.290860858
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.976234865
Short name T166
Test name
Test status
Simulation time 176282007461 ps
CPU time 27.26 seconds
Started May 09 02:51:06 PM PDT 24
Finished May 09 02:51:40 PM PDT 24
Peak memory 202364 kb
Host smart-702a810c-0373-4528-bda6-5732a9fc27ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976234865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.976234865
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3004310911
Short name T318
Test name
Test status
Simulation time 324924142382 ps
CPU time 374.2 seconds
Started May 09 02:51:02 PM PDT 24
Finished May 09 02:57:23 PM PDT 24
Peak memory 202320 kb
Host smart-1497f65a-93a9-4b61-85d5-141e0e013ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004310911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3004310911
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2439562713
Short name T611
Test name
Test status
Simulation time 496097603945 ps
CPU time 276.06 seconds
Started May 09 02:51:06 PM PDT 24
Finished May 09 02:55:49 PM PDT 24
Peak memory 202324 kb
Host smart-2628fa1d-0cee-4d43-aaa8-41056a5f5f32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439562713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2439562713
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3659128102
Short name T329
Test name
Test status
Simulation time 331764917534 ps
CPU time 786.05 seconds
Started May 09 02:51:09 PM PDT 24
Finished May 09 03:04:23 PM PDT 24
Peak memory 202348 kb
Host smart-bdec9454-7723-4bfc-9822-809927ddaf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659128102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3659128102
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2710575999
Short name T480
Test name
Test status
Simulation time 161919219314 ps
CPU time 379.3 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:57:38 PM PDT 24
Peak memory 202312 kb
Host smart-7979e3f1-4826-49f6-88a1-df3805a66273
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710575999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2710575999
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3715327228
Short name T773
Test name
Test status
Simulation time 573338313673 ps
CPU time 1397.25 seconds
Started May 09 02:51:07 PM PDT 24
Finished May 09 03:14:32 PM PDT 24
Peak memory 202324 kb
Host smart-5185d5ff-6ff9-48fd-8058-0132f2bcfbd0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715327228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3715327228
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2427566943
Short name T783
Test name
Test status
Simulation time 405430136864 ps
CPU time 229.34 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:55:08 PM PDT 24
Peak memory 202312 kb
Host smart-583ef845-85f5-4078-9f10-05ba9fd8db60
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427566943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2427566943
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2156179463
Short name T47
Test name
Test status
Simulation time 145207959898 ps
CPU time 705.51 seconds
Started May 09 02:51:09 PM PDT 24
Finished May 09 03:03:02 PM PDT 24
Peak memory 202692 kb
Host smart-f80c873a-9fbb-4ac3-a7cd-3e858f8dbe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156179463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2156179463
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2394152345
Short name T554
Test name
Test status
Simulation time 21488254247 ps
CPU time 9.85 seconds
Started May 09 02:51:08 PM PDT 24
Finished May 09 02:51:26 PM PDT 24
Peak memory 202152 kb
Host smart-0c8cceaf-a8d1-4342-a2cd-c352c94dad17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394152345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2394152345
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2967864399
Short name T478
Test name
Test status
Simulation time 3770028051 ps
CPU time 2.32 seconds
Started May 09 02:51:08 PM PDT 24
Finished May 09 02:51:17 PM PDT 24
Peak memory 202160 kb
Host smart-bdc13c92-f5f8-4c8a-9002-3d61ec5bcfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967864399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2967864399
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3039560328
Short name T147
Test name
Test status
Simulation time 6141621656 ps
CPU time 4.32 seconds
Started May 09 02:51:06 PM PDT 24
Finished May 09 02:51:18 PM PDT 24
Peak memory 202128 kb
Host smart-6d32e961-737a-4c37-98b9-8388add42fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039560328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3039560328
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1343457976
Short name T305
Test name
Test status
Simulation time 246280726814 ps
CPU time 147.61 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:53:47 PM PDT 24
Peak memory 202416 kb
Host smart-585222e2-0237-4f7a-8558-7c674df954ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343457976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1343457976
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3041442319
Short name T109
Test name
Test status
Simulation time 306266292491 ps
CPU time 376.88 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:57:36 PM PDT 24
Peak memory 218192 kb
Host smart-e3eeffac-dd65-401d-b03d-d72f4462190f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041442319 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3041442319
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1940866104
Short name T487
Test name
Test status
Simulation time 418670675 ps
CPU time 1.05 seconds
Started May 09 02:51:16 PM PDT 24
Finished May 09 02:51:23 PM PDT 24
Peak memory 202028 kb
Host smart-a4a8a566-7c6a-4f40-846b-b158bf368d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940866104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1940866104
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3845366736
Short name T62
Test name
Test status
Simulation time 178569663030 ps
CPU time 367.61 seconds
Started May 09 02:51:15 PM PDT 24
Finished May 09 02:57:29 PM PDT 24
Peak memory 202348 kb
Host smart-21d8e83d-6c38-4e8c-be21-f0e4712f18ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845366736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3845366736
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3505607804
Short name T331
Test name
Test status
Simulation time 341626734940 ps
CPU time 221.88 seconds
Started May 09 02:51:31 PM PDT 24
Finished May 09 02:55:16 PM PDT 24
Peak memory 202292 kb
Host smart-403bac09-062f-4bb3-a631-04dcd157f781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505607804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3505607804
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.273661966
Short name T264
Test name
Test status
Simulation time 328431458020 ps
CPU time 144.72 seconds
Started May 09 02:51:13 PM PDT 24
Finished May 09 02:53:45 PM PDT 24
Peak memory 202396 kb
Host smart-55427a35-de63-4047-9f5f-98ea5e1e2371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273661966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.273661966
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2423173214
Short name T422
Test name
Test status
Simulation time 495435612835 ps
CPU time 1204.01 seconds
Started May 09 02:51:15 PM PDT 24
Finished May 09 03:11:26 PM PDT 24
Peak memory 202328 kb
Host smart-b89d0a2d-7dcf-4a38-abb8-dedb3a92437e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423173214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2423173214
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.911566470
Short name T402
Test name
Test status
Simulation time 165349634897 ps
CPU time 351.61 seconds
Started May 09 02:51:13 PM PDT 24
Finished May 09 02:57:12 PM PDT 24
Peak memory 202276 kb
Host smart-47ea03bb-9ceb-40ca-98d8-d7c4762b9cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911566470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.911566470
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1379143568
Short name T683
Test name
Test status
Simulation time 492526375709 ps
CPU time 1197.98 seconds
Started May 09 02:51:15 PM PDT 24
Finished May 09 03:11:20 PM PDT 24
Peak memory 202300 kb
Host smart-ba603b6a-c992-40f6-b600-bc7c2274d77c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379143568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1379143568
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.158422452
Short name T295
Test name
Test status
Simulation time 673052872806 ps
CPU time 1564.34 seconds
Started May 09 02:51:16 PM PDT 24
Finished May 09 03:17:27 PM PDT 24
Peak memory 202424 kb
Host smart-2eeb60d2-4745-41ff-81fb-d4d4f270b36b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158422452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.158422452
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2176233070
Short name T709
Test name
Test status
Simulation time 202598484670 ps
CPU time 121.82 seconds
Started May 09 02:51:19 PM PDT 24
Finished May 09 02:53:25 PM PDT 24
Peak memory 202364 kb
Host smart-2048df10-9d2b-4f40-8f97-0e544cf62c51
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176233070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2176233070
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1022034138
Short name T346
Test name
Test status
Simulation time 73436404997 ps
CPU time 320.28 seconds
Started May 09 02:51:18 PM PDT 24
Finished May 09 02:56:44 PM PDT 24
Peak memory 202304 kb
Host smart-06bccb0f-e27c-46f8-a931-4c1cde3b81ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022034138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1022034138
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.102415928
Short name T514
Test name
Test status
Simulation time 34499850049 ps
CPU time 20.44 seconds
Started May 09 02:51:19 PM PDT 24
Finished May 09 02:51:44 PM PDT 24
Peak memory 202144 kb
Host smart-84c715d3-6d76-42c0-9e0a-32b70065e180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102415928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.102415928
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1791588180
Short name T105
Test name
Test status
Simulation time 2854281356 ps
CPU time 4.06 seconds
Started May 09 02:51:16 PM PDT 24
Finished May 09 02:51:26 PM PDT 24
Peak memory 202136 kb
Host smart-c257e924-11d8-4de1-a2b7-0f54f0c78bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791588180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1791588180
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1189059286
Short name T108
Test name
Test status
Simulation time 5930393537 ps
CPU time 13.03 seconds
Started May 09 02:51:15 PM PDT 24
Finished May 09 02:51:35 PM PDT 24
Peak memory 202080 kb
Host smart-98e03a9c-82a0-409a-ae94-544462e9441b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189059286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1189059286
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2158907957
Short name T562
Test name
Test status
Simulation time 316304946269 ps
CPU time 719.32 seconds
Started May 09 02:51:12 PM PDT 24
Finished May 09 03:03:19 PM PDT 24
Peak memory 212784 kb
Host smart-9889ea30-20a6-42fe-9b73-7b5054d99a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158907957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2158907957
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3287511386
Short name T107
Test name
Test status
Simulation time 497768586 ps
CPU time 0.68 seconds
Started May 09 02:51:28 PM PDT 24
Finished May 09 02:51:32 PM PDT 24
Peak memory 202000 kb
Host smart-16892fcb-be78-41ef-930a-9b1c90bcda2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287511386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3287511386
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3657807354
Short name T273
Test name
Test status
Simulation time 167316213048 ps
CPU time 105.75 seconds
Started May 09 02:51:16 PM PDT 24
Finished May 09 02:53:08 PM PDT 24
Peak memory 202364 kb
Host smart-1c6946b5-6a2a-422d-a1c2-b017dbaac7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657807354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3657807354
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2567286347
Short name T447
Test name
Test status
Simulation time 158090774594 ps
CPU time 65.38 seconds
Started May 09 02:51:14 PM PDT 24
Finished May 09 02:52:27 PM PDT 24
Peak memory 202368 kb
Host smart-166aad97-18fe-4d9d-b684-3766eb8522a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567286347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2567286347
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1202563829
Short name T592
Test name
Test status
Simulation time 491651050670 ps
CPU time 1197.88 seconds
Started May 09 02:51:14 PM PDT 24
Finished May 09 03:11:19 PM PDT 24
Peak memory 202380 kb
Host smart-8c4f3294-8a48-4398-bc8a-cca420017879
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202563829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1202563829
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2777065591
Short name T432
Test name
Test status
Simulation time 486330666560 ps
CPU time 1066.27 seconds
Started May 09 02:51:14 PM PDT 24
Finished May 09 03:09:07 PM PDT 24
Peak memory 202324 kb
Host smart-4447bbac-93d0-4a3c-8edc-24d91d13c817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777065591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2777065591
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.4249500518
Short name T724
Test name
Test status
Simulation time 495955445373 ps
CPU time 1036.34 seconds
Started May 09 02:51:16 PM PDT 24
Finished May 09 03:08:39 PM PDT 24
Peak memory 202292 kb
Host smart-934c8e90-ea39-4d30-bd29-fe9b116f898d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249500518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.4249500518
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1576386053
Short name T243
Test name
Test status
Simulation time 354247113947 ps
CPU time 430.8 seconds
Started May 09 02:51:16 PM PDT 24
Finished May 09 02:58:33 PM PDT 24
Peak memory 202424 kb
Host smart-7a7b67f9-0f03-4d1b-85a9-e0b49847210f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576386053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1576386053
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.4208831204
Short name T678
Test name
Test status
Simulation time 591450529159 ps
CPU time 332.59 seconds
Started May 09 02:51:19 PM PDT 24
Finished May 09 02:56:56 PM PDT 24
Peak memory 202324 kb
Host smart-5afad79c-bb5e-4ebb-9f88-19d49ed3bb97
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208831204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.4208831204
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1820539530
Short name T588
Test name
Test status
Simulation time 74504210513 ps
CPU time 309.63 seconds
Started May 09 02:51:13 PM PDT 24
Finished May 09 02:56:30 PM PDT 24
Peak memory 202720 kb
Host smart-73bd746e-9b4f-49ea-b353-7ae502d27dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820539530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1820539530
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2348196238
Short name T377
Test name
Test status
Simulation time 42015398832 ps
CPU time 25.76 seconds
Started May 09 02:51:12 PM PDT 24
Finished May 09 02:51:45 PM PDT 24
Peak memory 202160 kb
Host smart-22eaad1a-8adf-4480-bd16-d3d7c2ed6197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348196238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2348196238
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2798816584
Short name T431
Test name
Test status
Simulation time 3341544830 ps
CPU time 8.3 seconds
Started May 09 02:51:18 PM PDT 24
Finished May 09 02:51:32 PM PDT 24
Peak memory 201772 kb
Host smart-13bedd03-8619-4d7f-8916-a5e0e2177a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798816584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2798816584
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3904462920
Short name T654
Test name
Test status
Simulation time 5664950026 ps
CPU time 12.8 seconds
Started May 09 02:51:18 PM PDT 24
Finished May 09 02:51:36 PM PDT 24
Peak memory 202108 kb
Host smart-03a9e643-5524-4525-8033-aaff45735f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904462920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3904462920
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2544346384
Short name T35
Test name
Test status
Simulation time 491617238043 ps
CPU time 436.93 seconds
Started May 09 02:51:19 PM PDT 24
Finished May 09 02:58:40 PM PDT 24
Peak memory 202296 kb
Host smart-52891202-763e-4758-84b1-27c1033347cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544346384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2544346384
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.227216788
Short name T22
Test name
Test status
Simulation time 140823320111 ps
CPU time 193.73 seconds
Started May 09 02:51:15 PM PDT 24
Finished May 09 02:54:35 PM PDT 24
Peak memory 218328 kb
Host smart-44508a6c-b3d0-4fc7-be5d-4eaf18fad673
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227216788 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.227216788
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2658420434
Short name T687
Test name
Test status
Simulation time 389225875 ps
CPU time 0.98 seconds
Started May 09 02:51:20 PM PDT 24
Finished May 09 02:51:25 PM PDT 24
Peak memory 202060 kb
Host smart-f3a531c7-15fb-4518-ab21-fc267b8fff80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658420434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2658420434
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1290404627
Short name T547
Test name
Test status
Simulation time 165200246219 ps
CPU time 98.02 seconds
Started May 09 02:51:15 PM PDT 24
Finished May 09 02:53:00 PM PDT 24
Peak memory 202448 kb
Host smart-a97cf22a-b72a-4d12-b07a-f4dbe286f79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290404627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1290404627
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1609783895
Short name T389
Test name
Test status
Simulation time 491037222784 ps
CPU time 629.87 seconds
Started May 09 02:51:13 PM PDT 24
Finished May 09 03:01:50 PM PDT 24
Peak memory 202336 kb
Host smart-11c1dcfa-2217-4d55-8394-7476f35ec449
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609783895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1609783895
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.853495786
Short name T1
Test name
Test status
Simulation time 166912552244 ps
CPU time 102.11 seconds
Started May 09 02:51:20 PM PDT 24
Finished May 09 02:53:06 PM PDT 24
Peak memory 202364 kb
Host smart-3de4908d-9d04-4565-b247-5f953bc642c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853495786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.853495786
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.56622558
Short name T357
Test name
Test status
Simulation time 162134937409 ps
CPU time 106.01 seconds
Started May 09 02:51:13 PM PDT 24
Finished May 09 02:53:07 PM PDT 24
Peak memory 202536 kb
Host smart-907b2db3-92c2-4328-a0f8-9b957e2a108a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=56622558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed
.56622558
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.4192553577
Short name T307
Test name
Test status
Simulation time 178839395788 ps
CPU time 32.08 seconds
Started May 09 02:51:16 PM PDT 24
Finished May 09 02:51:54 PM PDT 24
Peak memory 202296 kb
Host smart-1e45632a-7790-4547-b735-0d0ca5968c72
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192553577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.4192553577
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3835739878
Short name T575
Test name
Test status
Simulation time 606737515699 ps
CPU time 1326.04 seconds
Started May 09 02:51:15 PM PDT 24
Finished May 09 03:13:28 PM PDT 24
Peak memory 202336 kb
Host smart-0ef336d7-f386-44a4-aa75-f07ca75cac13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835739878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3835739878
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2416950710
Short name T434
Test name
Test status
Simulation time 40475761207 ps
CPU time 88.78 seconds
Started May 09 02:51:14 PM PDT 24
Finished May 09 02:52:50 PM PDT 24
Peak memory 202148 kb
Host smart-250832a8-80c2-4bdf-b0ef-feb297bb4a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416950710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2416950710
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.4180164625
Short name T561
Test name
Test status
Simulation time 3281025523 ps
CPU time 8.63 seconds
Started May 09 02:51:18 PM PDT 24
Finished May 09 02:51:32 PM PDT 24
Peak memory 202144 kb
Host smart-a39b47be-3e7d-4367-ae52-8f32e117f24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180164625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.4180164625
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1379483699
Short name T791
Test name
Test status
Simulation time 5456217599 ps
CPU time 13.52 seconds
Started May 09 02:51:14 PM PDT 24
Finished May 09 02:51:35 PM PDT 24
Peak memory 202088 kb
Host smart-a8f5d064-7cf7-45e9-8aae-a100cd06e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379483699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1379483699
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1995983865
Short name T179
Test name
Test status
Simulation time 204546004517 ps
CPU time 159.69 seconds
Started May 09 02:51:20 PM PDT 24
Finished May 09 02:54:04 PM PDT 24
Peak memory 202440 kb
Host smart-5577df0f-0375-46f2-a4ac-5704a569f21a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995983865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1995983865
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2307091001
Short name T596
Test name
Test status
Simulation time 17770789230 ps
CPU time 42.55 seconds
Started May 09 02:51:21 PM PDT 24
Finished May 09 02:52:07 PM PDT 24
Peak memory 210668 kb
Host smart-37dd0c25-61e7-4073-98a1-fc83ae5f76ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307091001 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2307091001
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.771204696
Short name T476
Test name
Test status
Simulation time 467019204 ps
CPU time 1.15 seconds
Started May 09 02:51:17 PM PDT 24
Finished May 09 02:51:24 PM PDT 24
Peak memory 201964 kb
Host smart-a56f6571-1fd7-4e37-bdee-da3863260986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771204696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.771204696
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.415581766
Short name T545
Test name
Test status
Simulation time 191915475940 ps
CPU time 34.68 seconds
Started May 09 02:51:20 PM PDT 24
Finished May 09 02:51:58 PM PDT 24
Peak memory 202436 kb
Host smart-56d776b5-2e65-4f28-9d59-8ce09ebe0ac8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415581766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.415581766
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3708041161
Short name T736
Test name
Test status
Simulation time 527668532445 ps
CPU time 1272.48 seconds
Started May 09 02:51:19 PM PDT 24
Finished May 09 03:12:36 PM PDT 24
Peak memory 202288 kb
Host smart-c5f05395-ebdd-4855-a680-6194d3215190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708041161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3708041161
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1459708021
Short name T198
Test name
Test status
Simulation time 163851035920 ps
CPU time 103.33 seconds
Started May 09 02:51:18 PM PDT 24
Finished May 09 02:53:06 PM PDT 24
Peak memory 202272 kb
Host smart-69b0570f-f1d6-4d7a-8aed-966c0ea5c6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459708021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1459708021
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3333324647
Short name T590
Test name
Test status
Simulation time 333171674308 ps
CPU time 399.16 seconds
Started May 09 02:51:21 PM PDT 24
Finished May 09 02:58:04 PM PDT 24
Peak memory 202348 kb
Host smart-ca70cc1f-21b2-4a5d-ad81-f595f1fa88d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333324647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3333324647
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2511789842
Short name T789
Test name
Test status
Simulation time 317978729753 ps
CPU time 193.77 seconds
Started May 09 02:51:31 PM PDT 24
Finished May 09 02:54:48 PM PDT 24
Peak memory 202372 kb
Host smart-14c4c552-bd40-498f-9ba5-097f50f0c7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511789842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2511789842
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3794459830
Short name T455
Test name
Test status
Simulation time 335889433259 ps
CPU time 738.85 seconds
Started May 09 02:51:19 PM PDT 24
Finished May 09 03:03:42 PM PDT 24
Peak memory 202352 kb
Host smart-b0e7492c-6cca-4e0a-bd31-63f157e08fb2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794459830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3794459830
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2473609680
Short name T456
Test name
Test status
Simulation time 399189737897 ps
CPU time 458.44 seconds
Started May 09 02:51:15 PM PDT 24
Finished May 09 02:59:00 PM PDT 24
Peak memory 202320 kb
Host smart-3eae4d2d-d35a-4bc7-8e4b-2dc63992db20
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473609680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2473609680
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1177052141
Short name T798
Test name
Test status
Simulation time 141691786285 ps
CPU time 545.56 seconds
Started May 09 02:51:31 PM PDT 24
Finished May 09 03:00:40 PM PDT 24
Peak memory 202540 kb
Host smart-b4159196-8458-4817-b586-97754f445589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177052141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1177052141
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2663198172
Short name T368
Test name
Test status
Simulation time 26830795782 ps
CPU time 19.65 seconds
Started May 09 02:51:28 PM PDT 24
Finished May 09 02:51:51 PM PDT 24
Peak memory 202120 kb
Host smart-0b022e52-b4af-42ac-b5a7-b83181c18f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663198172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2663198172
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1034419355
Short name T355
Test name
Test status
Simulation time 4992505338 ps
CPU time 2.08 seconds
Started May 09 02:51:31 PM PDT 24
Finished May 09 02:51:37 PM PDT 24
Peak memory 202124 kb
Host smart-62c8bf41-721b-45a6-b075-4781662f36f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034419355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1034419355
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.4281595007
Short name T428
Test name
Test status
Simulation time 5760168506 ps
CPU time 3.95 seconds
Started May 09 02:51:14 PM PDT 24
Finished May 09 02:51:25 PM PDT 24
Peak memory 202200 kb
Host smart-a30149a8-3689-404b-93cd-1f6c57c09ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281595007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.4281595007
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3832172696
Short name T51
Test name
Test status
Simulation time 25805049631 ps
CPU time 59.11 seconds
Started May 09 02:51:22 PM PDT 24
Finished May 09 02:52:24 PM PDT 24
Peak memory 210752 kb
Host smart-bcc511fd-2271-4bdd-b3e6-b49ef2f1af68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832172696 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3832172696
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3348458247
Short name T437
Test name
Test status
Simulation time 534785106 ps
CPU time 1.74 seconds
Started May 09 02:51:19 PM PDT 24
Finished May 09 02:51:25 PM PDT 24
Peak memory 201976 kb
Host smart-d6861e41-b161-4a2f-9134-bb9ace20fa23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348458247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3348458247
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2723454100
Short name T390
Test name
Test status
Simulation time 485483386903 ps
CPU time 277.97 seconds
Started May 09 02:51:21 PM PDT 24
Finished May 09 02:56:02 PM PDT 24
Peak memory 202352 kb
Host smart-78679e5d-e4eb-4300-86d4-2e93a01e5be3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723454100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2723454100
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.4235517529
Short name T231
Test name
Test status
Simulation time 484534330089 ps
CPU time 1073.37 seconds
Started May 09 02:51:28 PM PDT 24
Finished May 09 03:09:25 PM PDT 24
Peak memory 202372 kb
Host smart-dfef096b-7e75-4508-abbe-6a7c9f8cf0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235517529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.4235517529
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2337791817
Short name T556
Test name
Test status
Simulation time 494997918490 ps
CPU time 303.92 seconds
Started May 09 02:51:19 PM PDT 24
Finished May 09 02:56:27 PM PDT 24
Peak memory 202236 kb
Host smart-66b40a76-d062-412e-a3eb-bce8009da50a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337791817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2337791817
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.4169518047
Short name T189
Test name
Test status
Simulation time 420599400429 ps
CPU time 83.73 seconds
Started May 09 02:51:19 PM PDT 24
Finished May 09 02:52:47 PM PDT 24
Peak memory 202372 kb
Host smart-49e3decc-20f6-4d0a-8e09-d8ca1cca0201
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169518047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.4169518047
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.56086780
Short name T733
Test name
Test status
Simulation time 394175120923 ps
CPU time 194.56 seconds
Started May 09 02:51:22 PM PDT 24
Finished May 09 02:54:39 PM PDT 24
Peak memory 202308 kb
Host smart-fada9fc2-2afb-4b18-803c-481186f0900b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56086780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.a
dc_ctrl_filters_wakeup_fixed.56086780
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.95556894
Short name T410
Test name
Test status
Simulation time 35855576793 ps
CPU time 81.21 seconds
Started May 09 02:51:22 PM PDT 24
Finished May 09 02:52:46 PM PDT 24
Peak memory 202164 kb
Host smart-43c8737f-bb0b-45d4-ab21-6bf75fef2c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95556894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.95556894
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2778504281
Short name T417
Test name
Test status
Simulation time 4207547135 ps
CPU time 2.17 seconds
Started May 09 02:51:18 PM PDT 24
Finished May 09 02:51:25 PM PDT 24
Peak memory 202096 kb
Host smart-cc64c030-a492-4da8-94dc-863f690eb20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778504281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2778504281
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.395994998
Short name T370
Test name
Test status
Simulation time 5851175886 ps
CPU time 1.93 seconds
Started May 09 02:51:15 PM PDT 24
Finished May 09 02:51:24 PM PDT 24
Peak memory 202168 kb
Host smart-d0fc06da-b24b-4821-929c-1c043854dfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395994998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.395994998
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.4059379165
Short name T275
Test name
Test status
Simulation time 166827912679 ps
CPU time 229.31 seconds
Started May 09 02:51:21 PM PDT 24
Finished May 09 02:55:14 PM PDT 24
Peak memory 218656 kb
Host smart-8828ac50-07e9-4897-a8b0-9f66070cf9ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059379165 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.4059379165
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1338010795
Short name T663
Test name
Test status
Simulation time 354174741 ps
CPU time 1.49 seconds
Started May 09 02:51:26 PM PDT 24
Finished May 09 02:51:30 PM PDT 24
Peak memory 201964 kb
Host smart-e6cd4e4a-bada-43d9-99c2-23183ce3f7ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338010795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1338010795
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3445791562
Short name T513
Test name
Test status
Simulation time 328039254187 ps
CPU time 180.4 seconds
Started May 09 02:51:26 PM PDT 24
Finished May 09 02:54:29 PM PDT 24
Peak memory 202308 kb
Host smart-d9b26511-31f4-4e97-9806-b7b1f0def436
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445791562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3445791562
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1990661132
Short name T645
Test name
Test status
Simulation time 496377477175 ps
CPU time 310.88 seconds
Started May 09 02:51:29 PM PDT 24
Finished May 09 02:56:44 PM PDT 24
Peak memory 202368 kb
Host smart-f8fb3e70-e94c-4a17-be11-56f39c7f742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990661132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1990661132
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.677935589
Short name T167
Test name
Test status
Simulation time 328716388039 ps
CPU time 68.23 seconds
Started May 09 02:51:29 PM PDT 24
Finished May 09 02:52:41 PM PDT 24
Peak memory 201944 kb
Host smart-ec0833ea-e6a8-4c8f-a360-6f045302cc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677935589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.677935589
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2841500707
Short name T648
Test name
Test status
Simulation time 324975908783 ps
CPU time 193.51 seconds
Started May 09 02:51:30 PM PDT 24
Finished May 09 02:54:47 PM PDT 24
Peak memory 202340 kb
Host smart-0439a1cb-6427-4f67-a6d1-3427141d5cda
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841500707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2841500707
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2632377443
Short name T393
Test name
Test status
Simulation time 158083576513 ps
CPU time 334.72 seconds
Started May 09 02:51:32 PM PDT 24
Finished May 09 02:57:10 PM PDT 24
Peak memory 202292 kb
Host smart-7cce2074-fc79-47f7-87ef-5d88a7ab021a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632377443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2632377443
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3062129093
Short name T468
Test name
Test status
Simulation time 361568073922 ps
CPU time 403.28 seconds
Started May 09 02:51:24 PM PDT 24
Finished May 09 02:58:09 PM PDT 24
Peak memory 202372 kb
Host smart-28ae30a5-f1ce-4185-aa9f-660c058b780d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062129093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3062129093
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.59933901
Short name T409
Test name
Test status
Simulation time 214818573963 ps
CPU time 246.45 seconds
Started May 09 02:51:28 PM PDT 24
Finished May 09 02:55:38 PM PDT 24
Peak memory 202376 kb
Host smart-5f3205ed-9267-4856-ad5a-ec299a954844
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59933901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.a
dc_ctrl_filters_wakeup_fixed.59933901
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.4158307972
Short name T421
Test name
Test status
Simulation time 36226708409 ps
CPU time 23.73 seconds
Started May 09 02:51:26 PM PDT 24
Finished May 09 02:51:53 PM PDT 24
Peak memory 202172 kb
Host smart-69e489e7-71ce-4a51-b0c8-c6dbb30addec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158307972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.4158307972
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3278834401
Short name T354
Test name
Test status
Simulation time 4428691053 ps
CPU time 11.37 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:51:42 PM PDT 24
Peak memory 202132 kb
Host smart-bed3872b-2c7e-46f7-b1e4-6c0ec79e61ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278834401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3278834401
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3134724746
Short name T679
Test name
Test status
Simulation time 5894429838 ps
CPU time 6.94 seconds
Started May 09 02:51:22 PM PDT 24
Finished May 09 02:51:32 PM PDT 24
Peak memory 202144 kb
Host smart-fd478742-fd31-40e5-957a-427795241fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134724746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3134724746
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1739228066
Short name T553
Test name
Test status
Simulation time 335973104795 ps
CPU time 819.21 seconds
Started May 09 02:51:24 PM PDT 24
Finished May 09 03:05:05 PM PDT 24
Peak memory 202320 kb
Host smart-0ba39ec9-ba16-4df8-ba6a-3bf34312a4fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739228066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1739228066
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3461643630
Short name T619
Test name
Test status
Simulation time 294734215 ps
CPU time 1.22 seconds
Started May 09 02:51:29 PM PDT 24
Finished May 09 02:51:34 PM PDT 24
Peak memory 202016 kb
Host smart-11bc9030-0ca0-473b-b157-2460d36b0a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461643630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3461643630
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2479882326
Short name T549
Test name
Test status
Simulation time 205520247847 ps
CPU time 480.18 seconds
Started May 09 02:51:29 PM PDT 24
Finished May 09 02:59:33 PM PDT 24
Peak memory 202388 kb
Host smart-2adca57f-3d70-40ae-a8f7-2824ca100309
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479882326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2479882326
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3433159263
Short name T702
Test name
Test status
Simulation time 166111921203 ps
CPU time 365.04 seconds
Started May 09 02:51:26 PM PDT 24
Finished May 09 02:57:34 PM PDT 24
Peak memory 202384 kb
Host smart-69e15bf1-6835-4b7d-aa57-834ee4bafc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433159263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3433159263
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1955357816
Short name T206
Test name
Test status
Simulation time 163787178513 ps
CPU time 359.34 seconds
Started May 09 02:51:31 PM PDT 24
Finished May 09 02:57:34 PM PDT 24
Peak memory 202304 kb
Host smart-a2745152-8113-41c7-917a-a0d54065fcd5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955357816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1955357816
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.654301575
Short name T195
Test name
Test status
Simulation time 489568176061 ps
CPU time 285.55 seconds
Started May 09 02:51:25 PM PDT 24
Finished May 09 02:56:12 PM PDT 24
Peak memory 202444 kb
Host smart-cd18458b-cb4b-4a33-963a-7b86211e7023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654301575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.654301575
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.824224887
Short name T533
Test name
Test status
Simulation time 495062387151 ps
CPU time 1163.65 seconds
Started May 09 02:51:25 PM PDT 24
Finished May 09 03:10:51 PM PDT 24
Peak memory 202356 kb
Host smart-8176280e-1658-499b-8fb8-e822c2cd623c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=824224887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.824224887
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2017588288
Short name T785
Test name
Test status
Simulation time 406837077784 ps
CPU time 131.83 seconds
Started May 09 02:51:24 PM PDT 24
Finished May 09 02:53:38 PM PDT 24
Peak memory 202332 kb
Host smart-4c696e5f-8a7e-486b-8974-440fc2d6d1b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017588288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2017588288
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1799749410
Short name T660
Test name
Test status
Simulation time 190031925306 ps
CPU time 200.03 seconds
Started May 09 02:51:31 PM PDT 24
Finished May 09 02:54:55 PM PDT 24
Peak memory 202180 kb
Host smart-2346875b-0167-4c57-891f-f94084392134
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799749410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1799749410
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2587383356
Short name T569
Test name
Test status
Simulation time 120360852719 ps
CPU time 447.3 seconds
Started May 09 02:51:25 PM PDT 24
Finished May 09 02:58:54 PM PDT 24
Peak memory 202788 kb
Host smart-dcaf1ffd-8080-4b34-a34d-208cc9f2b5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587383356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2587383356
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2926420489
Short name T508
Test name
Test status
Simulation time 21246890171 ps
CPU time 40.77 seconds
Started May 09 02:51:32 PM PDT 24
Finished May 09 02:52:16 PM PDT 24
Peak memory 202148 kb
Host smart-f42ea05a-4159-4891-a9e8-8c9fd716101a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926420489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2926420489
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2221579388
Short name T406
Test name
Test status
Simulation time 4254220578 ps
CPU time 6.76 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:51:37 PM PDT 24
Peak memory 202152 kb
Host smart-13605e5e-caf8-4781-a351-5b858a70e336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221579388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2221579388
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2195701648
Short name T449
Test name
Test status
Simulation time 5991894235 ps
CPU time 5.13 seconds
Started May 09 02:51:30 PM PDT 24
Finished May 09 02:51:39 PM PDT 24
Peak memory 202184 kb
Host smart-fa019aba-a8d1-4e34-9930-290069b0ae8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195701648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2195701648
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.4134247724
Short name T19
Test name
Test status
Simulation time 69966982835 ps
CPU time 57.33 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:52:27 PM PDT 24
Peak memory 211228 kb
Host smart-ee5b3186-fc8f-4306-a279-c74ced5b6c9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134247724 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.4134247724
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1563287152
Short name T197
Test name
Test status
Simulation time 458669412 ps
CPU time 1.75 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:51:32 PM PDT 24
Peak memory 202040 kb
Host smart-bea49d0a-7c5b-4a4b-9733-7f305d7a8150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563287152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1563287152
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.339744959
Short name T112
Test name
Test status
Simulation time 353667271722 ps
CPU time 217.24 seconds
Started May 09 02:51:28 PM PDT 24
Finished May 09 02:55:08 PM PDT 24
Peak memory 202348 kb
Host smart-11657f36-88e1-4b89-b530-3565d1159f9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339744959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.339744959
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1604746086
Short name T530
Test name
Test status
Simulation time 388297413279 ps
CPU time 210.74 seconds
Started May 09 02:51:23 PM PDT 24
Finished May 09 02:54:56 PM PDT 24
Peak memory 202424 kb
Host smart-35555df3-7316-442a-a975-194e90e910ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604746086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1604746086
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3280638949
Short name T260
Test name
Test status
Simulation time 164721831776 ps
CPU time 58.28 seconds
Started May 09 02:51:30 PM PDT 24
Finished May 09 02:52:33 PM PDT 24
Peak memory 202364 kb
Host smart-5d2721b5-5c04-437c-84f0-1df2d0e35f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280638949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3280638949
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.4098187333
Short name T535
Test name
Test status
Simulation time 320842523290 ps
CPU time 179.14 seconds
Started May 09 02:51:24 PM PDT 24
Finished May 09 02:54:25 PM PDT 24
Peak memory 202316 kb
Host smart-fac26f22-167b-40e3-bd54-3b60df40c111
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098187333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.4098187333
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1096850100
Short name T416
Test name
Test status
Simulation time 168057041391 ps
CPU time 177.48 seconds
Started May 09 02:51:29 PM PDT 24
Finished May 09 02:54:30 PM PDT 24
Peak memory 202376 kb
Host smart-44758343-1bcd-46bf-aa06-bdb6199585a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096850100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1096850100
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3374869484
Short name T597
Test name
Test status
Simulation time 490460060744 ps
CPU time 596.66 seconds
Started May 09 02:51:28 PM PDT 24
Finished May 09 03:01:28 PM PDT 24
Peak memory 202324 kb
Host smart-59b2091f-4cf6-43f5-9d43-08f246a7e4ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374869484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3374869484
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1382352939
Short name T270
Test name
Test status
Simulation time 162614240885 ps
CPU time 89.58 seconds
Started May 09 02:51:33 PM PDT 24
Finished May 09 02:53:05 PM PDT 24
Peak memory 202372 kb
Host smart-76d02fb2-04e8-4441-8031-0c0f474fcaef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382352939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1382352939
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.736071840
Short name T497
Test name
Test status
Simulation time 595364702888 ps
CPU time 347.53 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:57:18 PM PDT 24
Peak memory 202388 kb
Host smart-fbe18e90-8485-41d8-b5b9-681d428889f5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736071840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.736071840
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.965741312
Short name T218
Test name
Test status
Simulation time 130412608772 ps
CPU time 451.7 seconds
Started May 09 02:51:28 PM PDT 24
Finished May 09 02:59:03 PM PDT 24
Peak memory 202672 kb
Host smart-0cf121da-4292-445c-8d68-f51fb4149bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965741312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.965741312
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2410136382
Short name T713
Test name
Test status
Simulation time 47343741252 ps
CPU time 51.7 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:52:22 PM PDT 24
Peak memory 202176 kb
Host smart-133e2ea6-978d-4803-b5a7-634d3fb0615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410136382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2410136382
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3435484256
Short name T697
Test name
Test status
Simulation time 2926830257 ps
CPU time 7.89 seconds
Started May 09 02:51:30 PM PDT 24
Finished May 09 02:51:42 PM PDT 24
Peak memory 202100 kb
Host smart-31822a6e-5a69-4960-929a-a0cd25285f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435484256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3435484256
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3168451812
Short name T632
Test name
Test status
Simulation time 5772491762 ps
CPU time 15.51 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:51:45 PM PDT 24
Peak memory 202132 kb
Host smart-0b59620e-db3d-4c70-9c00-42b876059d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168451812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3168451812
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3107273965
Short name T48
Test name
Test status
Simulation time 99600926646 ps
CPU time 205.68 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:54:55 PM PDT 24
Peak memory 212000 kb
Host smart-4f870bb0-3884-4e46-a769-e6a5aa0883fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107273965 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3107273965
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.63317547
Short name T80
Test name
Test status
Simulation time 354049531 ps
CPU time 0.81 seconds
Started May 09 02:50:50 PM PDT 24
Finished May 09 02:50:56 PM PDT 24
Peak memory 202016 kb
Host smart-1b5d9b1a-8154-4217-a1cd-1d8856723c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63317547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.63317547
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3024911272
Short name T694
Test name
Test status
Simulation time 165108269230 ps
CPU time 79.37 seconds
Started May 09 02:50:53 PM PDT 24
Finished May 09 02:52:16 PM PDT 24
Peak memory 202348 kb
Host smart-a213acc2-79b7-4ed2-8aa3-1e0926a93555
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024911272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3024911272
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.365933726
Short name T459
Test name
Test status
Simulation time 336122332002 ps
CPU time 142.78 seconds
Started May 09 02:50:51 PM PDT 24
Finished May 09 02:53:19 PM PDT 24
Peak memory 202336 kb
Host smart-37769244-34f3-4704-98a7-ad3a0d0bbc01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=365933726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.365933726
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2008161893
Short name T794
Test name
Test status
Simulation time 502556631419 ps
CPU time 1135.77 seconds
Started May 09 02:50:40 PM PDT 24
Finished May 09 03:09:46 PM PDT 24
Peak memory 202376 kb
Host smart-ccf28e29-d7c7-47b3-a62f-755893eadd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008161893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2008161893
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.858772485
Short name T462
Test name
Test status
Simulation time 488703956707 ps
CPU time 557.05 seconds
Started May 09 02:50:51 PM PDT 24
Finished May 09 03:00:13 PM PDT 24
Peak memory 202292 kb
Host smart-760dd5ab-8964-42be-9db0-1e2dd5700e36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=858772485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.858772485
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1606332339
Short name T748
Test name
Test status
Simulation time 396062989312 ps
CPU time 214.07 seconds
Started May 09 02:50:52 PM PDT 24
Finished May 09 02:54:31 PM PDT 24
Peak memory 202400 kb
Host smart-89f39d63-1c47-4cde-b211-300a4460abf7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606332339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1606332339
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3492659002
Short name T217
Test name
Test status
Simulation time 128312607238 ps
CPU time 447.87 seconds
Started May 09 02:50:47 PM PDT 24
Finished May 09 02:58:22 PM PDT 24
Peak memory 202688 kb
Host smart-ea34d00d-268e-4dcd-94e2-d362afa2b1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492659002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3492659002
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2025380572
Short name T407
Test name
Test status
Simulation time 30212153689 ps
CPU time 72.87 seconds
Started May 09 02:50:48 PM PDT 24
Finished May 09 02:52:08 PM PDT 24
Peak memory 202152 kb
Host smart-35e3c341-250d-4b2b-8a11-1cbae0c01e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025380572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2025380572
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3867536727
Short name T718
Test name
Test status
Simulation time 5061354657 ps
CPU time 11.94 seconds
Started May 09 02:50:55 PM PDT 24
Finished May 09 02:51:10 PM PDT 24
Peak memory 202076 kb
Host smart-04b5386a-c00d-4181-9242-c12a8a484a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867536727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3867536727
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1048005241
Short name T88
Test name
Test status
Simulation time 4533953759 ps
CPU time 11.62 seconds
Started May 09 02:50:48 PM PDT 24
Finished May 09 02:51:06 PM PDT 24
Peak memory 217844 kb
Host smart-f11a8cad-4c4d-468d-b940-d4936aedf013
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048005241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1048005241
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4142206195
Short name T363
Test name
Test status
Simulation time 5788037015 ps
CPU time 3.88 seconds
Started May 09 02:50:52 PM PDT 24
Finished May 09 02:51:00 PM PDT 24
Peak memory 202124 kb
Host smart-404ec693-4cf9-431c-a814-9f64f38d117f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142206195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4142206195
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3212533847
Short name T96
Test name
Test status
Simulation time 167354664587 ps
CPU time 48.14 seconds
Started May 09 02:50:49 PM PDT 24
Finished May 09 02:51:43 PM PDT 24
Peak memory 202316 kb
Host smart-619805cd-ffb9-4edf-bb15-a757ffeccf89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212533847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3212533847
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2204930709
Short name T68
Test name
Test status
Simulation time 80263493949 ps
CPU time 223.94 seconds
Started May 09 02:50:54 PM PDT 24
Finished May 09 02:54:41 PM PDT 24
Peak memory 218576 kb
Host smart-1db0a93c-642c-43f4-9a6a-ecab751b7eb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204930709 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2204930709
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1451064574
Short name T509
Test name
Test status
Simulation time 376334194 ps
CPU time 1.32 seconds
Started May 09 02:51:25 PM PDT 24
Finished May 09 02:51:29 PM PDT 24
Peak memory 201976 kb
Host smart-2c7c3fda-48b4-4fab-af41-8d7585ef4a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451064574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1451064574
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1487924282
Short name T524
Test name
Test status
Simulation time 168929892265 ps
CPU time 84.53 seconds
Started May 09 02:51:32 PM PDT 24
Finished May 09 02:53:00 PM PDT 24
Peak memory 202392 kb
Host smart-7d45162c-9c94-4dc1-bbf0-d06672f38a02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487924282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1487924282
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2670373075
Short name T240
Test name
Test status
Simulation time 332440557968 ps
CPU time 772.71 seconds
Started May 09 02:51:24 PM PDT 24
Finished May 09 03:04:19 PM PDT 24
Peak memory 202352 kb
Host smart-c71390d2-4e80-4f62-afc3-13485fb34067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670373075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2670373075
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1616304529
Short name T474
Test name
Test status
Simulation time 166288609699 ps
CPU time 53.91 seconds
Started May 09 02:51:29 PM PDT 24
Finished May 09 02:52:27 PM PDT 24
Peak memory 201864 kb
Host smart-07715f98-66b3-48e1-b953-04b585edcd48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616304529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1616304529
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1445648039
Short name T100
Test name
Test status
Simulation time 166263515322 ps
CPU time 93.13 seconds
Started May 09 02:51:29 PM PDT 24
Finished May 09 02:53:06 PM PDT 24
Peak memory 202372 kb
Host smart-6427bccf-f875-4a43-8ff8-6ab845de5b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445648039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1445648039
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1400982786
Short name T548
Test name
Test status
Simulation time 166556784466 ps
CPU time 188.68 seconds
Started May 09 02:51:29 PM PDT 24
Finished May 09 02:54:42 PM PDT 24
Peak memory 202244 kb
Host smart-dff8ab00-d25f-4132-a422-c4f364bf66e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400982786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1400982786
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1755136249
Short name T658
Test name
Test status
Simulation time 185553117055 ps
CPU time 110.64 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:53:21 PM PDT 24
Peak memory 202340 kb
Host smart-6ec8559a-f863-42d5-82cf-52a5d704b9a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755136249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1755136249
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1861063545
Short name T761
Test name
Test status
Simulation time 385309535110 ps
CPU time 477.88 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:59:28 PM PDT 24
Peak memory 202336 kb
Host smart-08e35660-2b44-4ce2-a0bb-5ec5e64bc386
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861063545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1861063545
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3837726092
Short name T768
Test name
Test status
Simulation time 85261508949 ps
CPU time 282.37 seconds
Started May 09 02:51:29 PM PDT 24
Finished May 09 02:56:14 PM PDT 24
Peak memory 202600 kb
Host smart-dfe8fed0-3694-4358-b4e5-96d6462b2d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837726092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3837726092
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1065681523
Short name T534
Test name
Test status
Simulation time 40346037668 ps
CPU time 60.29 seconds
Started May 09 02:51:24 PM PDT 24
Finished May 09 02:52:26 PM PDT 24
Peak memory 202192 kb
Host smart-1878b373-2864-4465-b437-07a7eec0b21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065681523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1065681523
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.51515486
Short name T726
Test name
Test status
Simulation time 4240238792 ps
CPU time 3.55 seconds
Started May 09 02:51:28 PM PDT 24
Finished May 09 02:51:35 PM PDT 24
Peak memory 202076 kb
Host smart-1f08f908-e286-4099-8db6-ddad55a8e09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51515486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.51515486
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.4242115328
Short name T606
Test name
Test status
Simulation time 5870727781 ps
CPU time 4.35 seconds
Started May 09 02:51:26 PM PDT 24
Finished May 09 02:51:34 PM PDT 24
Peak memory 202132 kb
Host smart-6d00b4c3-c0e7-4854-9528-7020f886f1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242115328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.4242115328
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1889207299
Short name T538
Test name
Test status
Simulation time 47333635911 ps
CPU time 110.18 seconds
Started May 09 02:51:29 PM PDT 24
Finished May 09 02:53:22 PM PDT 24
Peak memory 202236 kb
Host smart-21336a7c-5e33-4796-83ae-e335585345c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889207299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1889207299
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.825235913
Short name T609
Test name
Test status
Simulation time 462370435 ps
CPU time 1.05 seconds
Started May 09 02:51:25 PM PDT 24
Finished May 09 02:51:28 PM PDT 24
Peak memory 202052 kb
Host smart-f79c91ca-3a64-4500-a3b5-3f9cdeb53981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825235913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.825235913
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2764672348
Short name T115
Test name
Test status
Simulation time 498886756591 ps
CPU time 1065.38 seconds
Started May 09 02:51:33 PM PDT 24
Finished May 09 03:09:21 PM PDT 24
Peak memory 202360 kb
Host smart-66f18a5f-077f-46d2-891f-f2c26b4a504a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764672348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2764672348
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2815501975
Short name T581
Test name
Test status
Simulation time 168385859239 ps
CPU time 93.64 seconds
Started May 09 02:51:27 PM PDT 24
Finished May 09 02:53:04 PM PDT 24
Peak memory 202344 kb
Host smart-ab951c19-faf9-46f5-a393-8a1422a8a9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815501975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2815501975
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1779728155
Short name T399
Test name
Test status
Simulation time 485170839491 ps
CPU time 527.12 seconds
Started May 09 02:51:31 PM PDT 24
Finished May 09 03:00:22 PM PDT 24
Peak memory 202256 kb
Host smart-502257f9-aac5-4c89-9826-d141ea6865db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779728155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1779728155
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.4265648416
Short name T496
Test name
Test status
Simulation time 162433208955 ps
CPU time 23.5 seconds
Started May 09 02:51:33 PM PDT 24
Finished May 09 02:52:00 PM PDT 24
Peak memory 202300 kb
Host smart-4ee20ae6-5e64-4440-a649-e6564592c73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265648416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.4265648416
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2672033649
Short name T518
Test name
Test status
Simulation time 158962768434 ps
CPU time 269.73 seconds
Started May 09 02:51:33 PM PDT 24
Finished May 09 02:56:05 PM PDT 24
Peak memory 202360 kb
Host smart-ab5ac19f-5825-453c-8d98-f4b8c18c8f9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672033649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2672033649
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1439449927
Short name T251
Test name
Test status
Simulation time 349282218604 ps
CPU time 807.31 seconds
Started May 09 02:51:32 PM PDT 24
Finished May 09 03:05:03 PM PDT 24
Peak memory 202448 kb
Host smart-80c357c5-2864-4340-8b20-4eb9689c866d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439449927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1439449927
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.406930738
Short name T672
Test name
Test status
Simulation time 209334928709 ps
CPU time 369.73 seconds
Started May 09 02:51:31 PM PDT 24
Finished May 09 02:57:44 PM PDT 24
Peak memory 202264 kb
Host smart-3c834e0b-a4a1-4a5b-a794-54946b48a359
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406930738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.406930738
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.190715038
Short name T351
Test name
Test status
Simulation time 90945945685 ps
CPU time 322.79 seconds
Started May 09 02:51:33 PM PDT 24
Finished May 09 02:56:59 PM PDT 24
Peak memory 202728 kb
Host smart-fc6aad08-495a-4ce4-ad10-cfe30c437209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190715038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.190715038
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1921014927
Short name T650
Test name
Test status
Simulation time 44856602880 ps
CPU time 25.73 seconds
Started May 09 02:51:32 PM PDT 24
Finished May 09 02:52:01 PM PDT 24
Peak memory 202140 kb
Host smart-33a8428c-6402-4203-8972-aa8cb00a5d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921014927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1921014927
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3167807070
Short name T460
Test name
Test status
Simulation time 3590811850 ps
CPU time 2.64 seconds
Started May 09 02:51:33 PM PDT 24
Finished May 09 02:51:38 PM PDT 24
Peak memory 202136 kb
Host smart-57d4c804-92c3-47b0-a3d6-b8e6bb709f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167807070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3167807070
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2342815006
Short name T775
Test name
Test status
Simulation time 5989296215 ps
CPU time 4.63 seconds
Started May 09 02:51:28 PM PDT 24
Finished May 09 02:51:36 PM PDT 24
Peak memory 202132 kb
Host smart-9268cfeb-5570-4fe9-8f0d-d84e04947774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342815006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2342815006
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2510783309
Short name T384
Test name
Test status
Simulation time 172476434429 ps
CPU time 80 seconds
Started May 09 02:51:33 PM PDT 24
Finished May 09 02:52:56 PM PDT 24
Peak memory 202304 kb
Host smart-72a04e36-3cb7-4211-9176-6987b57e14a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510783309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2510783309
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.815813284
Short name T280
Test name
Test status
Simulation time 23160027833 ps
CPU time 58.09 seconds
Started May 09 02:51:33 PM PDT 24
Finished May 09 02:52:34 PM PDT 24
Peak memory 210976 kb
Host smart-95fd9239-b368-4243-b788-19110b58b5b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815813284 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.815813284
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4013497150
Short name T466
Test name
Test status
Simulation time 327831994 ps
CPU time 0.79 seconds
Started May 09 02:51:33 PM PDT 24
Finished May 09 02:51:37 PM PDT 24
Peak memory 201948 kb
Host smart-1acdd6fb-7048-4442-bade-bde84730057a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013497150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4013497150
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3491233804
Short name T190
Test name
Test status
Simulation time 376079123567 ps
CPU time 184.35 seconds
Started May 09 02:51:30 PM PDT 24
Finished May 09 02:54:38 PM PDT 24
Peak memory 202448 kb
Host smart-1d401a30-1db7-47f4-bf70-149d9e00e3bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491233804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3491233804
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.963163369
Short name T756
Test name
Test status
Simulation time 496094849833 ps
CPU time 304.77 seconds
Started May 09 02:51:33 PM PDT 24
Finished May 09 02:56:41 PM PDT 24
Peak memory 202244 kb
Host smart-9bc4727d-f6e8-4629-baab-c93087dd1cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963163369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.963163369
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3626449285
Short name T29
Test name
Test status
Simulation time 168676793645 ps
CPU time 369.5 seconds
Started May 09 02:51:36 PM PDT 24
Finished May 09 02:57:47 PM PDT 24
Peak memory 202324 kb
Host smart-c94784b9-93f0-49b6-98b3-e0d4a57fa87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626449285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3626449285
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1180258795
Short name T624
Test name
Test status
Simulation time 161282725566 ps
CPU time 194.89 seconds
Started May 09 02:51:30 PM PDT 24
Finished May 09 02:54:49 PM PDT 24
Peak memory 202300 kb
Host smart-e22c586d-b952-4dae-9813-4bf8b6e72336
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180258795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1180258795
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.348078094
Short name T445
Test name
Test status
Simulation time 497314571359 ps
CPU time 1132.28 seconds
Started May 09 02:51:32 PM PDT 24
Finished May 09 03:10:28 PM PDT 24
Peak memory 202332 kb
Host smart-7136f67c-714e-4ed8-a70a-712adc3fd557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348078094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.348078094
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1221128724
Short name T599
Test name
Test status
Simulation time 159598900053 ps
CPU time 376.47 seconds
Started May 09 02:51:30 PM PDT 24
Finished May 09 02:57:51 PM PDT 24
Peak memory 202316 kb
Host smart-bc86ce3a-59d2-4eed-96ee-393a23f413cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221128724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1221128724
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1994667736
Short name T728
Test name
Test status
Simulation time 178550952881 ps
CPU time 414.17 seconds
Started May 09 02:51:30 PM PDT 24
Finished May 09 02:58:28 PM PDT 24
Peak memory 202368 kb
Host smart-04f013b4-ef73-4871-b24c-19c1b099048d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994667736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1994667736
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.237150107
Short name T595
Test name
Test status
Simulation time 610420850260 ps
CPU time 717.73 seconds
Started May 09 02:51:35 PM PDT 24
Finished May 09 03:03:35 PM PDT 24
Peak memory 202308 kb
Host smart-50024761-9ae8-471d-8b9e-8f959683aa76
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237150107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.237150107
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1124083744
Short name T215
Test name
Test status
Simulation time 123442227227 ps
CPU time 438.01 seconds
Started May 09 02:51:35 PM PDT 24
Finished May 09 02:58:55 PM PDT 24
Peak memory 202756 kb
Host smart-3a823115-dd68-446a-8745-f82a7c903a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124083744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1124083744
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.673352735
Short name T101
Test name
Test status
Simulation time 37684602522 ps
CPU time 90.06 seconds
Started May 09 02:51:33 PM PDT 24
Finished May 09 02:53:06 PM PDT 24
Peak memory 202068 kb
Host smart-6746e030-6a0f-4d16-8a46-48e147654522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673352735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.673352735
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3326075278
Short name T623
Test name
Test status
Simulation time 4168908520 ps
CPU time 10.48 seconds
Started May 09 02:51:36 PM PDT 24
Finished May 09 02:51:48 PM PDT 24
Peak memory 202156 kb
Host smart-ede1fecb-21a6-4e46-b5a4-328ea05db6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326075278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3326075278
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2727680393
Short name T526
Test name
Test status
Simulation time 6022825534 ps
CPU time 14.33 seconds
Started May 09 02:51:30 PM PDT 24
Finished May 09 02:51:49 PM PDT 24
Peak memory 202136 kb
Host smart-70a2b8d0-e8ec-4732-a6c5-9daf034659a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727680393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2727680393
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3948866965
Short name T196
Test name
Test status
Simulation time 195453447488 ps
CPU time 212.8 seconds
Started May 09 02:51:36 PM PDT 24
Finished May 09 02:55:11 PM PDT 24
Peak memory 202400 kb
Host smart-e62ade9c-e281-4445-88eb-06bdd973f34a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948866965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3948866965
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3389489281
Short name T42
Test name
Test status
Simulation time 304793994 ps
CPU time 1.31 seconds
Started May 09 02:51:37 PM PDT 24
Finished May 09 02:51:40 PM PDT 24
Peak memory 202032 kb
Host smart-ebc3d63a-51a1-4523-b812-28afbacb8b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389489281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3389489281
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1236957442
Short name T667
Test name
Test status
Simulation time 598884040229 ps
CPU time 351.41 seconds
Started May 09 02:51:50 PM PDT 24
Finished May 09 02:57:45 PM PDT 24
Peak memory 202104 kb
Host smart-730a0d3a-c656-440a-8e48-4493b21f8e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236957442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1236957442
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.363644781
Short name T719
Test name
Test status
Simulation time 488733832418 ps
CPU time 272.66 seconds
Started May 09 02:51:31 PM PDT 24
Finished May 09 02:56:07 PM PDT 24
Peak memory 202300 kb
Host smart-b0100d25-c17e-46af-a121-c956fe34a8e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=363644781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.363644781
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.4285884069
Short name T285
Test name
Test status
Simulation time 483434653134 ps
CPU time 1135.82 seconds
Started May 09 02:51:30 PM PDT 24
Finished May 09 03:10:30 PM PDT 24
Peak memory 202248 kb
Host smart-4ac77780-a34c-4210-b6ee-810ca5050861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285884069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.4285884069
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2143268696
Short name T397
Test name
Test status
Simulation time 501721974498 ps
CPU time 450.71 seconds
Started May 09 02:51:36 PM PDT 24
Finished May 09 02:59:08 PM PDT 24
Peak memory 202308 kb
Host smart-152e0cf5-ac86-4e48-8b0f-d9718a2156ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143268696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2143268696
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3611598093
Short name T633
Test name
Test status
Simulation time 196079168095 ps
CPU time 212.2 seconds
Started May 09 02:51:37 PM PDT 24
Finished May 09 02:55:11 PM PDT 24
Peak memory 202336 kb
Host smart-a97c19a1-5d7e-4118-af07-2c6a6676d9a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611598093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3611598093
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3667249358
Short name T457
Test name
Test status
Simulation time 113429532052 ps
CPU time 387.52 seconds
Started May 09 02:51:51 PM PDT 24
Finished May 09 02:58:22 PM PDT 24
Peak memory 202660 kb
Host smart-09ef9d31-ed86-461b-ac8f-c5be45281aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667249358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3667249358
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.4154063768
Short name T777
Test name
Test status
Simulation time 31403083074 ps
CPU time 70 seconds
Started May 09 02:51:37 PM PDT 24
Finished May 09 02:52:49 PM PDT 24
Peak memory 202164 kb
Host smart-10267f45-d79a-4ae2-a88c-f35a3b75f9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154063768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.4154063768
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3698698862
Short name T359
Test name
Test status
Simulation time 3674482124 ps
CPU time 9.54 seconds
Started May 09 02:51:49 PM PDT 24
Finished May 09 02:52:01 PM PDT 24
Peak memory 202148 kb
Host smart-e32fd279-7d08-406a-9879-44cd2c396f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698698862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3698698862
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3389531880
Short name T625
Test name
Test status
Simulation time 6120437821 ps
CPU time 7.58 seconds
Started May 09 02:51:33 PM PDT 24
Finished May 09 02:51:43 PM PDT 24
Peak memory 202080 kb
Host smart-0f1b8f6f-454b-421d-b481-8b7650421478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389531880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3389531880
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3926042477
Short name T162
Test name
Test status
Simulation time 327372784061 ps
CPU time 125.9 seconds
Started May 09 02:51:37 PM PDT 24
Finished May 09 02:53:45 PM PDT 24
Peak memory 202356 kb
Host smart-0ef21e31-a60f-4aef-9225-003e57ce4ce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926042477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3926042477
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.55946011
Short name T52
Test name
Test status
Simulation time 40904504166 ps
CPU time 88.36 seconds
Started May 09 02:51:48 PM PDT 24
Finished May 09 02:53:20 PM PDT 24
Peak memory 211012 kb
Host smart-e5887890-51fd-4109-87f4-2890d0ec93bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55946011 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.55946011
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.4119851204
Short name T643
Test name
Test status
Simulation time 300358002 ps
CPU time 1.3 seconds
Started May 09 02:51:49 PM PDT 24
Finished May 09 02:51:53 PM PDT 24
Peak memory 202048 kb
Host smart-45362821-a98e-4cae-ad7f-d52a6367ed51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119851204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.4119851204
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3839530863
Short name T268
Test name
Test status
Simulation time 486308511567 ps
CPU time 292.7 seconds
Started May 09 02:51:45 PM PDT 24
Finished May 09 02:56:38 PM PDT 24
Peak memory 202360 kb
Host smart-eda94e98-4069-4af5-a1d5-c4638ae22767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839530863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3839530863
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3926745407
Short name T286
Test name
Test status
Simulation time 494597390744 ps
CPU time 648.19 seconds
Started May 09 02:51:42 PM PDT 24
Finished May 09 03:02:31 PM PDT 24
Peak memory 202336 kb
Host smart-45555b27-0793-4d26-8be7-b4e4fbf2fd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926745407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3926745407
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.515406790
Short name T602
Test name
Test status
Simulation time 500240348466 ps
CPU time 275.47 seconds
Started May 09 02:51:51 PM PDT 24
Finished May 09 02:56:30 PM PDT 24
Peak memory 202292 kb
Host smart-a0077ea0-c01d-4827-9028-674e10ead8e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=515406790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.515406790
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3133567218
Short name T622
Test name
Test status
Simulation time 492693719618 ps
CPU time 1199.53 seconds
Started May 09 02:51:47 PM PDT 24
Finished May 09 03:11:49 PM PDT 24
Peak memory 202308 kb
Host smart-d40ad37d-2124-427b-8325-4432d10d11e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133567218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3133567218
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.188815852
Short name T340
Test name
Test status
Simulation time 530427947281 ps
CPU time 659.97 seconds
Started May 09 02:51:50 PM PDT 24
Finished May 09 03:02:53 PM PDT 24
Peak memory 202376 kb
Host smart-3aeda38a-eabe-4acb-bfa5-1869dbefefd9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188815852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.188815852
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1820962452
Short name T55
Test name
Test status
Simulation time 384966317271 ps
CPU time 452.88 seconds
Started May 09 02:51:39 PM PDT 24
Finished May 09 02:59:13 PM PDT 24
Peak memory 202308 kb
Host smart-17fcd0e7-adf1-4983-9971-90d1ec301b3b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820962452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1820962452
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1101166793
Short name T345
Test name
Test status
Simulation time 88734532659 ps
CPU time 449.2 seconds
Started May 09 02:51:39 PM PDT 24
Finished May 09 02:59:10 PM PDT 24
Peak memory 202684 kb
Host smart-0d8ecc43-ee34-4ca0-a30f-dcc23548ec95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101166793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1101166793
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1011668429
Short name T175
Test name
Test status
Simulation time 31761656482 ps
CPU time 71.75 seconds
Started May 09 02:51:45 PM PDT 24
Finished May 09 02:52:58 PM PDT 24
Peak memory 202160 kb
Host smart-745d9089-2e34-47c8-8434-aa484f913f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011668429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1011668429
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3647757040
Short name T425
Test name
Test status
Simulation time 3747639567 ps
CPU time 2.97 seconds
Started May 09 02:51:46 PM PDT 24
Finished May 09 02:51:51 PM PDT 24
Peak memory 202176 kb
Host smart-db1a7e57-bf87-49f2-a347-aa20940adcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647757040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3647757040
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3802344173
Short name T484
Test name
Test status
Simulation time 5549637039 ps
CPU time 4 seconds
Started May 09 02:51:36 PM PDT 24
Finished May 09 02:51:42 PM PDT 24
Peak memory 202132 kb
Host smart-a21bae0c-fb4d-4b24-ab89-accd39467fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802344173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3802344173
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1680856930
Short name T151
Test name
Test status
Simulation time 428922137466 ps
CPU time 352.97 seconds
Started May 09 02:51:46 PM PDT 24
Finished May 09 02:57:41 PM PDT 24
Peak memory 202780 kb
Host smart-d4b6ad27-8361-4c83-888f-9734c119e06d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680856930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1680856930
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.256412512
Short name T79
Test name
Test status
Simulation time 507984013 ps
CPU time 1.19 seconds
Started May 09 02:51:46 PM PDT 24
Finished May 09 02:51:49 PM PDT 24
Peak memory 202008 kb
Host smart-b3e6a990-d470-4325-8d4c-c0e83a1d13af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256412512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.256412512
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.636613335
Short name T150
Test name
Test status
Simulation time 490984951951 ps
CPU time 893.91 seconds
Started May 09 02:51:38 PM PDT 24
Finished May 09 03:06:34 PM PDT 24
Peak memory 202320 kb
Host smart-4c9146f3-80cd-4343-ac43-6bc876f22f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636613335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.636613335
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.394970506
Short name T656
Test name
Test status
Simulation time 169150439764 ps
CPU time 102.61 seconds
Started May 09 02:51:37 PM PDT 24
Finished May 09 02:53:21 PM PDT 24
Peak memory 202348 kb
Host smart-35e6e26d-c97e-4f36-af1e-f4f366141e32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=394970506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.394970506
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.826290208
Short name T93
Test name
Test status
Simulation time 164646625485 ps
CPU time 103.1 seconds
Started May 09 02:51:49 PM PDT 24
Finished May 09 02:53:35 PM PDT 24
Peak memory 202344 kb
Host smart-163e2fab-b58a-4773-8d0c-854768637242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826290208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.826290208
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.4098386483
Short name T520
Test name
Test status
Simulation time 481835210504 ps
CPU time 1159.95 seconds
Started May 09 02:51:49 PM PDT 24
Finished May 09 03:11:12 PM PDT 24
Peak memory 202400 kb
Host smart-3e03eab3-e147-4309-94d3-bc3c65fa7a81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098386483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.4098386483
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.652183442
Short name T537
Test name
Test status
Simulation time 165454444463 ps
CPU time 415 seconds
Started May 09 02:51:49 PM PDT 24
Finished May 09 02:58:47 PM PDT 24
Peak memory 202420 kb
Host smart-2f8ccf0a-256e-48c1-81ff-2dc7e8c94dbd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652183442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.652183442
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1868242870
Short name T765
Test name
Test status
Simulation time 400574889803 ps
CPU time 227.97 seconds
Started May 09 02:51:50 PM PDT 24
Finished May 09 02:55:41 PM PDT 24
Peak memory 202148 kb
Host smart-f05e16e1-7e5d-4b33-86d6-abc00d1609e6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868242870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1868242870
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1753031679
Short name T116
Test name
Test status
Simulation time 132474856533 ps
CPU time 446.69 seconds
Started May 09 02:51:40 PM PDT 24
Finished May 09 02:59:08 PM PDT 24
Peak memory 202696 kb
Host smart-a3c5a070-c5ab-4b69-9c95-728e424f7f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753031679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1753031679
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2746338375
Short name T174
Test name
Test status
Simulation time 37727121751 ps
CPU time 42.16 seconds
Started May 09 02:51:46 PM PDT 24
Finished May 09 02:52:30 PM PDT 24
Peak memory 202164 kb
Host smart-44f33d98-a61c-453f-b1b3-2ff70469a412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746338375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2746338375
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.659425680
Short name T375
Test name
Test status
Simulation time 4442036833 ps
CPU time 10.37 seconds
Started May 09 02:51:46 PM PDT 24
Finished May 09 02:51:57 PM PDT 24
Peak memory 202176 kb
Host smart-57c15fc4-c0e7-477f-921f-ee87d49955e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659425680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.659425680
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3379336613
Short name T571
Test name
Test status
Simulation time 6004848075 ps
CPU time 4.99 seconds
Started May 09 02:51:44 PM PDT 24
Finished May 09 02:51:50 PM PDT 24
Peak memory 202120 kb
Host smart-ac6c22f7-9919-498b-984a-a2f724b9843c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379336613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3379336613
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.299373599
Short name T155
Test name
Test status
Simulation time 493736891573 ps
CPU time 1101.42 seconds
Started May 09 02:51:51 PM PDT 24
Finished May 09 03:10:16 PM PDT 24
Peak memory 202296 kb
Host smart-d633b4d3-b148-4860-9a01-a0ccb2f9c86d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299373599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
299373599
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2405897274
Short name T754
Test name
Test status
Simulation time 184682875068 ps
CPU time 82.61 seconds
Started May 09 02:51:54 PM PDT 24
Finished May 09 02:53:19 PM PDT 24
Peak memory 211092 kb
Host smart-2cf2c8f9-2a0f-4990-a5fb-b27fd894248e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405897274 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2405897274
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2228085189
Short name T442
Test name
Test status
Simulation time 359781364 ps
CPU time 1.07 seconds
Started May 09 02:51:45 PM PDT 24
Finished May 09 02:51:47 PM PDT 24
Peak memory 202036 kb
Host smart-1c9e8421-5ff5-40fe-8818-14c0fe8453ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228085189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2228085189
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1612013613
Short name T330
Test name
Test status
Simulation time 358426089705 ps
CPU time 830.93 seconds
Started May 09 02:51:49 PM PDT 24
Finished May 09 03:05:43 PM PDT 24
Peak memory 202420 kb
Host smart-5e80f726-d6ad-4d42-bf33-bd9c2099cfbf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612013613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1612013613
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3027267174
Short name T668
Test name
Test status
Simulation time 157849675600 ps
CPU time 110.03 seconds
Started May 09 02:51:47 PM PDT 24
Finished May 09 02:53:40 PM PDT 24
Peak memory 202328 kb
Host smart-d9ed39c9-e08e-45a1-a1ac-67101a40d225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027267174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3027267174
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3941078741
Short name T210
Test name
Test status
Simulation time 490661052142 ps
CPU time 242.78 seconds
Started May 09 02:51:42 PM PDT 24
Finished May 09 02:55:46 PM PDT 24
Peak memory 202388 kb
Host smart-7c492fe1-96b0-4b97-bead-ccc7ee8c63a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941078741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3941078741
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2798803895
Short name T780
Test name
Test status
Simulation time 496185466499 ps
CPU time 272.82 seconds
Started May 09 02:51:41 PM PDT 24
Finished May 09 02:56:15 PM PDT 24
Peak memory 202320 kb
Host smart-585b086d-9cbd-4b5f-84d4-bd12904c733e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798803895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2798803895
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.775875712
Short name T546
Test name
Test status
Simulation time 162122651177 ps
CPU time 373.84 seconds
Started May 09 02:51:47 PM PDT 24
Finished May 09 02:58:04 PM PDT 24
Peak memory 202308 kb
Host smart-905f844d-5fd2-4ef8-8be3-dd780b86a17d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=775875712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.775875712
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2345493993
Short name T165
Test name
Test status
Simulation time 616129581432 ps
CPU time 357.11 seconds
Started May 09 02:51:37 PM PDT 24
Finished May 09 02:57:36 PM PDT 24
Peak memory 202628 kb
Host smart-5eb2ec9c-104f-4e4f-b8c6-bb4ba2151ba0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345493993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2345493993
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2316682195
Short name T778
Test name
Test status
Simulation time 209895294479 ps
CPU time 259.97 seconds
Started May 09 02:51:38 PM PDT 24
Finished May 09 02:55:59 PM PDT 24
Peak memory 202292 kb
Host smart-12e99c16-0ed0-4fbe-a855-ac7db6b07546
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316682195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2316682195
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2792773076
Short name T661
Test name
Test status
Simulation time 81229414019 ps
CPU time 392.48 seconds
Started May 09 02:51:47 PM PDT 24
Finished May 09 02:58:22 PM PDT 24
Peak memory 202628 kb
Host smart-b8b4f0fb-9431-4738-aaa0-9d9a970737d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792773076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2792773076
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2552633315
Short name T711
Test name
Test status
Simulation time 35920752118 ps
CPU time 41.76 seconds
Started May 09 02:51:48 PM PDT 24
Finished May 09 02:52:33 PM PDT 24
Peak memory 202172 kb
Host smart-073e21a8-9398-4889-b00c-526c360e0045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552633315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2552633315
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1918725296
Short name T603
Test name
Test status
Simulation time 4381166862 ps
CPU time 9.93 seconds
Started May 09 02:51:49 PM PDT 24
Finished May 09 02:52:02 PM PDT 24
Peak memory 202168 kb
Host smart-353c77e0-60bf-4089-a5e4-224153a3c8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918725296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1918725296
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1172371420
Short name T527
Test name
Test status
Simulation time 5576139735 ps
CPU time 7.08 seconds
Started May 09 02:51:45 PM PDT 24
Finished May 09 02:51:53 PM PDT 24
Peak memory 202172 kb
Host smart-46f30d11-3a35-4c9a-8b30-ad1bdc08a7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172371420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1172371420
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3642695801
Short name T637
Test name
Test status
Simulation time 377114723935 ps
CPU time 457.48 seconds
Started May 09 02:51:54 PM PDT 24
Finished May 09 02:59:34 PM PDT 24
Peak memory 202412 kb
Host smart-3d095ed3-dc9e-40e6-aed6-c3799d6967c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642695801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3642695801
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1674736146
Short name T734
Test name
Test status
Simulation time 251540854106 ps
CPU time 225.57 seconds
Started May 09 02:51:51 PM PDT 24
Finished May 09 02:55:40 PM PDT 24
Peak memory 210964 kb
Host smart-6246f958-ee66-4ce4-8cb0-dc0835eb7acf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674736146 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1674736146
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1107043516
Short name T472
Test name
Test status
Simulation time 480025457 ps
CPU time 0.89 seconds
Started May 09 02:51:41 PM PDT 24
Finished May 09 02:51:43 PM PDT 24
Peak memory 202016 kb
Host smart-915c9450-0212-4711-accd-c4fd69023fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107043516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1107043516
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2729361522
Short name T208
Test name
Test status
Simulation time 330087969043 ps
CPU time 141.54 seconds
Started May 09 02:51:54 PM PDT 24
Finished May 09 02:54:18 PM PDT 24
Peak memory 202204 kb
Host smart-534f6316-70d7-4f50-b1d7-3c8ff8160bb0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729361522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2729361522
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1582014389
Short name T323
Test name
Test status
Simulation time 161328998216 ps
CPU time 186.26 seconds
Started May 09 02:51:46 PM PDT 24
Finished May 09 02:54:53 PM PDT 24
Peak memory 202300 kb
Host smart-cfa38e57-e249-4916-afd6-29d2b26ebf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582014389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1582014389
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.620443744
Short name T146
Test name
Test status
Simulation time 490552699658 ps
CPU time 1201.12 seconds
Started May 09 02:51:44 PM PDT 24
Finished May 09 03:11:47 PM PDT 24
Peak memory 202292 kb
Host smart-b4e3cc19-2285-4fa8-895b-05c0bd177422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620443744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.620443744
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.4000643012
Short name T486
Test name
Test status
Simulation time 326983583287 ps
CPU time 758.24 seconds
Started May 09 02:51:53 PM PDT 24
Finished May 09 03:04:34 PM PDT 24
Peak memory 202332 kb
Host smart-d6e261d9-aaa4-4f0e-b938-ff3972824f8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000643012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.4000643012
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1801274453
Short name T168
Test name
Test status
Simulation time 499608907094 ps
CPU time 196.19 seconds
Started May 09 02:51:51 PM PDT 24
Finished May 09 02:55:10 PM PDT 24
Peak memory 202300 kb
Host smart-17da6494-14e0-43ed-a549-2e7b0e153e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801274453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1801274453
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1628493494
Short name T381
Test name
Test status
Simulation time 494826640444 ps
CPU time 1198.11 seconds
Started May 09 02:51:53 PM PDT 24
Finished May 09 03:11:54 PM PDT 24
Peak memory 202324 kb
Host smart-a414b143-9684-45ab-acbc-4d64b8747fd6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628493494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1628493494
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2374420539
Short name T644
Test name
Test status
Simulation time 590762644558 ps
CPU time 1235.4 seconds
Started May 09 02:51:47 PM PDT 24
Finished May 09 03:12:25 PM PDT 24
Peak memory 202288 kb
Host smart-5938993f-5cee-43fa-83aa-0e4caf4d05db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374420539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2374420539
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2774504283
Short name T767
Test name
Test status
Simulation time 608386401458 ps
CPU time 403.27 seconds
Started May 09 02:51:53 PM PDT 24
Finished May 09 02:58:39 PM PDT 24
Peak memory 202320 kb
Host smart-3ecbcd21-39c2-4228-b232-505782305a37
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774504283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2774504283
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3758003423
Short name T89
Test name
Test status
Simulation time 79533408340 ps
CPU time 288.13 seconds
Started May 09 02:51:53 PM PDT 24
Finished May 09 02:56:44 PM PDT 24
Peak memory 202700 kb
Host smart-8edcafa3-fd26-4d9f-999a-34b69bbea9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758003423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3758003423
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1841567568
Short name T398
Test name
Test status
Simulation time 27269278748 ps
CPU time 22.97 seconds
Started May 09 02:51:38 PM PDT 24
Finished May 09 02:52:03 PM PDT 24
Peak memory 202160 kb
Host smart-0a5d18a3-9414-4e09-a603-4ba1772d1464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841567568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1841567568
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2005520017
Short name T54
Test name
Test status
Simulation time 3637134395 ps
CPU time 5.24 seconds
Started May 09 02:51:54 PM PDT 24
Finished May 09 02:52:02 PM PDT 24
Peak memory 202156 kb
Host smart-28ff1e21-7d15-4b78-94bc-b4313700993e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005520017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2005520017
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.926838603
Short name T762
Test name
Test status
Simulation time 6110043042 ps
CPU time 3.94 seconds
Started May 09 02:51:50 PM PDT 24
Finished May 09 02:51:57 PM PDT 24
Peak memory 202128 kb
Host smart-a2f769b1-21a1-4799-b1f4-9753c58043b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926838603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.926838603
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.100189027
Short name T772
Test name
Test status
Simulation time 25643870937 ps
CPU time 29.53 seconds
Started May 09 02:51:47 PM PDT 24
Finished May 09 02:52:18 PM PDT 24
Peak memory 210656 kb
Host smart-0a59725a-dc03-4fbc-8d9d-1e5fd3814382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100189027 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.100189027
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2801311681
Short name T740
Test name
Test status
Simulation time 394469035 ps
CPU time 0.82 seconds
Started May 09 02:51:48 PM PDT 24
Finished May 09 02:51:52 PM PDT 24
Peak memory 202064 kb
Host smart-61ced38b-dda3-4aae-ae3e-c55b44d3fd13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801311681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2801311681
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1231650116
Short name T559
Test name
Test status
Simulation time 359830558698 ps
CPU time 447.92 seconds
Started May 09 02:51:48 PM PDT 24
Finished May 09 02:59:19 PM PDT 24
Peak memory 202376 kb
Host smart-3bbed50b-c6eb-43dc-81c7-c3985f2b7283
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231650116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1231650116
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3246505014
Short name T747
Test name
Test status
Simulation time 326205560031 ps
CPU time 134.7 seconds
Started May 09 02:51:46 PM PDT 24
Finished May 09 02:54:02 PM PDT 24
Peak memory 202308 kb
Host smart-f418b1d1-c885-488d-83d6-bc63e39d44e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246505014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3246505014
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.4168290325
Short name T403
Test name
Test status
Simulation time 165307680900 ps
CPU time 68.38 seconds
Started May 09 02:51:48 PM PDT 24
Finished May 09 02:52:59 PM PDT 24
Peak memory 202288 kb
Host smart-dc34c2be-5f07-431b-b652-127da18d251e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168290325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.4168290325
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2532557461
Short name T335
Test name
Test status
Simulation time 491588523689 ps
CPU time 517.77 seconds
Started May 09 02:51:54 PM PDT 24
Finished May 09 03:00:34 PM PDT 24
Peak memory 202176 kb
Host smart-b06e120d-3c04-4107-b8d6-1c56ac85d08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532557461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2532557461
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.879995454
Short name T378
Test name
Test status
Simulation time 496897134649 ps
CPU time 1244.4 seconds
Started May 09 02:51:43 PM PDT 24
Finished May 09 03:12:29 PM PDT 24
Peak memory 202256 kb
Host smart-604fc3ec-fb80-4996-ac56-43d932c92de8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=879995454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.879995454
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3720501985
Short name T45
Test name
Test status
Simulation time 563394467601 ps
CPU time 1121.16 seconds
Started May 09 02:51:48 PM PDT 24
Finished May 09 03:10:32 PM PDT 24
Peak memory 202376 kb
Host smart-9557fd3b-3e6d-47a4-adf7-e1a3bb7b3089
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720501985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3720501985
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1379734299
Short name T452
Test name
Test status
Simulation time 400358030311 ps
CPU time 250.3 seconds
Started May 09 02:51:43 PM PDT 24
Finished May 09 02:55:55 PM PDT 24
Peak memory 202264 kb
Host smart-5b5fd6bf-c592-43bf-8563-53df15d46c0f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379734299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1379734299
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.681744689
Short name T57
Test name
Test status
Simulation time 67588154739 ps
CPU time 278.4 seconds
Started May 09 02:51:47 PM PDT 24
Finished May 09 02:56:28 PM PDT 24
Peak memory 202652 kb
Host smart-2a65deba-82de-4e96-b400-28a81d700930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681744689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.681744689
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1538984006
Short name T204
Test name
Test status
Simulation time 28012649930 ps
CPU time 33.03 seconds
Started May 09 02:51:43 PM PDT 24
Finished May 09 02:52:17 PM PDT 24
Peak memory 202108 kb
Host smart-36b75c1c-0769-4043-83ca-7c9eb2f6caec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538984006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1538984006
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.429120554
Short name T448
Test name
Test status
Simulation time 4728008358 ps
CPU time 6.62 seconds
Started May 09 02:51:48 PM PDT 24
Finished May 09 02:51:57 PM PDT 24
Peak memory 202132 kb
Host smart-9d4b03be-ec69-4d00-8284-c02d7e7ac841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429120554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.429120554
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1288848470
Short name T657
Test name
Test status
Simulation time 6019858807 ps
CPU time 4.5 seconds
Started May 09 02:51:53 PM PDT 24
Finished May 09 02:52:00 PM PDT 24
Peak memory 202120 kb
Host smart-79025f8d-68a1-4f2c-9ccc-e258c5c9fbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288848470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1288848470
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1230356126
Short name T236
Test name
Test status
Simulation time 371117361381 ps
CPU time 213.19 seconds
Started May 09 02:51:58 PM PDT 24
Finished May 09 02:55:32 PM PDT 24
Peak memory 202408 kb
Host smart-7d73ba7a-cdab-48e0-97ae-ba4b56f32a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230356126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1230356126
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3370356196
Short name T291
Test name
Test status
Simulation time 39099473937 ps
CPU time 94.66 seconds
Started May 09 02:51:47 PM PDT 24
Finished May 09 02:53:25 PM PDT 24
Peak memory 210676 kb
Host smart-5661cd61-de79-419a-a346-6f56913b2ee0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370356196 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3370356196
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.508004768
Short name T541
Test name
Test status
Simulation time 312609000 ps
CPU time 1.24 seconds
Started May 09 02:51:57 PM PDT 24
Finished May 09 02:51:59 PM PDT 24
Peak memory 202036 kb
Host smart-3ca77b30-bc82-4be8-9d4d-c928ba2434ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508004768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.508004768
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1962208341
Short name T247
Test name
Test status
Simulation time 325559741849 ps
CPU time 478.93 seconds
Started May 09 02:51:51 PM PDT 24
Finished May 09 02:59:53 PM PDT 24
Peak memory 202380 kb
Host smart-5f1c4c32-ae0b-4e34-9d40-2230738abbbf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962208341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1962208341
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2438757864
Short name T310
Test name
Test status
Simulation time 506650137536 ps
CPU time 1127.47 seconds
Started May 09 02:51:53 PM PDT 24
Finished May 09 03:10:43 PM PDT 24
Peak memory 202344 kb
Host smart-98ed4754-aa14-4070-b053-9f02ad2897b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438757864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2438757864
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2830230958
Short name T769
Test name
Test status
Simulation time 328456921591 ps
CPU time 484.53 seconds
Started May 09 02:51:57 PM PDT 24
Finished May 09 03:00:03 PM PDT 24
Peak memory 202336 kb
Host smart-d47efe2e-3b2d-48d0-b43f-0e7235087d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830230958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2830230958
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.731973203
Short name T557
Test name
Test status
Simulation time 481368081618 ps
CPU time 295.39 seconds
Started May 09 02:51:50 PM PDT 24
Finished May 09 02:56:48 PM PDT 24
Peak memory 202316 kb
Host smart-f631bdf3-a19a-4f35-a78b-6c075c0346fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=731973203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.731973203
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1728490239
Short name T203
Test name
Test status
Simulation time 495091991622 ps
CPU time 183.2 seconds
Started May 09 02:51:49 PM PDT 24
Finished May 09 02:54:55 PM PDT 24
Peak memory 202348 kb
Host smart-5b24425b-53ed-4f94-b73b-dc0b7b305a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728490239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1728490239
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3912297728
Short name T796
Test name
Test status
Simulation time 164359931824 ps
CPU time 360.66 seconds
Started May 09 02:51:48 PM PDT 24
Finished May 09 02:57:52 PM PDT 24
Peak memory 202300 kb
Host smart-13a3f7a8-8a4e-4078-bbe1-d8ba3ef2bedd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912297728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3912297728
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2202755847
Short name T90
Test name
Test status
Simulation time 536002814329 ps
CPU time 417.75 seconds
Started May 09 02:51:52 PM PDT 24
Finished May 09 02:58:52 PM PDT 24
Peak memory 202256 kb
Host smart-9b0e0dbb-5100-4ff4-b474-5cfc7d05e3c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202755847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2202755847
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1105100663
Short name T205
Test name
Test status
Simulation time 397705597517 ps
CPU time 274.16 seconds
Started May 09 02:51:54 PM PDT 24
Finished May 09 02:56:30 PM PDT 24
Peak memory 202268 kb
Host smart-f6138d97-1d46-4cac-ac45-d35dba6f2558
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105100663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1105100663
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1366414511
Short name T786
Test name
Test status
Simulation time 65837873882 ps
CPU time 346.55 seconds
Started May 09 02:51:56 PM PDT 24
Finished May 09 02:57:45 PM PDT 24
Peak memory 202692 kb
Host smart-76bf4454-779f-4868-88e9-871d073a4f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366414511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1366414511
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.533440644
Short name T31
Test name
Test status
Simulation time 23806857452 ps
CPU time 52.94 seconds
Started May 09 02:51:49 PM PDT 24
Finished May 09 02:52:45 PM PDT 24
Peak memory 202148 kb
Host smart-6442a40d-7bf7-4843-bdfb-fffd4543ae33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533440644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.533440644
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.613646407
Short name T492
Test name
Test status
Simulation time 5270024832 ps
CPU time 5.98 seconds
Started May 09 02:51:53 PM PDT 24
Finished May 09 02:52:01 PM PDT 24
Peak memory 202104 kb
Host smart-0e86f943-fc43-45e0-aebe-b0f5c9279acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613646407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.613646407
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3337163537
Short name T9
Test name
Test status
Simulation time 5770974008 ps
CPU time 4.47 seconds
Started May 09 02:51:49 PM PDT 24
Finished May 09 02:51:56 PM PDT 24
Peak memory 202096 kb
Host smart-5d9a4c7d-b50b-4004-be4e-ccb3335a141a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337163537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3337163537
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.505028847
Short name T183
Test name
Test status
Simulation time 221878346054 ps
CPU time 127.97 seconds
Started May 09 02:51:49 PM PDT 24
Finished May 09 02:54:00 PM PDT 24
Peak memory 202308 kb
Host smart-7dc10d4b-c801-4330-b45f-4851b4ce61cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505028847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
505028847
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2637558322
Short name T666
Test name
Test status
Simulation time 456913960 ps
CPU time 0.71 seconds
Started May 09 02:50:48 PM PDT 24
Finished May 09 02:50:55 PM PDT 24
Peak memory 202028 kb
Host smart-baaefa4b-33ac-4819-8131-f98989547a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637558322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2637558322
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.162839671
Short name T279
Test name
Test status
Simulation time 330741635953 ps
CPU time 48.78 seconds
Started May 09 02:50:51 PM PDT 24
Finished May 09 02:51:45 PM PDT 24
Peak memory 202304 kb
Host smart-5526b2bd-9e03-4a75-8a06-d6bb3fa28161
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162839671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.162839671
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1945171106
Short name T593
Test name
Test status
Simulation time 328295650802 ps
CPU time 159.02 seconds
Started May 09 02:50:49 PM PDT 24
Finished May 09 02:53:34 PM PDT 24
Peak memory 202308 kb
Host smart-32affdba-4c1b-43de-a131-3e11710b0c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945171106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1945171106
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.374530781
Short name T395
Test name
Test status
Simulation time 493911953832 ps
CPU time 1125.2 seconds
Started May 09 02:50:51 PM PDT 24
Finished May 09 03:09:41 PM PDT 24
Peak memory 202344 kb
Host smart-1e4999d8-f119-4e0e-9d49-2231e2f980af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=374530781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.374530781
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2564780037
Short name T684
Test name
Test status
Simulation time 323019353097 ps
CPU time 105.47 seconds
Started May 09 02:50:49 PM PDT 24
Finished May 09 02:52:40 PM PDT 24
Peak memory 202268 kb
Host smart-fdd30bf8-4b3d-4dde-8203-6d269c508708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564780037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2564780037
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3535151227
Short name T28
Test name
Test status
Simulation time 499496399658 ps
CPU time 585.65 seconds
Started May 09 02:50:48 PM PDT 24
Finished May 09 03:00:40 PM PDT 24
Peak memory 202276 kb
Host smart-b1075f09-b8ce-4692-935e-d11cc075606f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535151227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3535151227
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3229034881
Short name T618
Test name
Test status
Simulation time 164573743884 ps
CPU time 51.43 seconds
Started May 09 02:50:50 PM PDT 24
Finished May 09 02:51:47 PM PDT 24
Peak memory 202420 kb
Host smart-bb6947d6-1db7-4a10-b2bf-c9c5fdc3a131
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229034881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3229034881
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1341011235
Short name T582
Test name
Test status
Simulation time 597349894886 ps
CPU time 1343.92 seconds
Started May 09 02:50:52 PM PDT 24
Finished May 09 03:13:20 PM PDT 24
Peak memory 202468 kb
Host smart-ad52b356-a69b-4008-8540-e80e3f4a20ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341011235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1341011235
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2052373903
Short name T585
Test name
Test status
Simulation time 115654811292 ps
CPU time 498.22 seconds
Started May 09 02:50:50 PM PDT 24
Finished May 09 02:59:14 PM PDT 24
Peak memory 202740 kb
Host smart-1fe9012c-f6fd-431f-90c1-c28a6b4a0b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052373903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2052373903
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1234577048
Short name T392
Test name
Test status
Simulation time 34375043166 ps
CPU time 6.82 seconds
Started May 09 02:50:51 PM PDT 24
Finished May 09 02:51:03 PM PDT 24
Peak memory 202192 kb
Host smart-a9ecda52-5a74-4932-887e-fd0fd716279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234577048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1234577048
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3794568841
Short name T510
Test name
Test status
Simulation time 5525067194 ps
CPU time 3.97 seconds
Started May 09 02:50:51 PM PDT 24
Finished May 09 02:51:00 PM PDT 24
Peak memory 202380 kb
Host smart-72af128e-4fc5-4e4a-8493-c503dbac9015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794568841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3794568841
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.347758941
Short name T73
Test name
Test status
Simulation time 4112584268 ps
CPU time 9.82 seconds
Started May 09 02:50:51 PM PDT 24
Finished May 09 02:51:06 PM PDT 24
Peak memory 217824 kb
Host smart-a13ffd12-6b77-41b1-b215-5fc6ca3d41d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347758941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.347758941
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.432873143
Short name T383
Test name
Test status
Simulation time 5867930810 ps
CPU time 14.29 seconds
Started May 09 02:51:08 PM PDT 24
Finished May 09 02:51:30 PM PDT 24
Peak memory 202136 kb
Host smart-082805cc-ced1-4461-a2e7-ba72f90d7fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432873143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.432873143
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2150124305
Short name T242
Test name
Test status
Simulation time 474783079204 ps
CPU time 1499.2 seconds
Started May 09 02:50:50 PM PDT 24
Finished May 09 03:15:55 PM PDT 24
Peak memory 210912 kb
Host smart-07c3aed3-9d77-40cd-b26e-28c90fa90015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150124305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2150124305
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.810020182
Short name T20
Test name
Test status
Simulation time 128259812572 ps
CPU time 201.35 seconds
Started May 09 02:50:50 PM PDT 24
Finished May 09 02:54:17 PM PDT 24
Peak memory 211016 kb
Host smart-0e4f3072-55a5-43b2-8a34-62b241375fde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810020182 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.810020182
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.670864295
Short name T700
Test name
Test status
Simulation time 548379933 ps
CPU time 1.03 seconds
Started May 09 02:52:00 PM PDT 24
Finished May 09 02:52:03 PM PDT 24
Peak memory 202048 kb
Host smart-9f21c05b-4e77-4f8d-8c28-fbbd6a16bdb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670864295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.670864295
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1918630226
Short name T228
Test name
Test status
Simulation time 396785478762 ps
CPU time 941.34 seconds
Started May 09 02:52:01 PM PDT 24
Finished May 09 03:07:44 PM PDT 24
Peak memory 202332 kb
Host smart-f38e2fd7-85e0-46bc-86d2-96aa94863cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918630226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1918630226
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2435425911
Short name T262
Test name
Test status
Simulation time 320151066672 ps
CPU time 381.69 seconds
Started May 09 02:51:50 PM PDT 24
Finished May 09 02:58:15 PM PDT 24
Peak memory 202260 kb
Host smart-97a9f399-37b1-4fc9-bfe2-247b71f6baf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435425911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2435425911
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2358306883
Short name T194
Test name
Test status
Simulation time 331856640082 ps
CPU time 127.69 seconds
Started May 09 02:51:48 PM PDT 24
Finished May 09 02:53:59 PM PDT 24
Peak memory 202340 kb
Host smart-48e252da-af01-41a4-a02d-e3912f01be3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358306883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2358306883
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2793815557
Short name T695
Test name
Test status
Simulation time 169783561399 ps
CPU time 91.09 seconds
Started May 09 02:51:48 PM PDT 24
Finished May 09 02:53:22 PM PDT 24
Peak memory 202364 kb
Host smart-1a03601d-bbb1-44bc-a9dc-b39b4f0b73e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793815557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2793815557
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1299627039
Short name T187
Test name
Test status
Simulation time 537009391169 ps
CPU time 269.87 seconds
Started May 09 02:51:57 PM PDT 24
Finished May 09 02:56:28 PM PDT 24
Peak memory 202332 kb
Host smart-979e6beb-ef79-4f18-b235-771c26376cfc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299627039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1299627039
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.4080832343
Short name T433
Test name
Test status
Simulation time 617289718134 ps
CPU time 1395.21 seconds
Started May 09 02:51:48 PM PDT 24
Finished May 09 03:15:06 PM PDT 24
Peak memory 202288 kb
Host smart-e44d1ab7-e307-417c-b274-a991441371b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080832343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.4080832343
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2987490535
Short name T352
Test name
Test status
Simulation time 78161363556 ps
CPU time 222.94 seconds
Started May 09 02:52:00 PM PDT 24
Finished May 09 02:55:45 PM PDT 24
Peak memory 202768 kb
Host smart-bfc0ffe8-2266-4d87-9af3-96065a698e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987490535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2987490535
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2926309182
Short name T441
Test name
Test status
Simulation time 39004342436 ps
CPU time 87.08 seconds
Started May 09 02:51:59 PM PDT 24
Finished May 09 02:53:28 PM PDT 24
Peak memory 202092 kb
Host smart-af623afb-59f9-4ce7-94cf-c47dd5a41501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926309182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2926309182
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.40297996
Short name T787
Test name
Test status
Simulation time 4338273055 ps
CPU time 10.25 seconds
Started May 09 02:52:04 PM PDT 24
Finished May 09 02:52:15 PM PDT 24
Peak memory 202156 kb
Host smart-a6782c4d-cd0a-4c64-8fc7-617fd31cb351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40297996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.40297996
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2886076510
Short name T353
Test name
Test status
Simulation time 6087877037 ps
CPU time 4.03 seconds
Started May 09 02:51:49 PM PDT 24
Finished May 09 02:51:56 PM PDT 24
Peak memory 202152 kb
Host smart-da88c318-d6c2-440e-bbd8-70950d51a683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886076510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2886076510
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3266284892
Short name T78
Test name
Test status
Simulation time 166772702772 ps
CPU time 96.59 seconds
Started May 09 02:51:59 PM PDT 24
Finished May 09 02:53:38 PM PDT 24
Peak memory 202368 kb
Host smart-b504221a-165a-4121-a061-6dce831afa80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266284892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3266284892
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3867320388
Short name T714
Test name
Test status
Simulation time 396981714 ps
CPU time 1.43 seconds
Started May 09 02:52:01 PM PDT 24
Finished May 09 02:52:04 PM PDT 24
Peak memory 202012 kb
Host smart-525f5f77-ee22-4cd7-85fa-a66bec989989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867320388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3867320388
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1748975698
Short name T211
Test name
Test status
Simulation time 354985280106 ps
CPU time 103.15 seconds
Started May 09 02:51:59 PM PDT 24
Finished May 09 02:53:43 PM PDT 24
Peak memory 202280 kb
Host smart-a320ecae-17dc-47f7-8f3b-1683571b6f3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748975698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1748975698
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3196604279
Short name T118
Test name
Test status
Simulation time 165473110462 ps
CPU time 281.88 seconds
Started May 09 02:51:59 PM PDT 24
Finished May 09 02:56:42 PM PDT 24
Peak memory 202308 kb
Host smart-931e892c-03e4-41bc-b132-ca5651e2e313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196604279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3196604279
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2528194858
Short name T294
Test name
Test status
Simulation time 318467445028 ps
CPU time 182.98 seconds
Started May 09 02:51:59 PM PDT 24
Finished May 09 02:55:04 PM PDT 24
Peak memory 202256 kb
Host smart-17b3ecbe-d4b2-48e4-88df-f4dc652d1643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528194858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2528194858
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.729989635
Short name T685
Test name
Test status
Simulation time 327777781519 ps
CPU time 185.91 seconds
Started May 09 02:52:00 PM PDT 24
Finished May 09 02:55:08 PM PDT 24
Peak memory 202288 kb
Host smart-6a1a7a69-ba7a-41c3-82fb-4316e8d57e7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=729989635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.729989635
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3619207809
Short name T696
Test name
Test status
Simulation time 162984476333 ps
CPU time 96.26 seconds
Started May 09 02:52:01 PM PDT 24
Finished May 09 02:53:39 PM PDT 24
Peak memory 202360 kb
Host smart-5fd75939-7f56-4200-afd0-40d8d5339ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619207809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3619207809
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1090897118
Short name T572
Test name
Test status
Simulation time 163221874237 ps
CPU time 73.96 seconds
Started May 09 02:52:00 PM PDT 24
Finished May 09 02:53:16 PM PDT 24
Peak memory 202236 kb
Host smart-501dc3f2-a7f5-481c-b37d-902d2f0422f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090897118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1090897118
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2394003703
Short name T255
Test name
Test status
Simulation time 351715586860 ps
CPU time 290.28 seconds
Started May 09 02:52:00 PM PDT 24
Finished May 09 02:56:53 PM PDT 24
Peak memory 202320 kb
Host smart-a052df85-becb-4af8-a927-d53951784a17
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394003703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2394003703
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.437597000
Short name T440
Test name
Test status
Simulation time 573855874128 ps
CPU time 695.09 seconds
Started May 09 02:52:01 PM PDT 24
Finished May 09 03:03:38 PM PDT 24
Peak memory 202296 kb
Host smart-dc850302-11d7-4d3c-9fa7-80f049c04cc8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437597000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.437597000
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3087785692
Short name T630
Test name
Test status
Simulation time 29025458034 ps
CPU time 17.81 seconds
Started May 09 02:52:00 PM PDT 24
Finished May 09 02:52:21 PM PDT 24
Peak memory 202156 kb
Host smart-48896a61-242d-4ff0-ba0d-9dcc0208bc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087785692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3087785692
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1024088573
Short name T531
Test name
Test status
Simulation time 3254353765 ps
CPU time 8.96 seconds
Started May 09 02:52:03 PM PDT 24
Finished May 09 02:52:13 PM PDT 24
Peak memory 202160 kb
Host smart-6f1c9091-a5b2-4ff2-9604-14c516f3df20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024088573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1024088573
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3872389833
Short name T362
Test name
Test status
Simulation time 5795738857 ps
CPU time 4.11 seconds
Started May 09 02:52:04 PM PDT 24
Finished May 09 02:52:08 PM PDT 24
Peak memory 202152 kb
Host smart-d66e3e5b-aaf0-4eec-95d1-947f3ea37826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872389833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3872389833
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2462272547
Short name T37
Test name
Test status
Simulation time 44081219600 ps
CPU time 96.8 seconds
Started May 09 02:51:59 PM PDT 24
Finished May 09 02:53:38 PM PDT 24
Peak memory 202424 kb
Host smart-73dbfcaa-fadf-444d-bb85-229ca447c758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462272547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2462272547
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2582563948
Short name T565
Test name
Test status
Simulation time 59364917308 ps
CPU time 140.3 seconds
Started May 09 02:52:00 PM PDT 24
Finished May 09 02:54:23 PM PDT 24
Peak memory 211108 kb
Host smart-0f57960a-7db0-474a-849c-95439a922467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582563948 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2582563948
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1767094883
Short name T498
Test name
Test status
Simulation time 423806408 ps
CPU time 0.89 seconds
Started May 09 02:52:10 PM PDT 24
Finished May 09 02:52:12 PM PDT 24
Peak memory 202008 kb
Host smart-73e5e01c-201c-44e8-aa24-b01eba3dba5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767094883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1767094883
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2758647406
Short name T543
Test name
Test status
Simulation time 167479065084 ps
CPU time 93.99 seconds
Started May 09 02:52:12 PM PDT 24
Finished May 09 02:53:47 PM PDT 24
Peak memory 202304 kb
Host smart-de96caca-41e3-4565-8e29-e2289ba3928b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758647406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2758647406
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.363257474
Short name T302
Test name
Test status
Simulation time 165207504328 ps
CPU time 103.81 seconds
Started May 09 02:52:10 PM PDT 24
Finished May 09 02:53:54 PM PDT 24
Peak memory 202328 kb
Host smart-11f20a8b-5f45-4a0a-b37f-8d0358058485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363257474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.363257474
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1988379433
Short name T117
Test name
Test status
Simulation time 161024681429 ps
CPU time 354.17 seconds
Started May 09 02:52:09 PM PDT 24
Finished May 09 02:58:04 PM PDT 24
Peak memory 202360 kb
Host smart-2cda0b15-ae87-4254-94b8-5cbf7efbba8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988379433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1988379433
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1455275815
Short name T621
Test name
Test status
Simulation time 325528285219 ps
CPU time 137.88 seconds
Started May 09 02:52:10 PM PDT 24
Finished May 09 02:54:29 PM PDT 24
Peak memory 202348 kb
Host smart-7a29fb25-0d8a-4d7f-adab-672a352df2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455275815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1455275815
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.35381121
Short name T464
Test name
Test status
Simulation time 490217937198 ps
CPU time 256.48 seconds
Started May 09 02:52:10 PM PDT 24
Finished May 09 02:56:29 PM PDT 24
Peak memory 202276 kb
Host smart-32fb644a-587b-456f-acd5-b038cc912c31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=35381121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed
.35381121
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1205957784
Short name T529
Test name
Test status
Simulation time 397831595290 ps
CPU time 934.85 seconds
Started May 09 02:52:12 PM PDT 24
Finished May 09 03:07:48 PM PDT 24
Peak memory 202236 kb
Host smart-7cb26514-4f67-414e-8050-5dbfb7646937
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205957784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1205957784
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3258840185
Short name T8
Test name
Test status
Simulation time 198029811992 ps
CPU time 211.14 seconds
Started May 09 02:52:11 PM PDT 24
Finished May 09 02:55:43 PM PDT 24
Peak memory 202296 kb
Host smart-d07048a6-8ffc-41a5-b870-4dd987542706
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258840185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3258840185
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1061613133
Short name T725
Test name
Test status
Simulation time 66809725934 ps
CPU time 246.68 seconds
Started May 09 02:52:09 PM PDT 24
Finished May 09 02:56:17 PM PDT 24
Peak memory 202688 kb
Host smart-7382db74-4f0b-4936-914e-a6407317c61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061613133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1061613133
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2942496270
Short name T429
Test name
Test status
Simulation time 26224401934 ps
CPU time 60.32 seconds
Started May 09 02:52:11 PM PDT 24
Finished May 09 02:53:13 PM PDT 24
Peak memory 202140 kb
Host smart-e6e23d9c-d726-4295-af03-16f338ee76ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942496270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2942496270
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.836397163
Short name T779
Test name
Test status
Simulation time 4417030038 ps
CPU time 11.73 seconds
Started May 09 02:52:10 PM PDT 24
Finished May 09 02:52:23 PM PDT 24
Peak memory 202136 kb
Host smart-f183f0ba-844b-422c-bb1c-8e035fc4c5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836397163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.836397163
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.224009244
Short name T564
Test name
Test status
Simulation time 5521607393 ps
CPU time 7.53 seconds
Started May 09 02:52:11 PM PDT 24
Finished May 09 02:52:20 PM PDT 24
Peak memory 202104 kb
Host smart-4884f5dd-aa17-4b4d-b6c5-c455427ab537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224009244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.224009244
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1565135727
Short name T741
Test name
Test status
Simulation time 43545750506 ps
CPU time 102.81 seconds
Started May 09 02:52:10 PM PDT 24
Finished May 09 02:53:54 PM PDT 24
Peak memory 202196 kb
Host smart-a1112d3f-1b62-4291-a68f-ac0978f2b3df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565135727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1565135727
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1393110130
Short name T23
Test name
Test status
Simulation time 97916502973 ps
CPU time 214.53 seconds
Started May 09 02:52:10 PM PDT 24
Finished May 09 02:55:46 PM PDT 24
Peak memory 211064 kb
Host smart-0df317e4-d8c6-485e-b754-808fe064166b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393110130 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1393110130
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.4039039355
Short name T499
Test name
Test status
Simulation time 486843265 ps
CPU time 0.68 seconds
Started May 09 02:52:17 PM PDT 24
Finished May 09 02:52:19 PM PDT 24
Peak memory 202004 kb
Host smart-0ad4b683-cf27-43b2-a9de-79ed2027bb7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039039355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.4039039355
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.436668243
Short name T161
Test name
Test status
Simulation time 161916548793 ps
CPU time 361.77 seconds
Started May 09 02:52:10 PM PDT 24
Finished May 09 02:58:14 PM PDT 24
Peak memory 202340 kb
Host smart-996192c5-2b2b-4ccd-b4b0-1ebae216c4a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436668243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.436668243
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2677729715
Short name T799
Test name
Test status
Simulation time 169475923310 ps
CPU time 411.91 seconds
Started May 09 02:52:11 PM PDT 24
Finished May 09 02:59:04 PM PDT 24
Peak memory 202440 kb
Host smart-4518c967-7493-4f42-89ca-c09312912c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677729715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2677729715
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3702514803
Short name T542
Test name
Test status
Simulation time 502083944886 ps
CPU time 908.55 seconds
Started May 09 02:52:11 PM PDT 24
Finished May 09 03:07:21 PM PDT 24
Peak memory 202280 kb
Host smart-0521bcb4-c884-4e0d-9b9e-f7c14255dbd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702514803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3702514803
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.220231759
Short name T316
Test name
Test status
Simulation time 485289357359 ps
CPU time 265.85 seconds
Started May 09 02:52:11 PM PDT 24
Finished May 09 02:56:39 PM PDT 24
Peak memory 202232 kb
Host smart-cc52a9c9-791c-4b36-acf3-760a3a0729f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220231759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.220231759
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.376232070
Short name T701
Test name
Test status
Simulation time 164629934165 ps
CPU time 54.98 seconds
Started May 09 02:52:11 PM PDT 24
Finished May 09 02:53:07 PM PDT 24
Peak memory 202296 kb
Host smart-e414c5ec-d3ee-45f7-b978-e615b20336b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=376232070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.376232070
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.698089384
Short name T737
Test name
Test status
Simulation time 354190359426 ps
CPU time 808.31 seconds
Started May 09 02:52:13 PM PDT 24
Finished May 09 03:05:42 PM PDT 24
Peak memory 202424 kb
Host smart-ab43154c-4317-4a51-9e92-3686ef81718d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698089384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.698089384
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.878190537
Short name T94
Test name
Test status
Simulation time 611286448746 ps
CPU time 1394.97 seconds
Started May 09 02:52:11 PM PDT 24
Finished May 09 03:15:28 PM PDT 24
Peak memory 202368 kb
Host smart-8d7bd116-e1dd-4280-8c96-f4a984da14ec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878190537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.878190537
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3615551711
Short name T673
Test name
Test status
Simulation time 116445488188 ps
CPU time 627.55 seconds
Started May 09 02:52:13 PM PDT 24
Finished May 09 03:02:42 PM PDT 24
Peak memory 202804 kb
Host smart-c42f9ee0-be0a-40d7-9611-ea93bc9611ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615551711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3615551711
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1372577163
Short name T651
Test name
Test status
Simulation time 36786048666 ps
CPU time 85.92 seconds
Started May 09 02:52:10 PM PDT 24
Finished May 09 02:53:38 PM PDT 24
Peak memory 202076 kb
Host smart-82d316ae-c37c-4503-9f70-4c30c2ddd644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372577163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1372577163
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3182524226
Short name T97
Test name
Test status
Simulation time 3100062880 ps
CPU time 7.91 seconds
Started May 09 02:52:16 PM PDT 24
Finished May 09 02:52:26 PM PDT 24
Peak memory 202128 kb
Host smart-59a9e2ea-afdc-4427-be02-f6a646974f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182524226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3182524226
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2586005324
Short name T682
Test name
Test status
Simulation time 5929065888 ps
CPU time 2.72 seconds
Started May 09 02:52:10 PM PDT 24
Finished May 09 02:52:14 PM PDT 24
Peak memory 202152 kb
Host smart-2f5c8ccd-b37e-4c01-a0fc-bc0d9e7d8c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586005324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2586005324
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.194980976
Short name T635
Test name
Test status
Simulation time 368231069816 ps
CPU time 445.56 seconds
Started May 09 02:52:12 PM PDT 24
Finished May 09 02:59:39 PM PDT 24
Peak memory 202420 kb
Host smart-e390947c-9d88-48fd-8e58-4f32c10163b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194980976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
194980976
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1380598309
Short name T587
Test name
Test status
Simulation time 15886702889 ps
CPU time 35.43 seconds
Started May 09 02:52:10 PM PDT 24
Finished May 09 02:52:46 PM PDT 24
Peak memory 202368 kb
Host smart-47817f05-2d9f-4883-9d43-79f6ed15cbd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380598309 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1380598309
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1064942958
Short name T371
Test name
Test status
Simulation time 326875102 ps
CPU time 1.29 seconds
Started May 09 02:52:21 PM PDT 24
Finished May 09 02:52:26 PM PDT 24
Peak memory 202008 kb
Host smart-a78fdfa9-1fed-4f0f-882e-12c27899ba08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064942958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1064942958
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2514128772
Short name T338
Test name
Test status
Simulation time 166760964302 ps
CPU time 103.36 seconds
Started May 09 02:52:21 PM PDT 24
Finished May 09 02:54:07 PM PDT 24
Peak memory 202364 kb
Host smart-b39a6245-920b-42b6-98e5-a9a5977e627e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514128772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2514128772
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3365173465
Short name T177
Test name
Test status
Simulation time 330799507444 ps
CPU time 102.92 seconds
Started May 09 02:52:22 PM PDT 24
Finished May 09 02:54:08 PM PDT 24
Peak memory 202448 kb
Host smart-17d38631-5e4d-4783-9ad6-784b7ed9e911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365173465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3365173465
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.289709504
Short name T488
Test name
Test status
Simulation time 168693002243 ps
CPU time 201.81 seconds
Started May 09 02:52:25 PM PDT 24
Finished May 09 02:55:48 PM PDT 24
Peak memory 202324 kb
Host smart-003acc43-5b16-4432-a578-ca334597fc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289709504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.289709504
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.4135209415
Short name T641
Test name
Test status
Simulation time 490139442108 ps
CPU time 1059.28 seconds
Started May 09 02:52:23 PM PDT 24
Finished May 09 03:10:05 PM PDT 24
Peak memory 202308 kb
Host smart-16561957-8c3b-4d5c-9146-adc775d0cf4b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135209415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.4135209415
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1583899201
Short name T186
Test name
Test status
Simulation time 331706689984 ps
CPU time 101.46 seconds
Started May 09 02:52:21 PM PDT 24
Finished May 09 02:54:05 PM PDT 24
Peak memory 202348 kb
Host smart-30f5f8e4-ffef-49b2-a7a7-b1b1f78789a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583899201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1583899201
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1738678492
Short name T489
Test name
Test status
Simulation time 494252255150 ps
CPU time 586.83 seconds
Started May 09 02:52:22 PM PDT 24
Finished May 09 03:02:12 PM PDT 24
Peak memory 202288 kb
Host smart-27a72152-f101-4ebd-81f0-7a11e0bc8b18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738678492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1738678492
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.4156939441
Short name T771
Test name
Test status
Simulation time 406826584038 ps
CPU time 570.92 seconds
Started May 09 02:52:23 PM PDT 24
Finished May 09 03:01:57 PM PDT 24
Peak memory 202312 kb
Host smart-c4c50003-d2a2-4bae-a166-8c739274e8cb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156939441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.4156939441
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.481473971
Short name T795
Test name
Test status
Simulation time 40915549702 ps
CPU time 6 seconds
Started May 09 02:52:22 PM PDT 24
Finished May 09 02:52:31 PM PDT 24
Peak memory 202172 kb
Host smart-4f8b9f95-2e60-436e-a6e2-58d065a1358e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481473971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.481473971
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1916857260
Short name T652
Test name
Test status
Simulation time 3462124286 ps
CPU time 2.86 seconds
Started May 09 02:52:22 PM PDT 24
Finished May 09 02:52:28 PM PDT 24
Peak memory 202132 kb
Host smart-48bd2cfb-c95f-4d76-aa4d-ab4885ea06ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916857260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1916857260
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.973275067
Short name T649
Test name
Test status
Simulation time 6168296920 ps
CPU time 15.43 seconds
Started May 09 02:52:12 PM PDT 24
Finished May 09 02:52:29 PM PDT 24
Peak memory 202136 kb
Host smart-a961fe2c-9b54-4a3e-81d3-d23594ed65a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973275067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.973275067
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1855779227
Short name T319
Test name
Test status
Simulation time 168235231616 ps
CPU time 195.65 seconds
Started May 09 02:52:23 PM PDT 24
Finished May 09 02:55:41 PM PDT 24
Peak memory 210656 kb
Host smart-e2f3d5f6-e738-4855-80e8-66b28e5c13c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855779227 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1855779227
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1391899121
Short name T628
Test name
Test status
Simulation time 414340850 ps
CPU time 1.35 seconds
Started May 09 02:52:31 PM PDT 24
Finished May 09 02:52:33 PM PDT 24
Peak memory 202036 kb
Host smart-00ab05b5-7f50-4f13-a0c0-16ab2042c953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391899121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1391899121
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1504117870
Short name T662
Test name
Test status
Simulation time 346693505901 ps
CPU time 107.78 seconds
Started May 09 02:52:24 PM PDT 24
Finished May 09 02:54:14 PM PDT 24
Peak memory 202332 kb
Host smart-d39f9174-2131-4cac-aa89-c1ea80cbf889
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504117870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1504117870
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.4038026917
Short name T290
Test name
Test status
Simulation time 215893987773 ps
CPU time 128.2 seconds
Started May 09 02:52:21 PM PDT 24
Finished May 09 02:54:33 PM PDT 24
Peak memory 202308 kb
Host smart-c9ee900c-b685-4844-b664-3a7590a204e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038026917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.4038026917
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.994915067
Short name T333
Test name
Test status
Simulation time 501326803900 ps
CPU time 277.2 seconds
Started May 09 02:52:24 PM PDT 24
Finished May 09 02:57:03 PM PDT 24
Peak memory 202404 kb
Host smart-8b8e878c-5c40-4871-acce-749a8139ba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994915067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.994915067
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1067195581
Short name T578
Test name
Test status
Simulation time 492158610770 ps
CPU time 384.58 seconds
Started May 09 02:52:22 PM PDT 24
Finished May 09 02:58:49 PM PDT 24
Peak memory 202296 kb
Host smart-7fc1a4b1-86ca-4aeb-bb4e-a7bcbffc46b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067195581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1067195581
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1309188705
Short name T223
Test name
Test status
Simulation time 330583788460 ps
CPU time 202.41 seconds
Started May 09 02:52:21 PM PDT 24
Finished May 09 02:55:46 PM PDT 24
Peak memory 202300 kb
Host smart-e85f0b48-96f8-4f8b-b37b-ac1ce3597b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309188705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1309188705
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.121941806
Short name T758
Test name
Test status
Simulation time 162774427727 ps
CPU time 361.8 seconds
Started May 09 02:52:22 PM PDT 24
Finished May 09 02:58:27 PM PDT 24
Peak memory 202284 kb
Host smart-5f8cfcd6-814f-4f91-9d44-59b27e9885be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=121941806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.121941806
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3808327291
Short name T334
Test name
Test status
Simulation time 172465900016 ps
CPU time 67.89 seconds
Started May 09 02:52:25 PM PDT 24
Finished May 09 02:53:34 PM PDT 24
Peak memory 202252 kb
Host smart-ec7754a1-9b0e-47f9-86a8-242ee0023fc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808327291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3808327291
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3097425805
Short name T770
Test name
Test status
Simulation time 196689172273 ps
CPU time 118.12 seconds
Started May 09 02:52:23 PM PDT 24
Finished May 09 02:54:24 PM PDT 24
Peak memory 202244 kb
Host smart-27b6d3ae-8db5-4ed9-a3b4-29be52aa905e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097425805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3097425805
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2897053867
Short name T222
Test name
Test status
Simulation time 93854473338 ps
CPU time 473.7 seconds
Started May 09 02:52:21 PM PDT 24
Finished May 09 03:00:17 PM PDT 24
Peak memory 202764 kb
Host smart-596a4365-1b85-42c3-99e8-6af933f19fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897053867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2897053867
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2332899435
Short name T506
Test name
Test status
Simulation time 42827258493 ps
CPU time 26.18 seconds
Started May 09 02:52:22 PM PDT 24
Finished May 09 02:52:51 PM PDT 24
Peak memory 202156 kb
Host smart-6a2b93f8-eac7-482b-852e-89ec1c62009b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332899435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2332899435
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2262457872
Short name T453
Test name
Test status
Simulation time 4842330852 ps
CPU time 8.2 seconds
Started May 09 02:52:20 PM PDT 24
Finished May 09 02:52:31 PM PDT 24
Peak memory 202148 kb
Host smart-f489c43d-5368-4c4c-9a6a-964cc1280e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262457872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2262457872
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2674283310
Short name T511
Test name
Test status
Simulation time 5885264272 ps
CPU time 3.72 seconds
Started May 09 02:52:21 PM PDT 24
Finished May 09 02:52:27 PM PDT 24
Peak memory 202132 kb
Host smart-d6b5f09e-d39e-4875-b138-cfc5fe3db22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674283310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2674283310
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2672513861
Short name T328
Test name
Test status
Simulation time 275694895867 ps
CPU time 416.36 seconds
Started May 09 02:52:31 PM PDT 24
Finished May 09 02:59:29 PM PDT 24
Peak memory 202704 kb
Host smart-c3bfa09e-ff56-4446-bc3b-14fcf752a9b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672513861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2672513861
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3693698855
Short name T620
Test name
Test status
Simulation time 54467497459 ps
CPU time 136.21 seconds
Started May 09 02:52:22 PM PDT 24
Finished May 09 02:54:41 PM PDT 24
Peak memory 210936 kb
Host smart-dc108077-c9db-40c2-ab08-7d02c3a568b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693698855 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3693698855
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.228651063
Short name T690
Test name
Test status
Simulation time 492039000 ps
CPU time 1.61 seconds
Started May 09 02:52:33 PM PDT 24
Finished May 09 02:52:36 PM PDT 24
Peak memory 202008 kb
Host smart-91de448b-f3f5-4cd0-ae78-aed6bbe97ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228651063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.228651063
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2005465985
Short name T3
Test name
Test status
Simulation time 164851368276 ps
CPU time 134.53 seconds
Started May 09 02:52:33 PM PDT 24
Finished May 09 02:54:49 PM PDT 24
Peak memory 202340 kb
Host smart-9ca97125-8981-46b7-9f18-f5bf66818ba2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005465985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2005465985
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2571520855
Short name T671
Test name
Test status
Simulation time 164423916178 ps
CPU time 80.07 seconds
Started May 09 02:52:34 PM PDT 24
Finished May 09 02:53:55 PM PDT 24
Peak memory 202256 kb
Host smart-d5defd47-5d8d-40ea-8be1-363c6a4c6a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571520855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2571520855
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3803016550
Short name T710
Test name
Test status
Simulation time 489051339589 ps
CPU time 203.73 seconds
Started May 09 02:52:33 PM PDT 24
Finished May 09 02:55:58 PM PDT 24
Peak memory 202308 kb
Host smart-64bc216c-8fb8-4249-b99e-33d3c9ca24e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803016550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3803016550
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2916599405
Short name T544
Test name
Test status
Simulation time 321745803037 ps
CPU time 174.9 seconds
Started May 09 02:52:34 PM PDT 24
Finished May 09 02:55:30 PM PDT 24
Peak memory 202288 kb
Host smart-e6e92a87-b9be-4ad2-a70a-98ba1e1105e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916599405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2916599405
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2072401340
Short name T207
Test name
Test status
Simulation time 322475079755 ps
CPU time 205.56 seconds
Started May 09 02:52:34 PM PDT 24
Finished May 09 02:56:01 PM PDT 24
Peak memory 202340 kb
Host smart-fd5d1289-5443-40e5-851f-d4fbb084bfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072401340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2072401340
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3381954983
Short name T675
Test name
Test status
Simulation time 167050799525 ps
CPU time 367.37 seconds
Started May 09 02:52:33 PM PDT 24
Finished May 09 02:58:42 PM PDT 24
Peak memory 202416 kb
Host smart-eaebeaad-dc9d-4633-ba95-52f3887cf541
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381954983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3381954983
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.552192867
Short name T444
Test name
Test status
Simulation time 270859125556 ps
CPU time 161.81 seconds
Started May 09 02:52:33 PM PDT 24
Finished May 09 02:55:17 PM PDT 24
Peak memory 202296 kb
Host smart-12df7218-854a-4b2b-a586-36e378926562
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552192867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.552192867
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2186278022
Short name T594
Test name
Test status
Simulation time 201846286455 ps
CPU time 496.79 seconds
Started May 09 02:52:35 PM PDT 24
Finished May 09 03:00:53 PM PDT 24
Peak memory 202248 kb
Host smart-b80489c8-cfd3-4567-a41d-f4c9c145ccd5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186278022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2186278022
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3605390668
Short name T39
Test name
Test status
Simulation time 98938264635 ps
CPU time 340.85 seconds
Started May 09 02:52:32 PM PDT 24
Finished May 09 02:58:14 PM PDT 24
Peak memory 202656 kb
Host smart-4fc087e1-7475-4b3b-a830-95ed2c3c8c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605390668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3605390668
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1039100883
Short name T465
Test name
Test status
Simulation time 37983591917 ps
CPU time 21.47 seconds
Started May 09 02:52:32 PM PDT 24
Finished May 09 02:52:55 PM PDT 24
Peak memory 202100 kb
Host smart-dc20c53b-f29f-4080-a0a6-cf02ea0f79ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039100883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1039100883
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.357667693
Short name T10
Test name
Test status
Simulation time 5258232913 ps
CPU time 6.99 seconds
Started May 09 02:52:33 PM PDT 24
Finished May 09 02:52:41 PM PDT 24
Peak memory 202124 kb
Host smart-9e701110-c1af-43a9-9882-b245a4e04c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357667693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.357667693
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3135471134
Short name T92
Test name
Test status
Simulation time 5438312657 ps
CPU time 12.27 seconds
Started May 09 02:52:32 PM PDT 24
Finished May 09 02:52:46 PM PDT 24
Peak memory 202172 kb
Host smart-367d93e3-602c-492b-979a-354e10db9ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135471134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3135471134
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.202757935
Short name T568
Test name
Test status
Simulation time 426889002415 ps
CPU time 520.86 seconds
Started May 09 02:52:34 PM PDT 24
Finished May 09 03:01:16 PM PDT 24
Peak memory 210928 kb
Host smart-2553b45f-6e1c-4c9b-a461-934f52b7c6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202757935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
202757935
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3887974277
Short name T21
Test name
Test status
Simulation time 133716915393 ps
CPU time 229.35 seconds
Started May 09 02:52:33 PM PDT 24
Finished May 09 02:56:24 PM PDT 24
Peak memory 210744 kb
Host smart-1233894f-211a-4697-8f5f-0821a1d4a346
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887974277 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3887974277
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.227093274
Short name T173
Test name
Test status
Simulation time 347383886 ps
CPU time 1.39 seconds
Started May 09 02:52:42 PM PDT 24
Finished May 09 02:52:44 PM PDT 24
Peak memory 201980 kb
Host smart-13129933-e315-443d-84fa-eddbcd061d2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227093274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.227093274
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3385245775
Short name T193
Test name
Test status
Simulation time 527435262797 ps
CPU time 169.62 seconds
Started May 09 02:52:43 PM PDT 24
Finished May 09 02:55:34 PM PDT 24
Peak memory 202384 kb
Host smart-da8cef87-6a1d-4b8f-840d-4da402e185e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385245775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3385245775
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3309224530
Short name T446
Test name
Test status
Simulation time 194556760140 ps
CPU time 83.83 seconds
Started May 09 02:52:45 PM PDT 24
Finished May 09 02:54:09 PM PDT 24
Peak memory 202344 kb
Host smart-6a4b8ee5-3d3f-456a-936a-45781d751572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309224530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3309224530
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2104190288
Short name T391
Test name
Test status
Simulation time 159490461214 ps
CPU time 400.59 seconds
Started May 09 02:52:33 PM PDT 24
Finished May 09 02:59:16 PM PDT 24
Peak memory 202288 kb
Host smart-dd086bff-a488-464d-b833-d91fa49b9ad3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104190288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2104190288
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2141848320
Short name T443
Test name
Test status
Simulation time 168079437823 ps
CPU time 75.53 seconds
Started May 09 02:52:31 PM PDT 24
Finished May 09 02:53:47 PM PDT 24
Peak memory 202304 kb
Host smart-338be802-2c63-41b3-8adf-aa6d0b875109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141848320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2141848320
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2344309408
Short name T32
Test name
Test status
Simulation time 327923234750 ps
CPU time 181.03 seconds
Started May 09 02:52:32 PM PDT 24
Finished May 09 02:55:35 PM PDT 24
Peak memory 202284 kb
Host smart-3d3fdf41-d853-44a7-8c8d-dc30793f3324
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344309408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2344309408
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.493698545
Short name T681
Test name
Test status
Simulation time 511232420269 ps
CPU time 193.83 seconds
Started May 09 02:52:32 PM PDT 24
Finished May 09 02:55:48 PM PDT 24
Peak memory 202172 kb
Host smart-5c6e823b-bc1f-4325-b92d-dc16dd8825d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493698545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.493698545
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.856892896
Short name T664
Test name
Test status
Simulation time 620056343006 ps
CPU time 752.77 seconds
Started May 09 02:52:33 PM PDT 24
Finished May 09 03:05:07 PM PDT 24
Peak memory 202316 kb
Host smart-f683fb61-65ef-4241-97aa-3c122951fea9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856892896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.856892896
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.257051418
Short name T216
Test name
Test status
Simulation time 104991321689 ps
CPU time 463.42 seconds
Started May 09 02:52:42 PM PDT 24
Finished May 09 03:00:26 PM PDT 24
Peak memory 202700 kb
Host smart-cb0440e1-312b-4f23-9494-49e3756e0826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257051418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.257051418
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3013513000
Short name T517
Test name
Test status
Simulation time 30299884817 ps
CPU time 32.85 seconds
Started May 09 02:52:42 PM PDT 24
Finished May 09 02:53:17 PM PDT 24
Peak memory 202152 kb
Host smart-674de6fb-273b-47fe-b781-5131ba8c2d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013513000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3013513000
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1485727366
Short name T766
Test name
Test status
Simulation time 4552373739 ps
CPU time 5.67 seconds
Started May 09 02:52:42 PM PDT 24
Finished May 09 02:52:49 PM PDT 24
Peak memory 202100 kb
Host smart-4158376a-e465-4224-b119-79b05dfeb26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485727366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1485727366
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.458450920
Short name T788
Test name
Test status
Simulation time 5509667848 ps
CPU time 13.47 seconds
Started May 09 02:52:33 PM PDT 24
Finished May 09 02:52:48 PM PDT 24
Peak memory 202160 kb
Host smart-42001a1a-40b4-49d2-907f-ecb8282568d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458450920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.458450920
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.238989323
Short name T148
Test name
Test status
Simulation time 384053899897 ps
CPU time 218.49 seconds
Started May 09 02:52:42 PM PDT 24
Finished May 09 02:56:21 PM PDT 24
Peak memory 202440 kb
Host smart-3c44c1e0-d24d-426d-aca0-e8a862e49d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238989323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
238989323
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3101710917
Short name T764
Test name
Test status
Simulation time 71056416697 ps
CPU time 177.03 seconds
Started May 09 02:52:42 PM PDT 24
Finished May 09 02:55:40 PM PDT 24
Peak memory 211008 kb
Host smart-0b2ad395-0f27-4357-af38-272a18d98a2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101710917 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3101710917
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2870986954
Short name T760
Test name
Test status
Simulation time 524825157 ps
CPU time 1.91 seconds
Started May 09 02:52:52 PM PDT 24
Finished May 09 02:52:55 PM PDT 24
Peak memory 202020 kb
Host smart-5d1a87c3-7ad0-40a3-95cc-766e26c33188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870986954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2870986954
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1796288607
Short name T536
Test name
Test status
Simulation time 168156287355 ps
CPU time 159.64 seconds
Started May 09 02:52:42 PM PDT 24
Finished May 09 02:55:23 PM PDT 24
Peak memory 202316 kb
Host smart-2d4b82fc-bfcc-40aa-8af9-a88ad813b89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796288607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1796288607
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3689536042
Short name T200
Test name
Test status
Simulation time 505523705256 ps
CPU time 1237.78 seconds
Started May 09 02:52:42 PM PDT 24
Finished May 09 03:13:21 PM PDT 24
Peak memory 202300 kb
Host smart-85c3a4e2-b022-47ca-8ed6-aed195ec03b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689536042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3689536042
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3846755009
Short name T523
Test name
Test status
Simulation time 167723545658 ps
CPU time 373.31 seconds
Started May 09 02:52:44 PM PDT 24
Finished May 09 02:58:58 PM PDT 24
Peak memory 202416 kb
Host smart-f96ef0c2-82d0-4824-a0c1-78b7583903a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846755009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3846755009
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2217477513
Short name T753
Test name
Test status
Simulation time 335938556459 ps
CPU time 409.31 seconds
Started May 09 02:52:45 PM PDT 24
Finished May 09 02:59:35 PM PDT 24
Peak memory 202400 kb
Host smart-2ec30961-7105-47d8-a07e-486e941a5b9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217477513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2217477513
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.130469028
Short name T522
Test name
Test status
Simulation time 193486166716 ps
CPU time 111.93 seconds
Started May 09 02:52:43 PM PDT 24
Finished May 09 02:54:36 PM PDT 24
Peak memory 202432 kb
Host smart-f1f37c61-f4b2-4c84-ac37-b4fd2a2be2fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130469028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.130469028
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.965779318
Short name T435
Test name
Test status
Simulation time 401107733173 ps
CPU time 1001.33 seconds
Started May 09 02:52:45 PM PDT 24
Finished May 09 03:09:27 PM PDT 24
Peak memory 202404 kb
Host smart-a18f2708-b3d9-477a-959a-11568e4ca49e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965779318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.965779318
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3988131678
Short name T613
Test name
Test status
Simulation time 87333773530 ps
CPU time 347.7 seconds
Started May 09 02:52:43 PM PDT 24
Finished May 09 02:58:32 PM PDT 24
Peak memory 202680 kb
Host smart-4ca1243f-13fd-41b2-a078-cc2908578470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988131678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3988131678
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3440593059
Short name T475
Test name
Test status
Simulation time 32372425614 ps
CPU time 33.08 seconds
Started May 09 02:52:43 PM PDT 24
Finished May 09 02:53:18 PM PDT 24
Peak memory 202184 kb
Host smart-d8b8ba60-0925-4394-95bc-87653dd6b2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440593059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3440593059
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2538886128
Short name T706
Test name
Test status
Simulation time 4026502882 ps
CPU time 2.68 seconds
Started May 09 02:52:43 PM PDT 24
Finished May 09 02:52:47 PM PDT 24
Peak memory 202152 kb
Host smart-6d2d13c4-635c-4b45-99f8-760c5bdbec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538886128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2538886128
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.273736077
Short name T7
Test name
Test status
Simulation time 5557034292 ps
CPU time 12.94 seconds
Started May 09 02:52:43 PM PDT 24
Finished May 09 02:52:57 PM PDT 24
Peak memory 201996 kb
Host smart-f412cb8d-b7f4-4f5b-adb2-f3f46b1b5187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273736077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.273736077
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3025439256
Short name T483
Test name
Test status
Simulation time 330097033485 ps
CPU time 213.96 seconds
Started May 09 02:52:43 PM PDT 24
Finished May 09 02:56:18 PM PDT 24
Peak memory 202244 kb
Host smart-e55f6fa9-a48f-4c5b-aec6-96af7205651a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025439256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3025439256
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2276277725
Short name T17
Test name
Test status
Simulation time 26765268225 ps
CPU time 5.62 seconds
Started May 09 02:52:43 PM PDT 24
Finished May 09 02:52:50 PM PDT 24
Peak memory 211752 kb
Host smart-28738026-dd54-49a2-8bc1-270edf10c5c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276277725 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2276277725
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3874022750
Short name T423
Test name
Test status
Simulation time 485426756 ps
CPU time 0.7 seconds
Started May 09 02:53:04 PM PDT 24
Finished May 09 02:53:07 PM PDT 24
Peak memory 202020 kb
Host smart-e9ad931b-af96-40bc-8165-2d4e2db360d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874022750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3874022750
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1652907398
Short name T269
Test name
Test status
Simulation time 167721229784 ps
CPU time 395.93 seconds
Started May 09 02:52:51 PM PDT 24
Finished May 09 02:59:28 PM PDT 24
Peak memory 202344 kb
Host smart-5b792274-7845-40aa-b518-9e4cdbdce097
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652907398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1652907398
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3281554967
Short name T607
Test name
Test status
Simulation time 274677676165 ps
CPU time 170.34 seconds
Started May 09 02:52:51 PM PDT 24
Finished May 09 02:55:42 PM PDT 24
Peak memory 202400 kb
Host smart-9dbc1819-78a2-45d4-a151-adfb2ac2c819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281554967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3281554967
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1754017143
Short name T181
Test name
Test status
Simulation time 339433576532 ps
CPU time 140.33 seconds
Started May 09 02:52:52 PM PDT 24
Finished May 09 02:55:14 PM PDT 24
Peak memory 202368 kb
Host smart-bea57e4a-db89-4e91-98fa-82c2b92d2b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754017143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1754017143
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.323240630
Short name T647
Test name
Test status
Simulation time 165932435530 ps
CPU time 194.09 seconds
Started May 09 02:52:55 PM PDT 24
Finished May 09 02:56:10 PM PDT 24
Peak memory 202260 kb
Host smart-de7a5611-639d-48e7-8f63-4eda66403212
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=323240630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.323240630
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.450559132
Short name T792
Test name
Test status
Simulation time 163711887548 ps
CPU time 94.57 seconds
Started May 09 02:52:55 PM PDT 24
Finished May 09 02:54:30 PM PDT 24
Peak memory 202364 kb
Host smart-c0c14ab1-3033-4a30-a932-23f54aea4f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450559132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.450559132
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.4164970178
Short name T385
Test name
Test status
Simulation time 163225375218 ps
CPU time 98.66 seconds
Started May 09 02:52:54 PM PDT 24
Finished May 09 02:54:33 PM PDT 24
Peak memory 202276 kb
Host smart-18475dbb-1395-45f7-9498-c249102c7ac2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164970178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.4164970178
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3257095803
Short name T615
Test name
Test status
Simulation time 547981223975 ps
CPU time 1257.32 seconds
Started May 09 02:52:52 PM PDT 24
Finished May 09 03:13:50 PM PDT 24
Peak memory 202356 kb
Host smart-e4086758-d0d2-45f1-993f-bb28326d97f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257095803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3257095803
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2084231731
Short name T380
Test name
Test status
Simulation time 207672616694 ps
CPU time 122.46 seconds
Started May 09 02:52:53 PM PDT 24
Finished May 09 02:54:57 PM PDT 24
Peak memory 202320 kb
Host smart-db03c827-f0f9-4d7c-b1d2-3772a10782e4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084231731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2084231731
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.114990316
Short name T103
Test name
Test status
Simulation time 128438244050 ps
CPU time 670.44 seconds
Started May 09 02:52:54 PM PDT 24
Finished May 09 03:04:05 PM PDT 24
Peak memory 202732 kb
Host smart-a3827cc7-a18d-4d6b-a7de-39c2d43f7ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114990316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.114990316
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1598905952
Short name T610
Test name
Test status
Simulation time 45269841349 ps
CPU time 49.61 seconds
Started May 09 02:52:52 PM PDT 24
Finished May 09 02:53:43 PM PDT 24
Peak memory 202144 kb
Host smart-7a5646e0-2a9e-4ede-baca-6200911504f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598905952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1598905952
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2172515105
Short name T91
Test name
Test status
Simulation time 4845711939 ps
CPU time 7.56 seconds
Started May 09 02:52:53 PM PDT 24
Finished May 09 02:53:02 PM PDT 24
Peak memory 202148 kb
Host smart-2cd4e70e-ea22-4ffa-ac7b-fef257f3399d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172515105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2172515105
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.842320090
Short name T540
Test name
Test status
Simulation time 5836439916 ps
CPU time 4.36 seconds
Started May 09 02:52:52 PM PDT 24
Finished May 09 02:52:57 PM PDT 24
Peak memory 202132 kb
Host smart-b305de10-517c-4dd4-a468-b23c2c80d3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842320090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.842320090
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.299391904
Short name T639
Test name
Test status
Simulation time 169018571996 ps
CPU time 94.38 seconds
Started May 09 02:53:03 PM PDT 24
Finished May 09 02:54:38 PM PDT 24
Peak memory 202312 kb
Host smart-dac7059a-4059-4c0c-a286-04b7c793a3b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299391904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
299391904
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.152932189
Short name T149
Test name
Test status
Simulation time 156693339382 ps
CPU time 57.59 seconds
Started May 09 02:52:52 PM PDT 24
Finished May 09 02:53:50 PM PDT 24
Peak memory 210580 kb
Host smart-44ea6a84-3456-4878-9e4a-8a661983bb97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152932189 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.152932189
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3092829525
Short name T600
Test name
Test status
Simulation time 309223789 ps
CPU time 0.8 seconds
Started May 09 02:50:50 PM PDT 24
Finished May 09 02:50:56 PM PDT 24
Peak memory 202000 kb
Host smart-7afa6b9b-0401-4251-878e-186095c88749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092829525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3092829525
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3621749187
Short name T591
Test name
Test status
Simulation time 185137788914 ps
CPU time 415.89 seconds
Started May 09 02:50:49 PM PDT 24
Finished May 09 02:57:51 PM PDT 24
Peak memory 202424 kb
Host smart-2375a8d7-ff3f-40e0-b678-8a78aeae5b0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621749187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3621749187
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.4237039969
Short name T317
Test name
Test status
Simulation time 335221394111 ps
CPU time 387.54 seconds
Started May 09 02:50:52 PM PDT 24
Finished May 09 02:57:24 PM PDT 24
Peak memory 202524 kb
Host smart-ca559129-0447-4879-860d-9f9bd6ade59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237039969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.4237039969
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1850179702
Short name T614
Test name
Test status
Simulation time 486489087768 ps
CPU time 1181.47 seconds
Started May 09 02:50:49 PM PDT 24
Finished May 09 03:10:37 PM PDT 24
Peak memory 202304 kb
Host smart-1cc550a9-1aa6-46e7-8fe5-b91af06139fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850179702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1850179702
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1936778503
Short name T704
Test name
Test status
Simulation time 169397903488 ps
CPU time 398.16 seconds
Started May 09 02:50:54 PM PDT 24
Finished May 09 02:57:35 PM PDT 24
Peak memory 202452 kb
Host smart-11e62733-e4e2-4f43-9716-646539f8dd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936778503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1936778503
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1424431704
Short name T11
Test name
Test status
Simulation time 162027448298 ps
CPU time 358.04 seconds
Started May 09 02:50:49 PM PDT 24
Finished May 09 02:56:53 PM PDT 24
Peak memory 202304 kb
Host smart-6c947c40-1bce-4c99-b64b-5850811eb1c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424431704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1424431704
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1572643959
Short name T256
Test name
Test status
Simulation time 518761454922 ps
CPU time 1120.62 seconds
Started May 09 02:50:48 PM PDT 24
Finished May 09 03:09:35 PM PDT 24
Peak memory 202448 kb
Host smart-8e028f65-f946-4c48-85aa-e3324de533d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572643959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1572643959
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1829918207
Short name T376
Test name
Test status
Simulation time 196274694627 ps
CPU time 104.25 seconds
Started May 09 02:50:52 PM PDT 24
Finished May 09 02:52:40 PM PDT 24
Peak memory 202408 kb
Host smart-563cac83-15c3-4ce1-871f-d8a6f3c399e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829918207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1829918207
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1101900644
Short name T539
Test name
Test status
Simulation time 101984423470 ps
CPU time 363.04 seconds
Started May 09 02:50:49 PM PDT 24
Finished May 09 02:56:58 PM PDT 24
Peak memory 202760 kb
Host smart-ee1def7d-35e6-4670-9bc2-65ea9fdb32f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101900644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1101900644
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2697439705
Short name T481
Test name
Test status
Simulation time 28947858549 ps
CPU time 19.15 seconds
Started May 09 02:50:50 PM PDT 24
Finished May 09 02:51:15 PM PDT 24
Peak memory 202164 kb
Host smart-435ddae4-6f90-48dc-b819-325990a81eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697439705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2697439705
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1392466485
Short name T172
Test name
Test status
Simulation time 4900496688 ps
CPU time 6.13 seconds
Started May 09 02:50:48 PM PDT 24
Finished May 09 02:51:01 PM PDT 24
Peak memory 202148 kb
Host smart-f642d5d8-eaa4-4ac8-aab8-9e170b7a851f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392466485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1392466485
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.4294697723
Short name T87
Test name
Test status
Simulation time 3751652515 ps
CPU time 8.84 seconds
Started May 09 02:50:50 PM PDT 24
Finished May 09 02:51:04 PM PDT 24
Peak memory 217952 kb
Host smart-681f3a2e-6fd4-46eb-ba3e-771db6a10140
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294697723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.4294697723
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.4179872982
Short name T373
Test name
Test status
Simulation time 5873288715 ps
CPU time 5.79 seconds
Started May 09 02:50:49 PM PDT 24
Finished May 09 02:51:00 PM PDT 24
Peak memory 202096 kb
Host smart-f394f566-4e64-4e01-b119-ba0b50c3cf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179872982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.4179872982
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2766271755
Short name T503
Test name
Test status
Simulation time 35083377002 ps
CPU time 80.91 seconds
Started May 09 02:50:49 PM PDT 24
Finished May 09 02:52:16 PM PDT 24
Peak memory 202132 kb
Host smart-6c678b4e-80e6-4864-afbe-a0f6a2c84c5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766271755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2766271755
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2906447547
Short name T558
Test name
Test status
Simulation time 44816955672 ps
CPU time 23.2 seconds
Started May 09 02:50:51 PM PDT 24
Finished May 09 02:51:19 PM PDT 24
Peak memory 210696 kb
Host smart-a5dd37dc-ecc7-4271-9131-0e29e3883372
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906447547 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2906447547
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2226598392
Short name T471
Test name
Test status
Simulation time 385062892 ps
CPU time 0.79 seconds
Started May 09 02:53:03 PM PDT 24
Finished May 09 02:53:05 PM PDT 24
Peak memory 201968 kb
Host smart-37d928de-868a-4f66-85b4-1ac3b5fc34c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226598392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2226598392
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2101916442
Short name T306
Test name
Test status
Simulation time 552974884770 ps
CPU time 864.43 seconds
Started May 09 02:53:05 PM PDT 24
Finished May 09 03:07:31 PM PDT 24
Peak memory 202304 kb
Host smart-15b4b03a-7c6d-4e52-b034-b3662c104b4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101916442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2101916442
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.483163867
Short name T751
Test name
Test status
Simulation time 166326108012 ps
CPU time 99.56 seconds
Started May 09 02:53:04 PM PDT 24
Finished May 09 02:54:45 PM PDT 24
Peak memory 202332 kb
Host smart-66acfa92-87a5-4fd7-af95-a7bb036b733c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483163867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.483163867
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2871205783
Short name T707
Test name
Test status
Simulation time 327907777984 ps
CPU time 202.48 seconds
Started May 09 02:53:04 PM PDT 24
Finished May 09 02:56:29 PM PDT 24
Peak memory 202264 kb
Host smart-f0b1c0ad-ceea-41f4-8b9d-e6a6ac7b607e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871205783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2871205783
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1263774661
Short name T408
Test name
Test status
Simulation time 163222082917 ps
CPU time 259.97 seconds
Started May 09 02:53:05 PM PDT 24
Finished May 09 02:57:27 PM PDT 24
Peak memory 202348 kb
Host smart-a0e21634-fbf0-4097-b9e9-29abac4cf60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263774661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1263774661
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.4244791724
Short name T46
Test name
Test status
Simulation time 154389490426 ps
CPU time 387.7 seconds
Started May 09 02:53:26 PM PDT 24
Finished May 09 02:59:55 PM PDT 24
Peak memory 202420 kb
Host smart-721036b6-eae5-4a68-855c-fbdc9fc9f85a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244791724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.4244791724
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3716095807
Short name T336
Test name
Test status
Simulation time 179377747302 ps
CPU time 388.77 seconds
Started May 09 02:53:04 PM PDT 24
Finished May 09 02:59:34 PM PDT 24
Peak memory 202424 kb
Host smart-b59e06cd-cb06-4458-b248-e684c887e6a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716095807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3716095807
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.843794888
Short name T438
Test name
Test status
Simulation time 210443746644 ps
CPU time 133.2 seconds
Started May 09 02:53:03 PM PDT 24
Finished May 09 02:55:18 PM PDT 24
Peak memory 202296 kb
Host smart-aa80ea64-05ac-410d-a0d2-d1708c3ba82e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843794888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.843794888
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.4044873318
Short name T213
Test name
Test status
Simulation time 80783802719 ps
CPU time 391.64 seconds
Started May 09 02:53:03 PM PDT 24
Finished May 09 02:59:36 PM PDT 24
Peak memory 202700 kb
Host smart-4414b188-1170-456b-b7d2-2873f3e14b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044873318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.4044873318
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2615998909
Short name T458
Test name
Test status
Simulation time 33934090859 ps
CPU time 13.39 seconds
Started May 09 02:53:06 PM PDT 24
Finished May 09 02:53:21 PM PDT 24
Peak memory 202160 kb
Host smart-59bdc11d-56e2-4f02-ae70-2cb1cd1899eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615998909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2615998909
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3855987531
Short name T653
Test name
Test status
Simulation time 2826124258 ps
CPU time 7.27 seconds
Started May 09 02:53:04 PM PDT 24
Finished May 09 02:53:12 PM PDT 24
Peak memory 202132 kb
Host smart-070b2108-05d4-4b7b-b09f-cde7f5ce0279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855987531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3855987531
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1363582848
Short name T367
Test name
Test status
Simulation time 5884584617 ps
CPU time 14.61 seconds
Started May 09 02:53:05 PM PDT 24
Finished May 09 02:53:21 PM PDT 24
Peak memory 202184 kb
Host smart-58a12c84-7d91-427a-8657-a3fe7e533e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363582848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1363582848
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1079559160
Short name T339
Test name
Test status
Simulation time 70704228640 ps
CPU time 318.2 seconds
Started May 09 02:53:04 PM PDT 24
Finished May 09 02:58:24 PM PDT 24
Peak memory 211072 kb
Host smart-f7ce8232-07f4-452c-b7e1-a147b9a1b6b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079559160 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1079559160
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3235701370
Short name T686
Test name
Test status
Simulation time 371707424 ps
CPU time 1.46 seconds
Started May 09 02:53:14 PM PDT 24
Finished May 09 02:53:17 PM PDT 24
Peak memory 202044 kb
Host smart-e2e1f17c-857a-456a-8014-54d9553ff6b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235701370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3235701370
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1471875667
Short name T239
Test name
Test status
Simulation time 511024675985 ps
CPU time 428.64 seconds
Started May 09 02:53:04 PM PDT 24
Finished May 09 03:00:14 PM PDT 24
Peak memory 202380 kb
Host smart-fb324f29-06cc-4657-957f-5603c5a98e16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471875667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1471875667
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3684705666
Short name T729
Test name
Test status
Simulation time 337064526584 ps
CPU time 192.82 seconds
Started May 09 02:53:04 PM PDT 24
Finished May 09 02:56:19 PM PDT 24
Peak memory 202420 kb
Host smart-c160b347-8e92-4d7c-955b-6c96de38fa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684705666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3684705666
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1543683866
Short name T738
Test name
Test status
Simulation time 487833848313 ps
CPU time 1051.18 seconds
Started May 09 02:53:03 PM PDT 24
Finished May 09 03:10:35 PM PDT 24
Peak memory 202252 kb
Host smart-fd4d3c97-bdb5-43f9-a4b2-fd09fd98f9c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543683866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1543683866
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3726740803
Short name T727
Test name
Test status
Simulation time 170840692164 ps
CPU time 104.28 seconds
Started May 09 02:53:05 PM PDT 24
Finished May 09 02:54:51 PM PDT 24
Peak memory 202348 kb
Host smart-7b18289f-b7d7-4582-9760-7742e1520f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726740803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3726740803
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2487333927
Short name T405
Test name
Test status
Simulation time 490270391340 ps
CPU time 1122.03 seconds
Started May 09 02:53:04 PM PDT 24
Finished May 09 03:11:48 PM PDT 24
Peak memory 202360 kb
Host smart-8e63ce7a-6382-4ae1-9564-2841a0a29578
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487333927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2487333927
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2630144918
Short name T601
Test name
Test status
Simulation time 557426505039 ps
CPU time 684.45 seconds
Started May 09 02:53:04 PM PDT 24
Finished May 09 03:04:29 PM PDT 24
Peak memory 202444 kb
Host smart-ac4490ad-6127-46d3-8d43-4a9d9b4dca07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630144918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2630144918
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.593569616
Short name T386
Test name
Test status
Simulation time 584902612894 ps
CPU time 665.06 seconds
Started May 09 02:53:05 PM PDT 24
Finished May 09 03:04:12 PM PDT 24
Peak memory 202340 kb
Host smart-5f8c9763-e27a-49a5-97c9-40cd4c02e8d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593569616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.593569616
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1952601012
Short name T521
Test name
Test status
Simulation time 103332486389 ps
CPU time 488.2 seconds
Started May 09 02:53:24 PM PDT 24
Finished May 09 03:01:33 PM PDT 24
Peak memory 202696 kb
Host smart-c4b6beb6-4ef6-4d2b-b43d-6fd43e6b8855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952601012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1952601012
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1570712521
Short name T516
Test name
Test status
Simulation time 32915809101 ps
CPU time 77.79 seconds
Started May 09 02:53:14 PM PDT 24
Finished May 09 02:54:34 PM PDT 24
Peak memory 202148 kb
Host smart-e2eb279b-43f6-4aff-9175-1aab8bc37918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570712521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1570712521
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1601816407
Short name T414
Test name
Test status
Simulation time 4788543117 ps
CPU time 6.62 seconds
Started May 09 02:53:16 PM PDT 24
Finished May 09 02:53:24 PM PDT 24
Peak memory 202140 kb
Host smart-4003877b-0033-4946-9296-acf6a45f367e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601816407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1601816407
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1431422435
Short name T388
Test name
Test status
Simulation time 6105356145 ps
CPU time 8 seconds
Started May 09 02:53:05 PM PDT 24
Finished May 09 02:53:15 PM PDT 24
Peak memory 202132 kb
Host smart-00db7d01-36bb-4e0a-bdbb-0d39e66d5162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431422435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1431422435
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1068972392
Short name T494
Test name
Test status
Simulation time 237404492754 ps
CPU time 389.05 seconds
Started May 09 02:53:15 PM PDT 24
Finished May 09 02:59:46 PM PDT 24
Peak memory 210864 kb
Host smart-1c7977d2-323b-4883-b096-a70dcf303e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068972392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1068972392
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1142939900
Short name T790
Test name
Test status
Simulation time 362744006002 ps
CPU time 310.57 seconds
Started May 09 02:53:22 PM PDT 24
Finished May 09 02:58:34 PM PDT 24
Peak memory 211100 kb
Host smart-35c58157-7ca6-487d-9937-875c15620764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142939900 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1142939900
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2962191926
Short name T525
Test name
Test status
Simulation time 339807956 ps
CPU time 1.39 seconds
Started May 09 02:53:18 PM PDT 24
Finished May 09 02:53:20 PM PDT 24
Peak memory 201976 kb
Host smart-d9c91010-1ffe-4658-8561-4ab8785a2fc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962191926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2962191926
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1119353235
Short name T749
Test name
Test status
Simulation time 329628970637 ps
CPU time 194.96 seconds
Started May 09 02:53:22 PM PDT 24
Finished May 09 02:56:38 PM PDT 24
Peak memory 202344 kb
Host smart-98196b85-3b6d-472c-b683-a625ca0d7342
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119353235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1119353235
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2334784944
Short name T145
Test name
Test status
Simulation time 191872898160 ps
CPU time 54.66 seconds
Started May 09 02:53:19 PM PDT 24
Finished May 09 02:54:15 PM PDT 24
Peak memory 202300 kb
Host smart-b8070b10-f3b7-4160-aa27-3d52c1d5718a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334784944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2334784944
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3113357955
Short name T283
Test name
Test status
Simulation time 326178364565 ps
CPU time 206.12 seconds
Started May 09 02:53:23 PM PDT 24
Finished May 09 02:56:49 PM PDT 24
Peak memory 202356 kb
Host smart-9ba23725-7cdb-46d5-8efb-2d3ca0ff403e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113357955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3113357955
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2848108660
Short name T156
Test name
Test status
Simulation time 168732051492 ps
CPU time 31.27 seconds
Started May 09 02:53:17 PM PDT 24
Finished May 09 02:53:49 PM PDT 24
Peak memory 202312 kb
Host smart-95c9f530-d7ae-4730-b083-8771d7a9f099
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848108660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2848108660
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.4237446176
Short name T185
Test name
Test status
Simulation time 328930331879 ps
CPU time 67.29 seconds
Started May 09 02:53:14 PM PDT 24
Finished May 09 02:54:22 PM PDT 24
Peak memory 202348 kb
Host smart-a10629b2-40d3-477b-b8da-b3c23f39b183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237446176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4237446176
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1338980110
Short name T757
Test name
Test status
Simulation time 165637765594 ps
CPU time 81.84 seconds
Started May 09 02:53:16 PM PDT 24
Finished May 09 02:54:39 PM PDT 24
Peak memory 202284 kb
Host smart-3569a495-ef6c-4e7b-b255-5bb6d8d65fb4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338980110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1338980110
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3198702382
Short name T308
Test name
Test status
Simulation time 348536720861 ps
CPU time 409.61 seconds
Started May 09 02:53:15 PM PDT 24
Finished May 09 03:00:06 PM PDT 24
Peak memory 202292 kb
Host smart-e39d8c5e-4711-4cc3-a762-07cd2ede08e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198702382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3198702382
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2304252530
Short name T579
Test name
Test status
Simulation time 204789975091 ps
CPU time 256.08 seconds
Started May 09 02:53:22 PM PDT 24
Finished May 09 02:57:39 PM PDT 24
Peak memory 202312 kb
Host smart-02c1a492-1386-4c8e-80c7-18c8477eefce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304252530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2304252530
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3042685623
Short name T505
Test name
Test status
Simulation time 83496432346 ps
CPU time 437.58 seconds
Started May 09 02:53:15 PM PDT 24
Finished May 09 03:00:34 PM PDT 24
Peak memory 202780 kb
Host smart-db2c02a8-85f1-49fe-967f-8e5c703d0472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042685623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3042685623
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.46146073
Short name T360
Test name
Test status
Simulation time 24574649378 ps
CPU time 14.12 seconds
Started May 09 02:53:15 PM PDT 24
Finished May 09 02:53:31 PM PDT 24
Peak memory 202192 kb
Host smart-d2eefc8c-7274-46f6-9047-9de011d14832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46146073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.46146073
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3415964777
Short name T776
Test name
Test status
Simulation time 2919331026 ps
CPU time 1.77 seconds
Started May 09 02:53:16 PM PDT 24
Finished May 09 02:53:19 PM PDT 24
Peak memory 202392 kb
Host smart-1759504d-bf64-46de-99f4-084a5812b114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415964777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3415964777
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.511112616
Short name T731
Test name
Test status
Simulation time 6026431350 ps
CPU time 2.41 seconds
Started May 09 02:53:14 PM PDT 24
Finished May 09 02:53:18 PM PDT 24
Peak memory 202132 kb
Host smart-215cb51b-b2e7-4e63-88a5-e7958ee82a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511112616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.511112616
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3858460100
Short name T287
Test name
Test status
Simulation time 338666818642 ps
CPU time 759.14 seconds
Started May 09 02:53:22 PM PDT 24
Finished May 09 03:06:02 PM PDT 24
Peak memory 202344 kb
Host smart-d71f7fa5-fd5d-4800-86a7-57d1bab87860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858460100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3858460100
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.817761036
Short name T349
Test name
Test status
Simulation time 99683615205 ps
CPU time 295.69 seconds
Started May 09 02:53:15 PM PDT 24
Finished May 09 02:58:12 PM PDT 24
Peak memory 211016 kb
Host smart-30037591-f179-4430-a201-290d501f84d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817761036 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.817761036
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.299927050
Short name T369
Test name
Test status
Simulation time 309555626 ps
CPU time 0.8 seconds
Started May 09 02:53:27 PM PDT 24
Finished May 09 02:53:28 PM PDT 24
Peak memory 201968 kb
Host smart-a552fb23-c73d-40fa-86f6-c346774a6549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299927050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.299927050
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1866668185
Short name T250
Test name
Test status
Simulation time 518161928299 ps
CPU time 975.37 seconds
Started May 09 02:53:26 PM PDT 24
Finished May 09 03:09:42 PM PDT 24
Peak memory 202352 kb
Host smart-b2b89b6f-0929-45b2-9758-32bed3d914d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866668185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1866668185
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1393574543
Short name T164
Test name
Test status
Simulation time 372904992764 ps
CPU time 162.48 seconds
Started May 09 02:53:24 PM PDT 24
Finished May 09 02:56:07 PM PDT 24
Peak memory 202388 kb
Host smart-4fb7751e-c7fa-4c16-8cf8-f6dcf76e2f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393574543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1393574543
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2925463301
Short name T254
Test name
Test status
Simulation time 486062255258 ps
CPU time 321.59 seconds
Started May 09 02:53:25 PM PDT 24
Finished May 09 02:58:47 PM PDT 24
Peak memory 202424 kb
Host smart-bfa99659-e9a2-4f0e-b7de-bc2c666a5659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925463301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2925463301
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.952015023
Short name T201
Test name
Test status
Simulation time 490500625098 ps
CPU time 288.15 seconds
Started May 09 02:53:25 PM PDT 24
Finished May 09 02:58:14 PM PDT 24
Peak memory 202348 kb
Host smart-720b7d09-6fc8-4cfe-b7d6-9d55fc99d8f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=952015023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.952015023
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2113997711
Short name T689
Test name
Test status
Simulation time 338296379518 ps
CPU time 384.06 seconds
Started May 09 02:53:26 PM PDT 24
Finished May 09 02:59:51 PM PDT 24
Peak memory 202276 kb
Host smart-8c1bbd8a-7404-4a7e-b57a-43310171ec5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113997711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2113997711
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1164864972
Short name T507
Test name
Test status
Simulation time 325737761456 ps
CPU time 211.31 seconds
Started May 09 02:53:26 PM PDT 24
Finished May 09 02:56:58 PM PDT 24
Peak memory 202280 kb
Host smart-d1b3163e-bcc2-4752-9d64-a08744799e2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164864972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1164864972
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3173673955
Short name T797
Test name
Test status
Simulation time 642771304422 ps
CPU time 1482.37 seconds
Started May 09 02:53:26 PM PDT 24
Finished May 09 03:18:09 PM PDT 24
Peak memory 202428 kb
Host smart-978ce340-ebee-4aba-9618-df292b1c1e22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173673955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3173673955
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1574783963
Short name T574
Test name
Test status
Simulation time 597196082143 ps
CPU time 366.69 seconds
Started May 09 02:53:27 PM PDT 24
Finished May 09 02:59:35 PM PDT 24
Peak memory 202324 kb
Host smart-27410abe-bae1-4de2-805b-01bd6c0591f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574783963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1574783963
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.587179479
Short name T608
Test name
Test status
Simulation time 85667240175 ps
CPU time 312.18 seconds
Started May 09 02:53:28 PM PDT 24
Finished May 09 02:58:41 PM PDT 24
Peak memory 202692 kb
Host smart-3e3b0d69-3bd2-42c6-b9f7-c9a5d1acf59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587179479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.587179479
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.21115715
Short name T102
Test name
Test status
Simulation time 39828187232 ps
CPU time 89.76 seconds
Started May 09 02:53:27 PM PDT 24
Finished May 09 02:54:57 PM PDT 24
Peak memory 202156 kb
Host smart-0f4026c1-f3be-453b-acf1-dbd3a1ddef01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21115715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.21115715
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2587809559
Short name T430
Test name
Test status
Simulation time 5311367961 ps
CPU time 1.89 seconds
Started May 09 02:53:20 PM PDT 24
Finished May 09 02:53:22 PM PDT 24
Peak memory 202168 kb
Host smart-06836f4a-ceb4-4826-a8e6-76c13fadbb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587809559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2587809559
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3817640096
Short name T176
Test name
Test status
Simulation time 5987720009 ps
CPU time 15.36 seconds
Started May 09 02:53:26 PM PDT 24
Finished May 09 02:53:42 PM PDT 24
Peak memory 202196 kb
Host smart-1bbcf368-09f6-4686-a911-b172a0d6ecd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817640096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3817640096
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1754387280
Short name T691
Test name
Test status
Simulation time 165168816115 ps
CPU time 362.77 seconds
Started May 09 02:53:26 PM PDT 24
Finished May 09 02:59:30 PM PDT 24
Peak memory 202256 kb
Host smart-18d000c7-ab46-4d78-987a-234cce4282ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754387280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1754387280
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1341110029
Short name T58
Test name
Test status
Simulation time 1411851918223 ps
CPU time 319.41 seconds
Started May 09 02:53:24 PM PDT 24
Finished May 09 02:58:44 PM PDT 24
Peak memory 212024 kb
Host smart-ae4e8822-32b5-4b9d-9b0a-f33580b2e51e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341110029 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1341110029
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1870340119
Short name T604
Test name
Test status
Simulation time 341727065 ps
CPU time 0.99 seconds
Started May 09 02:53:35 PM PDT 24
Finished May 09 02:53:37 PM PDT 24
Peak memory 202068 kb
Host smart-b04d26cd-adbd-4fa5-952e-cacf2f83bddb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870340119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1870340119
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3753881093
Short name T235
Test name
Test status
Simulation time 330963450443 ps
CPU time 837.3 seconds
Started May 09 02:53:35 PM PDT 24
Finished May 09 03:07:33 PM PDT 24
Peak memory 202380 kb
Host smart-127d42f3-5c7f-4110-9abf-463a7daa4ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753881093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3753881093
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.911311781
Short name T730
Test name
Test status
Simulation time 160723081251 ps
CPU time 56 seconds
Started May 09 02:53:35 PM PDT 24
Finished May 09 02:54:32 PM PDT 24
Peak memory 202292 kb
Host smart-b391fa84-aa85-4e05-bf68-00aa61e81684
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=911311781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.911311781
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1168438455
Short name T232
Test name
Test status
Simulation time 157673530498 ps
CPU time 21.75 seconds
Started May 09 02:53:34 PM PDT 24
Finished May 09 02:53:57 PM PDT 24
Peak memory 202300 kb
Host smart-e3d4644d-3ac5-4244-be01-7410879bad7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168438455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1168438455
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.584250712
Short name T512
Test name
Test status
Simulation time 167812582798 ps
CPU time 97.45 seconds
Started May 09 02:53:35 PM PDT 24
Finished May 09 02:55:14 PM PDT 24
Peak memory 202352 kb
Host smart-bd44fab7-01d2-4ba0-b0db-e9ccbfc0f2d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=584250712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.584250712
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3309623645
Short name T743
Test name
Test status
Simulation time 377722160848 ps
CPU time 889.61 seconds
Started May 09 02:53:37 PM PDT 24
Finished May 09 03:08:28 PM PDT 24
Peak memory 202344 kb
Host smart-3fbb91ea-11c2-4531-9033-9f71c49db98e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309623645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3309623645
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2728166169
Short name T418
Test name
Test status
Simulation time 194104382702 ps
CPU time 443.68 seconds
Started May 09 02:53:35 PM PDT 24
Finished May 09 03:01:00 PM PDT 24
Peak memory 202252 kb
Host smart-6cd01ff7-11d8-46bb-9581-7eba21cf1d3f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728166169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2728166169
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.4014061518
Short name T674
Test name
Test status
Simulation time 87928115378 ps
CPU time 382.26 seconds
Started May 09 02:53:36 PM PDT 24
Finished May 09 03:00:00 PM PDT 24
Peak memory 202676 kb
Host smart-dfc829be-c5c2-46fb-b935-b5637b5f5a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014061518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.4014061518
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1839651753
Short name T563
Test name
Test status
Simulation time 24162265116 ps
CPU time 56.63 seconds
Started May 09 02:53:39 PM PDT 24
Finished May 09 02:54:36 PM PDT 24
Peak memory 202156 kb
Host smart-924e3e37-251c-4f01-9110-7c9f097325d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839651753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1839651753
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.919185645
Short name T495
Test name
Test status
Simulation time 5352132761 ps
CPU time 9.45 seconds
Started May 09 02:53:35 PM PDT 24
Finished May 09 02:53:46 PM PDT 24
Peak memory 202200 kb
Host smart-1b3194ba-06f9-4c5d-9140-3878c8c79763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919185645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.919185645
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3965719692
Short name T420
Test name
Test status
Simulation time 5755606116 ps
CPU time 4.31 seconds
Started May 09 02:53:26 PM PDT 24
Finished May 09 02:53:32 PM PDT 24
Peak memory 202088 kb
Host smart-21ae2e59-98df-4489-b099-f69765c6118a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965719692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3965719692
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2473065029
Short name T169
Test name
Test status
Simulation time 170920043442 ps
CPU time 89.43 seconds
Started May 09 02:53:35 PM PDT 24
Finished May 09 02:55:06 PM PDT 24
Peak memory 202344 kb
Host smart-02734e65-e07f-4ca2-8a52-1d14939c7bd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473065029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2473065029
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.100352199
Short name T14
Test name
Test status
Simulation time 381249172 ps
CPU time 0.71 seconds
Started May 09 02:53:48 PM PDT 24
Finished May 09 02:53:50 PM PDT 24
Peak memory 202048 kb
Host smart-4498c83f-59f7-4c3f-b527-b21cc54f6882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100352199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.100352199
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3566185723
Short name T95
Test name
Test status
Simulation time 176866383733 ps
CPU time 380.81 seconds
Started May 09 02:53:46 PM PDT 24
Finished May 09 03:00:08 PM PDT 24
Peak memory 202352 kb
Host smart-b1031ac7-baa1-4739-9258-fb1c357ce7da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566185723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3566185723
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1454038561
Short name T209
Test name
Test status
Simulation time 551165596216 ps
CPU time 339.79 seconds
Started May 09 02:53:48 PM PDT 24
Finished May 09 02:59:29 PM PDT 24
Peak memory 202376 kb
Host smart-52b51939-0864-4705-84af-22d8704bf187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454038561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1454038561
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1368785682
Short name T184
Test name
Test status
Simulation time 168143108239 ps
CPU time 97.11 seconds
Started May 09 02:53:35 PM PDT 24
Finished May 09 02:55:13 PM PDT 24
Peak memory 202328 kb
Host smart-60bc742d-fc3c-412e-a20b-25224233aa30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368785682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1368785682
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.4127696207
Short name T229
Test name
Test status
Simulation time 335062448302 ps
CPU time 390.16 seconds
Started May 09 02:53:37 PM PDT 24
Finished May 09 03:00:08 PM PDT 24
Peak memory 202276 kb
Host smart-8159e1e2-64b7-43ab-95b7-8d6fda4491c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127696207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4127696207
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.826415167
Short name T699
Test name
Test status
Simulation time 496484516028 ps
CPU time 1138.35 seconds
Started May 09 02:53:36 PM PDT 24
Finished May 09 03:12:36 PM PDT 24
Peak memory 202332 kb
Host smart-a8b8f342-f4b9-4dff-8af3-4e7007fdcce5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=826415167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.826415167
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1026521681
Short name T439
Test name
Test status
Simulation time 609474510868 ps
CPU time 708.39 seconds
Started May 09 02:53:52 PM PDT 24
Finished May 09 03:05:41 PM PDT 24
Peak memory 202304 kb
Host smart-1bd29f7f-496f-4d6c-b0a8-cdd82d4bcf38
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026521681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1026521681
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2429702693
Short name T688
Test name
Test status
Simulation time 21370397170 ps
CPU time 51.59 seconds
Started May 09 02:53:48 PM PDT 24
Finished May 09 02:54:41 PM PDT 24
Peak memory 202100 kb
Host smart-9e0d3d4a-68de-454b-aeeb-9d726aa8a7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429702693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2429702693
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2550182753
Short name T372
Test name
Test status
Simulation time 4684729218 ps
CPU time 1.89 seconds
Started May 09 02:53:52 PM PDT 24
Finished May 09 02:53:55 PM PDT 24
Peak memory 202140 kb
Host smart-b937812f-4f75-4c7b-83ad-9cc8c9dc869d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550182753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2550182753
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.4125769740
Short name T752
Test name
Test status
Simulation time 5798375276 ps
CPU time 14.67 seconds
Started May 09 02:53:35 PM PDT 24
Finished May 09 02:53:51 PM PDT 24
Peak memory 202192 kb
Host smart-a243a5d5-c73f-405f-be24-8541fb525bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125769740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.4125769740
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3666634334
Short name T263
Test name
Test status
Simulation time 332497505598 ps
CPU time 769.54 seconds
Started May 09 02:53:52 PM PDT 24
Finished May 09 03:06:43 PM PDT 24
Peak memory 202300 kb
Host smart-85a4f01f-d9fd-4b2f-b1e6-daa6f49e354f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666634334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3666634334
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2494959067
Short name T612
Test name
Test status
Simulation time 92078536880 ps
CPU time 207.18 seconds
Started May 09 02:53:47 PM PDT 24
Finished May 09 02:57:16 PM PDT 24
Peak memory 210668 kb
Host smart-9e754f81-f72f-488a-8053-b064f3dc91b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494959067 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2494959067
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2138969425
Short name T366
Test name
Test status
Simulation time 384918213 ps
CPU time 0.84 seconds
Started May 09 02:53:48 PM PDT 24
Finished May 09 02:53:50 PM PDT 24
Peak memory 202008 kb
Host smart-59e674f3-d92c-499e-b4fa-014f9cd3953c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138969425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2138969425
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1893518809
Short name T560
Test name
Test status
Simulation time 183395638975 ps
CPU time 57.29 seconds
Started May 09 02:53:48 PM PDT 24
Finished May 09 02:54:47 PM PDT 24
Peak memory 202312 kb
Host smart-99db4405-7bc3-4690-9853-8d7cc653b273
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893518809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1893518809
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.895409674
Short name T266
Test name
Test status
Simulation time 161094000486 ps
CPU time 98.16 seconds
Started May 09 02:53:47 PM PDT 24
Finished May 09 02:55:26 PM PDT 24
Peak memory 202260 kb
Host smart-d3f94190-1d93-431e-86d4-fb271ed192f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895409674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.895409674
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.699587335
Short name T532
Test name
Test status
Simulation time 331340275811 ps
CPU time 802.97 seconds
Started May 09 02:53:49 PM PDT 24
Finished May 09 03:07:13 PM PDT 24
Peak memory 202376 kb
Host smart-a311511f-614e-4a9a-abd6-37757abf8986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699587335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.699587335
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.986630126
Short name T732
Test name
Test status
Simulation time 327816087432 ps
CPU time 793.58 seconds
Started May 09 02:53:47 PM PDT 24
Finished May 09 03:07:02 PM PDT 24
Peak memory 202292 kb
Host smart-b8457897-4ee0-4b70-a443-a572fe3c78b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=986630126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.986630126
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.4201628122
Short name T276
Test name
Test status
Simulation time 488833686474 ps
CPU time 468.12 seconds
Started May 09 02:53:47 PM PDT 24
Finished May 09 03:01:36 PM PDT 24
Peak memory 202376 kb
Host smart-b25ca109-aa50-42e4-bc0f-52b333e158e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201628122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4201628122
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3657422188
Short name T122
Test name
Test status
Simulation time 166722935741 ps
CPU time 365.2 seconds
Started May 09 02:53:49 PM PDT 24
Finished May 09 02:59:56 PM PDT 24
Peak memory 202268 kb
Host smart-243b0490-0b9c-41cc-909f-f44ee2a511a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657422188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3657422188
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2306359306
Short name T322
Test name
Test status
Simulation time 341043832247 ps
CPU time 192.96 seconds
Started May 09 02:53:48 PM PDT 24
Finished May 09 02:57:03 PM PDT 24
Peak memory 202448 kb
Host smart-a6220eae-5b1a-4b63-9861-3f50bea0f6b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306359306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2306359306
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.410350522
Short name T555
Test name
Test status
Simulation time 407288140701 ps
CPU time 252.14 seconds
Started May 09 02:53:49 PM PDT 24
Finished May 09 02:58:02 PM PDT 24
Peak memory 202536 kb
Host smart-10972d37-d68e-4b93-9c3d-6da4ebb30e61
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410350522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.410350522
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.145316095
Short name T712
Test name
Test status
Simulation time 117441610088 ps
CPU time 370.1 seconds
Started May 09 02:53:46 PM PDT 24
Finished May 09 02:59:58 PM PDT 24
Peak memory 202760 kb
Host smart-93c32bbf-9bfb-46d6-913e-25548ad0b5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145316095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.145316095
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2978172846
Short name T708
Test name
Test status
Simulation time 42771097093 ps
CPU time 47.78 seconds
Started May 09 02:53:47 PM PDT 24
Finished May 09 02:54:36 PM PDT 24
Peak memory 202076 kb
Host smart-f9b9eefc-3a70-48f6-a130-11c33ef64897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978172846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2978172846
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1720012183
Short name T41
Test name
Test status
Simulation time 3792978211 ps
CPU time 5.08 seconds
Started May 09 02:53:51 PM PDT 24
Finished May 09 02:53:57 PM PDT 24
Peak memory 202172 kb
Host smart-c6d5e779-bd1e-4380-b6fe-641e00692ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720012183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1720012183
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1271481302
Short name T693
Test name
Test status
Simulation time 6202323527 ps
CPU time 4.34 seconds
Started May 09 02:53:52 PM PDT 24
Finished May 09 02:53:58 PM PDT 24
Peak memory 202144 kb
Host smart-ba0e4280-0cb2-40f4-a1b0-e6132e2aadeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271481302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1271481302
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2820630712
Short name T698
Test name
Test status
Simulation time 191641337967 ps
CPU time 438.6 seconds
Started May 09 02:53:47 PM PDT 24
Finished May 09 03:01:07 PM PDT 24
Peak memory 202368 kb
Host smart-93bdaf71-e2bf-4313-a48b-b4ffe61a3776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820630712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2820630712
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.4276228907
Short name T716
Test name
Test status
Simulation time 43913217730 ps
CPU time 125.61 seconds
Started May 09 02:53:46 PM PDT 24
Finished May 09 02:55:53 PM PDT 24
Peak memory 211088 kb
Host smart-4ba7d39c-39d7-41d4-9b20-e236cbb8bac3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276228907 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.4276228907
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.4193077798
Short name T584
Test name
Test status
Simulation time 437321859 ps
CPU time 1.11 seconds
Started May 09 02:53:58 PM PDT 24
Finished May 09 02:54:00 PM PDT 24
Peak memory 202008 kb
Host smart-c5fcc401-adf5-43ae-af74-876e23a2feaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193077798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.4193077798
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1742345720
Short name T634
Test name
Test status
Simulation time 170184673197 ps
CPU time 357.43 seconds
Started May 09 02:53:59 PM PDT 24
Finished May 09 02:59:58 PM PDT 24
Peak memory 202280 kb
Host smart-22eee63b-6d9d-4d35-b257-0b15009fc5c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742345720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1742345720
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.573001615
Short name T144
Test name
Test status
Simulation time 516369996221 ps
CPU time 298.84 seconds
Started May 09 02:53:59 PM PDT 24
Finished May 09 02:58:59 PM PDT 24
Peak memory 202544 kb
Host smart-a28a81ad-1344-4cb8-97cf-12b1d987bb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573001615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.573001615
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4239950769
Short name T178
Test name
Test status
Simulation time 494121542596 ps
CPU time 1084.87 seconds
Started May 09 02:53:57 PM PDT 24
Finished May 09 03:12:03 PM PDT 24
Peak memory 202308 kb
Host smart-37bd273f-5792-41ea-9937-e677f807fd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239950769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4239950769
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1952716663
Short name T669
Test name
Test status
Simulation time 327027865835 ps
CPU time 382.13 seconds
Started May 09 02:53:59 PM PDT 24
Finished May 09 03:00:22 PM PDT 24
Peak memory 202244 kb
Host smart-f11b70dd-31e8-47e0-a614-24bf04a9fe05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952716663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1952716663
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2885808163
Short name T192
Test name
Test status
Simulation time 333377049117 ps
CPU time 181.48 seconds
Started May 09 02:53:47 PM PDT 24
Finished May 09 02:56:50 PM PDT 24
Peak memory 202300 kb
Host smart-0fb105e7-02ab-4e96-87d9-98e4a46947eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885808163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2885808163
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1299985585
Short name T745
Test name
Test status
Simulation time 323414206858 ps
CPU time 751.47 seconds
Started May 09 02:53:58 PM PDT 24
Finished May 09 03:06:30 PM PDT 24
Peak memory 202288 kb
Host smart-62a9f7b4-5bf7-4344-8c64-d9ec15e2deab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299985585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1299985585
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2102178991
Short name T382
Test name
Test status
Simulation time 200162096294 ps
CPU time 212.9 seconds
Started May 09 02:53:58 PM PDT 24
Finished May 09 02:57:32 PM PDT 24
Peak memory 202284 kb
Host smart-be84620c-ea07-42e9-a0c2-55eaf005c70e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102178991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2102178991
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.649479797
Short name T659
Test name
Test status
Simulation time 85887441624 ps
CPU time 351.27 seconds
Started May 09 02:53:59 PM PDT 24
Finished May 09 02:59:52 PM PDT 24
Peak memory 202696 kb
Host smart-7810c261-364b-42e1-9318-f82ca4ad01a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649479797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.649479797
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1671064455
Short name T394
Test name
Test status
Simulation time 23858393485 ps
CPU time 14.6 seconds
Started May 09 02:53:58 PM PDT 24
Finished May 09 02:54:14 PM PDT 24
Peak memory 202128 kb
Host smart-13f8775d-346a-4baa-81ec-994462a64395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671064455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1671064455
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3878438442
Short name T759
Test name
Test status
Simulation time 5363980831 ps
CPU time 14.7 seconds
Started May 09 02:54:00 PM PDT 24
Finished May 09 02:54:15 PM PDT 24
Peak memory 202144 kb
Host smart-d809fe61-6d82-4dbd-a947-45aa69810a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878438442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3878438442
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.866607331
Short name T742
Test name
Test status
Simulation time 6016668188 ps
CPU time 3.38 seconds
Started May 09 02:53:48 PM PDT 24
Finished May 09 02:53:53 PM PDT 24
Peak memory 202148 kb
Host smart-891b6286-0133-427a-87f4-4b3bff16b95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866607331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.866607331
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.4084594525
Short name T424
Test name
Test status
Simulation time 17885140907 ps
CPU time 47.24 seconds
Started May 09 02:53:59 PM PDT 24
Finished May 09 02:54:48 PM PDT 24
Peak memory 202344 kb
Host smart-8d237c2a-c7a9-4af5-a023-3a9b1ab4cec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084594525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.4084594525
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3080852343
Short name T763
Test name
Test status
Simulation time 194789966807 ps
CPU time 142.48 seconds
Started May 09 02:53:58 PM PDT 24
Finished May 09 02:56:21 PM PDT 24
Peak memory 211116 kb
Host smart-6e51fcca-6d56-47f7-baa4-ea31338962a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080852343 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3080852343
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3822337945
Short name T750
Test name
Test status
Simulation time 536080129 ps
CPU time 0.89 seconds
Started May 09 02:54:11 PM PDT 24
Finished May 09 02:54:13 PM PDT 24
Peak memory 202056 kb
Host smart-17b0a653-cc75-43e4-b7ce-ecde7f5a9bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822337945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3822337945
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2165109475
Short name T258
Test name
Test status
Simulation time 189766181750 ps
CPU time 43.66 seconds
Started May 09 02:54:10 PM PDT 24
Finished May 09 02:54:55 PM PDT 24
Peak memory 202360 kb
Host smart-f083cb19-afbd-4f7d-9457-80a88d7aa5ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165109475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2165109475
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3038265290
Short name T261
Test name
Test status
Simulation time 162200101869 ps
CPU time 194.69 seconds
Started May 09 02:54:13 PM PDT 24
Finished May 09 02:57:28 PM PDT 24
Peak memory 202264 kb
Host smart-943caf92-5280-4e5b-943b-d338de628f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038265290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3038265290
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3239481824
Short name T303
Test name
Test status
Simulation time 163668171754 ps
CPU time 70.28 seconds
Started May 09 02:53:59 PM PDT 24
Finished May 09 02:55:11 PM PDT 24
Peak memory 202296 kb
Host smart-39331d7f-fb19-4f1e-b08c-8edbdef0b640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239481824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3239481824
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.6336144
Short name T202
Test name
Test status
Simulation time 326398226788 ps
CPU time 186.38 seconds
Started May 09 02:53:58 PM PDT 24
Finished May 09 02:57:05 PM PDT 24
Peak memory 202336 kb
Host smart-ee6141f4-2f21-409e-af99-086db2622cd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=6336144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt_
fixed.6336144
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3773374178
Short name T605
Test name
Test status
Simulation time 164560296830 ps
CPU time 200.28 seconds
Started May 09 02:53:59 PM PDT 24
Finished May 09 02:57:21 PM PDT 24
Peak memory 202308 kb
Host smart-af58ba21-910e-4aa8-bcd9-d5a36c8666f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773374178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3773374178
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1178430413
Short name T30
Test name
Test status
Simulation time 161732719868 ps
CPU time 383.77 seconds
Started May 09 02:53:57 PM PDT 24
Finished May 09 03:00:22 PM PDT 24
Peak memory 202240 kb
Host smart-1f04ac28-ab83-4228-a991-6cd824f96746
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178430413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1178430413
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.667802606
Short name T670
Test name
Test status
Simulation time 176031530083 ps
CPU time 102.03 seconds
Started May 09 02:53:58 PM PDT 24
Finished May 09 02:55:41 PM PDT 24
Peak memory 202412 kb
Host smart-bd202aa3-fc46-413f-8cd0-5dea53fa794d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667802606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.667802606
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3327240546
Short name T364
Test name
Test status
Simulation time 583977813788 ps
CPU time 1388.55 seconds
Started May 09 02:53:58 PM PDT 24
Finished May 09 03:17:08 PM PDT 24
Peak memory 202384 kb
Host smart-07749faa-a43b-4a5d-b84f-9465aa1b7bec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327240546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3327240546
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.569420009
Short name T106
Test name
Test status
Simulation time 130769897343 ps
CPU time 390.87 seconds
Started May 09 02:54:11 PM PDT 24
Finished May 09 03:00:43 PM PDT 24
Peak memory 202656 kb
Host smart-ecd0fefd-0e9e-43e8-8e5a-28fdb2eb691a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569420009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.569420009
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.4276625631
Short name T589
Test name
Test status
Simulation time 23277601669 ps
CPU time 6.08 seconds
Started May 09 02:54:09 PM PDT 24
Finished May 09 02:54:16 PM PDT 24
Peak memory 202120 kb
Host smart-b3bef1c5-a9b8-4870-9bff-161bc1a647bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276625631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.4276625631
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1829084821
Short name T515
Test name
Test status
Simulation time 3214793593 ps
CPU time 7.94 seconds
Started May 09 02:54:09 PM PDT 24
Finished May 09 02:54:18 PM PDT 24
Peak memory 202084 kb
Host smart-bb2db2a3-f0a2-4a87-8fc5-050078810921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829084821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1829084821
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.97384935
Short name T191
Test name
Test status
Simulation time 6003804722 ps
CPU time 1.82 seconds
Started May 09 02:53:59 PM PDT 24
Finished May 09 02:54:02 PM PDT 24
Peak memory 202168 kb
Host smart-69e4325d-abd6-43d5-a5a3-42535ca52d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97384935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.97384935
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3828456431
Short name T36
Test name
Test status
Simulation time 228497230708 ps
CPU time 121.39 seconds
Started May 09 02:54:10 PM PDT 24
Finished May 09 02:56:12 PM PDT 24
Peak memory 202348 kb
Host smart-c950a89c-cede-48ac-a334-663810b0b106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828456431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3828456431
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.438471401
Short name T348
Test name
Test status
Simulation time 64332453408 ps
CPU time 90.64 seconds
Started May 09 02:54:11 PM PDT 24
Finished May 09 02:55:42 PM PDT 24
Peak memory 210980 kb
Host smart-73aaca35-de6b-45c8-bb14-f6d34f8cf447
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438471401 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.438471401
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3271474984
Short name T400
Test name
Test status
Simulation time 385216012 ps
CPU time 0.67 seconds
Started May 09 02:54:20 PM PDT 24
Finished May 09 02:54:21 PM PDT 24
Peak memory 201996 kb
Host smart-d281af53-e0f8-44c2-822e-0c133b5d1fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271474984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3271474984
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2555643674
Short name T379
Test name
Test status
Simulation time 164614801210 ps
CPU time 354.17 seconds
Started May 09 02:54:11 PM PDT 24
Finished May 09 03:00:06 PM PDT 24
Peak memory 202348 kb
Host smart-e03a6b23-ad85-4523-945e-c23e5c84a6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555643674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2555643674
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1988103190
Short name T677
Test name
Test status
Simulation time 335518853729 ps
CPU time 785.23 seconds
Started May 09 02:54:11 PM PDT 24
Finished May 09 03:07:17 PM PDT 24
Peak memory 202312 kb
Host smart-aaecb413-5981-4036-a41b-512c6265acc8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988103190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1988103190
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1919890858
Short name T500
Test name
Test status
Simulation time 166465881989 ps
CPU time 266.32 seconds
Started May 09 02:54:10 PM PDT 24
Finished May 09 02:58:37 PM PDT 24
Peak memory 202424 kb
Host smart-9e8c9199-ca66-461a-9569-ad621adb7dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919890858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1919890858
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.4168982842
Short name T640
Test name
Test status
Simulation time 159871895151 ps
CPU time 388.11 seconds
Started May 09 02:54:10 PM PDT 24
Finished May 09 03:00:39 PM PDT 24
Peak memory 202248 kb
Host smart-4fd6f41a-31d9-41ef-8dda-2aade0b6e0af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168982842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.4168982842
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1530657156
Short name T404
Test name
Test status
Simulation time 605964936744 ps
CPU time 1333.49 seconds
Started May 09 02:54:11 PM PDT 24
Finished May 09 03:16:25 PM PDT 24
Peak memory 202396 kb
Host smart-91c0e171-7aeb-4ad7-8774-87d317be8594
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530657156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1530657156
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3502698675
Short name T114
Test name
Test status
Simulation time 121901170526 ps
CPU time 403.96 seconds
Started May 09 02:54:19 PM PDT 24
Finished May 09 03:01:04 PM PDT 24
Peak memory 202804 kb
Host smart-5d667662-8b83-4bba-a9e3-89e1cc31f501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502698675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3502698675
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.923901335
Short name T781
Test name
Test status
Simulation time 35766599091 ps
CPU time 12.61 seconds
Started May 09 02:54:20 PM PDT 24
Finished May 09 02:54:33 PM PDT 24
Peak memory 202180 kb
Host smart-d6dfe5ad-77e8-4bc0-a4b2-67d3d1193187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923901335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.923901335
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1991705546
Short name T356
Test name
Test status
Simulation time 5115491163 ps
CPU time 12.43 seconds
Started May 09 02:54:11 PM PDT 24
Finished May 09 02:54:24 PM PDT 24
Peak memory 202156 kb
Host smart-f079801e-315f-4bf8-8bcc-d2713c6b2385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991705546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1991705546
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2130759677
Short name T361
Test name
Test status
Simulation time 5710604080 ps
CPU time 7.55 seconds
Started May 09 02:54:10 PM PDT 24
Finished May 09 02:54:19 PM PDT 24
Peak memory 202080 kb
Host smart-8dc288f1-5cfc-4840-a3aa-1eca0bc3f909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130759677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2130759677
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2632882007
Short name T293
Test name
Test status
Simulation time 338311876729 ps
CPU time 384.42 seconds
Started May 09 02:54:21 PM PDT 24
Finished May 09 03:00:46 PM PDT 24
Peak memory 202160 kb
Host smart-336079c9-cb09-4e68-ac6f-82be8e749a47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632882007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2632882007
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3825256047
Short name T720
Test name
Test status
Simulation time 360437197 ps
CPU time 1.45 seconds
Started May 09 02:51:00 PM PDT 24
Finished May 09 02:51:05 PM PDT 24
Peak memory 202024 kb
Host smart-afd2c68d-8fb7-4efc-96e2-f92379671bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825256047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3825256047
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3029185313
Short name T325
Test name
Test status
Simulation time 537809816691 ps
CPU time 529.23 seconds
Started May 09 02:51:01 PM PDT 24
Finished May 09 02:59:56 PM PDT 24
Peak memory 202428 kb
Host smart-da5b0d41-e5a5-4413-a452-89ab9ff52771
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029185313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3029185313
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1799684810
Short name T304
Test name
Test status
Simulation time 332823605286 ps
CPU time 284.71 seconds
Started May 09 02:51:02 PM PDT 24
Finished May 09 02:55:52 PM PDT 24
Peak memory 202424 kb
Host smart-0772bf33-8c0d-4d9b-b229-a230e58570ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799684810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1799684810
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.4087956118
Short name T358
Test name
Test status
Simulation time 163203580101 ps
CPU time 128.05 seconds
Started May 09 02:51:03 PM PDT 24
Finished May 09 02:53:17 PM PDT 24
Peak memory 202300 kb
Host smart-5f06cedb-debf-4515-810d-4d7cc04c35eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087956118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.4087956118
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.199302918
Short name T454
Test name
Test status
Simulation time 329757929414 ps
CPU time 751.31 seconds
Started May 09 02:51:04 PM PDT 24
Finished May 09 03:03:41 PM PDT 24
Peak memory 202368 kb
Host smart-0755bd74-8680-481b-af1b-b6c577f34f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199302918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.199302918
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2287513960
Short name T482
Test name
Test status
Simulation time 168184765529 ps
CPU time 93.66 seconds
Started May 09 02:51:00 PM PDT 24
Finished May 09 02:52:38 PM PDT 24
Peak memory 202296 kb
Host smart-0339a214-ffe5-4e9c-8af6-b283b5447120
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287513960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2287513960
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3334493370
Short name T25
Test name
Test status
Simulation time 177225710550 ps
CPU time 112.4 seconds
Started May 09 02:51:01 PM PDT 24
Finished May 09 02:52:59 PM PDT 24
Peak memory 202280 kb
Host smart-426d4322-9c1a-48b1-a53e-30ff7120f708
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334493370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3334493370
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1868583932
Short name T501
Test name
Test status
Simulation time 417756117863 ps
CPU time 214.83 seconds
Started May 09 02:51:00 PM PDT 24
Finished May 09 02:54:39 PM PDT 24
Peak memory 202316 kb
Host smart-d7d6603a-b600-43bf-a6c9-042ef53f5372
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868583932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1868583932
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.435183385
Short name T412
Test name
Test status
Simulation time 89229671652 ps
CPU time 283.68 seconds
Started May 09 02:51:00 PM PDT 24
Finished May 09 02:55:47 PM PDT 24
Peak memory 202612 kb
Host smart-0c71230f-3a8b-4cfb-9c5d-0b87e4e8707d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435183385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.435183385
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3687551089
Short name T493
Test name
Test status
Simulation time 33858556613 ps
CPU time 79.52 seconds
Started May 09 02:51:09 PM PDT 24
Finished May 09 02:52:36 PM PDT 24
Peak memory 202156 kb
Host smart-9c6eec8a-5989-41fa-985f-21dd44ecf52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687551089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3687551089
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.532820714
Short name T642
Test name
Test status
Simulation time 4046925318 ps
CPU time 10.39 seconds
Started May 09 02:51:01 PM PDT 24
Finished May 09 02:51:16 PM PDT 24
Peak memory 202176 kb
Host smart-494cee2b-6b3c-46d3-8e7a-1e4220d34243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532820714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.532820714
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.244177229
Short name T413
Test name
Test status
Simulation time 5915258498 ps
CPU time 3.31 seconds
Started May 09 02:51:00 PM PDT 24
Finished May 09 02:51:07 PM PDT 24
Peak memory 202076 kb
Host smart-cfc82a12-9309-4eb0-b507-cb50bfe01734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244177229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.244177229
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1470958711
Short name T631
Test name
Test status
Simulation time 194835697513 ps
CPU time 1023.02 seconds
Started May 09 02:51:01 PM PDT 24
Finished May 09 03:08:09 PM PDT 24
Peak memory 212052 kb
Host smart-1a51e6ce-672d-427c-91c9-490a1294da8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470958711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1470958711
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2928272942
Short name T467
Test name
Test status
Simulation time 468506211 ps
CPU time 1.73 seconds
Started May 09 02:51:03 PM PDT 24
Finished May 09 02:51:10 PM PDT 24
Peak memory 202008 kb
Host smart-d2f9b25f-2c0e-48ad-8ad3-f346a879bf0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928272942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2928272942
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.740553014
Short name T451
Test name
Test status
Simulation time 488481185160 ps
CPU time 297.6 seconds
Started May 09 02:51:01 PM PDT 24
Finished May 09 02:56:04 PM PDT 24
Peak memory 202348 kb
Host smart-ba8e0d92-e537-4a02-b26d-c2517cc3a01d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=740553014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.740553014
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2796079173
Short name T401
Test name
Test status
Simulation time 162055696815 ps
CPU time 175.08 seconds
Started May 09 02:51:01 PM PDT 24
Finished May 09 02:54:02 PM PDT 24
Peak memory 202272 kb
Host smart-14ac619c-e712-4edd-9862-9230e636b54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796079173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2796079173
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.4100345224
Short name T502
Test name
Test status
Simulation time 332746670006 ps
CPU time 85.14 seconds
Started May 09 02:51:01 PM PDT 24
Finished May 09 02:52:32 PM PDT 24
Peak memory 202312 kb
Host smart-02086f4d-a355-497a-8e39-9df923a88f79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100345224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.4100345224
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3991412989
Short name T180
Test name
Test status
Simulation time 444579339202 ps
CPU time 557.4 seconds
Started May 09 02:51:01 PM PDT 24
Finished May 09 03:00:23 PM PDT 24
Peak memory 202288 kb
Host smart-dcc097f3-90ce-42ae-87b8-0c77751c2777
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991412989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3991412989
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1253626098
Short name T387
Test name
Test status
Simulation time 408736753322 ps
CPU time 223.01 seconds
Started May 09 02:51:01 PM PDT 24
Finished May 09 02:54:50 PM PDT 24
Peak memory 202256 kb
Host smart-fea9161c-8afa-4371-aa6f-0a856aea64c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253626098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1253626098
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2959518138
Short name T49
Test name
Test status
Simulation time 64688917633 ps
CPU time 359.45 seconds
Started May 09 02:51:02 PM PDT 24
Finished May 09 02:57:08 PM PDT 24
Peak memory 202752 kb
Host smart-b1f6f31f-da62-454d-922a-aef452ca77bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959518138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2959518138
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3884060133
Short name T396
Test name
Test status
Simulation time 34579177945 ps
CPU time 42.34 seconds
Started May 09 02:51:02 PM PDT 24
Finished May 09 02:51:49 PM PDT 24
Peak memory 202128 kb
Host smart-627477bc-d5db-4bc8-af44-9db516006000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884060133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3884060133
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1496751497
Short name T463
Test name
Test status
Simulation time 4536489355 ps
CPU time 11.82 seconds
Started May 09 02:51:12 PM PDT 24
Finished May 09 02:51:32 PM PDT 24
Peak memory 202176 kb
Host smart-4cb7bb9d-9c59-4331-93d1-bbdf4e960531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496751497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1496751497
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1917877495
Short name T755
Test name
Test status
Simulation time 5949163967 ps
CPU time 7.34 seconds
Started May 09 02:51:02 PM PDT 24
Finished May 09 02:51:15 PM PDT 24
Peak memory 202160 kb
Host smart-284eab82-017a-427f-bd51-c7b54c85a506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917877495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1917877495
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1841189361
Short name T327
Test name
Test status
Simulation time 619425794091 ps
CPU time 753.89 seconds
Started May 09 02:51:02 PM PDT 24
Finished May 09 03:03:42 PM PDT 24
Peak memory 213756 kb
Host smart-c4be630a-4f33-4f36-9ca8-6fbf6789debc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841189361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1841189361
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1965541802
Short name T473
Test name
Test status
Simulation time 550185870 ps
CPU time 0.98 seconds
Started May 09 02:51:06 PM PDT 24
Finished May 09 02:51:14 PM PDT 24
Peak memory 202040 kb
Host smart-c2178ca1-c0c0-494a-a307-b8e7005c8b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965541802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1965541802
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1131057566
Short name T326
Test name
Test status
Simulation time 527927248219 ps
CPU time 298.58 seconds
Started May 09 02:51:03 PM PDT 24
Finished May 09 02:56:08 PM PDT 24
Peak memory 202352 kb
Host smart-692d2072-a7c4-46c2-986a-594ed93d6a9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131057566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1131057566
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.392246483
Short name T272
Test name
Test status
Simulation time 597684284878 ps
CPU time 747.48 seconds
Started May 09 02:51:01 PM PDT 24
Finished May 09 03:03:34 PM PDT 24
Peak memory 202264 kb
Host smart-1d304c0a-4bdd-4675-9344-28d96d2def27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392246483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.392246483
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1098152511
Short name T111
Test name
Test status
Simulation time 169526654921 ps
CPU time 64.85 seconds
Started May 09 02:51:01 PM PDT 24
Finished May 09 02:52:12 PM PDT 24
Peak memory 202348 kb
Host smart-50e2184b-5334-4fab-89c0-29c4d6704443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098152511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1098152511
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.200621393
Short name T12
Test name
Test status
Simulation time 164720319576 ps
CPU time 404.04 seconds
Started May 09 02:51:09 PM PDT 24
Finished May 09 02:58:01 PM PDT 24
Peak memory 202352 kb
Host smart-286e57c8-5224-4a2a-9962-753151bc95da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=200621393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.200621393
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.4271456500
Short name T470
Test name
Test status
Simulation time 160706216101 ps
CPU time 378.75 seconds
Started May 09 02:51:04 PM PDT 24
Finished May 09 02:57:29 PM PDT 24
Peak memory 202360 kb
Host smart-eecc3117-6a5d-4bf7-b99e-9b3f27a9517b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271456500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.4271456500
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2511034356
Short name T411
Test name
Test status
Simulation time 488741153028 ps
CPU time 102.91 seconds
Started May 09 02:51:10 PM PDT 24
Finished May 09 02:53:01 PM PDT 24
Peak memory 202344 kb
Host smart-dec404bb-49b7-48f8-9958-ed29f3f25aa1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511034356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2511034356
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.296571266
Short name T288
Test name
Test status
Simulation time 513672943260 ps
CPU time 107.72 seconds
Started May 09 02:51:02 PM PDT 24
Finished May 09 02:52:55 PM PDT 24
Peak memory 202424 kb
Host smart-edbaf3ee-b80f-464c-85d6-324020ed37c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296571266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.296571266
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1939922412
Short name T33
Test name
Test status
Simulation time 199239172340 ps
CPU time 443.08 seconds
Started May 09 02:51:04 PM PDT 24
Finished May 09 02:58:34 PM PDT 24
Peak memory 202260 kb
Host smart-f1ebf3ea-22d7-4c93-81e4-043b1ad3c925
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939922412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1939922412
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3503656907
Short name T212
Test name
Test status
Simulation time 124191597233 ps
CPU time 467.63 seconds
Started May 09 02:51:07 PM PDT 24
Finished May 09 02:59:03 PM PDT 24
Peak memory 202656 kb
Host smart-aa46d024-cea4-44e3-9301-eac9aba7f72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503656907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3503656907
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.419206853
Short name T774
Test name
Test status
Simulation time 25097069282 ps
CPU time 28.98 seconds
Started May 09 02:51:03 PM PDT 24
Finished May 09 02:51:39 PM PDT 24
Peak memory 202096 kb
Host smart-1391ecee-ab13-4bc6-9ebe-5634742a1f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419206853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.419206853
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2952941341
Short name T723
Test name
Test status
Simulation time 3672811359 ps
CPU time 2.51 seconds
Started May 09 02:51:03 PM PDT 24
Finished May 09 02:51:12 PM PDT 24
Peak memory 202120 kb
Host smart-9b0fcb10-285e-4eee-8acf-080a064b90f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952941341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2952941341
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.4041804291
Short name T692
Test name
Test status
Simulation time 5618139433 ps
CPU time 4.53 seconds
Started May 09 02:51:02 PM PDT 24
Finished May 09 02:51:11 PM PDT 24
Peak memory 202100 kb
Host smart-7b50145b-885a-43d6-9bb5-7f7976be9223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041804291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.4041804291
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.71225336
Short name T245
Test name
Test status
Simulation time 664479978059 ps
CPU time 188.28 seconds
Started May 09 02:51:06 PM PDT 24
Finished May 09 02:54:21 PM PDT 24
Peak memory 202336 kb
Host smart-7377fc81-1455-41fb-a0f7-efb9fe768db1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71225336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.71225336
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3056679880
Short name T577
Test name
Test status
Simulation time 226790986676 ps
CPU time 329.84 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:56:48 PM PDT 24
Peak memory 218528 kb
Host smart-5323a897-bcc7-442c-8fe2-70ab06c9f0af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056679880 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3056679880
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4249539663
Short name T110
Test name
Test status
Simulation time 426604113 ps
CPU time 1.65 seconds
Started May 09 02:51:04 PM PDT 24
Finished May 09 02:51:12 PM PDT 24
Peak memory 202020 kb
Host smart-ca700e0a-e397-4b94-a5c8-193151a5578d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249539663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4249539663
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3239027475
Short name T665
Test name
Test status
Simulation time 331103371691 ps
CPU time 173.8 seconds
Started May 09 02:51:10 PM PDT 24
Finished May 09 02:54:12 PM PDT 24
Peak memory 202428 kb
Host smart-49d414d1-f051-4295-89fe-81d9771c5f87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239027475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3239027475
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2427270744
Short name T313
Test name
Test status
Simulation time 164989722357 ps
CPU time 105.24 seconds
Started May 09 02:51:04 PM PDT 24
Finished May 09 02:52:56 PM PDT 24
Peak memory 202364 kb
Host smart-f04b9d36-824b-4532-9bd7-d09940926902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427270744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2427270744
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3303313046
Short name T629
Test name
Test status
Simulation time 163657046342 ps
CPU time 377.02 seconds
Started May 09 02:51:10 PM PDT 24
Finished May 09 02:57:35 PM PDT 24
Peak memory 202336 kb
Host smart-d6958cb2-886c-4f6c-b026-304e738557bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303313046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3303313046
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1335190319
Short name T104
Test name
Test status
Simulation time 326919261903 ps
CPU time 738.25 seconds
Started May 09 02:51:09 PM PDT 24
Finished May 09 03:03:35 PM PDT 24
Peak memory 202344 kb
Host smart-0cac7d88-7fea-4bfb-b8f6-0f4c193a4577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335190319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1335190319
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.4313795
Short name T576
Test name
Test status
Simulation time 327561094081 ps
CPU time 754.21 seconds
Started May 09 02:51:07 PM PDT 24
Finished May 09 03:03:49 PM PDT 24
Peak memory 202280 kb
Host smart-f30241aa-f560-4ec7-8bf5-2199659954b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4313795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.4313795
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2286574945
Short name T427
Test name
Test status
Simulation time 177142110207 ps
CPU time 406.34 seconds
Started May 09 02:51:08 PM PDT 24
Finished May 09 02:58:02 PM PDT 24
Peak memory 202324 kb
Host smart-8a335172-50df-44b0-8630-9cc3ad263f37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286574945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2286574945
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.789779464
Short name T490
Test name
Test status
Simulation time 596315000455 ps
CPU time 726.11 seconds
Started May 09 02:51:07 PM PDT 24
Finished May 09 03:03:21 PM PDT 24
Peak memory 202308 kb
Host smart-b37979b7-3530-4bb6-8ce5-5802e2cbeae8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789779464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.789779464
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.279622624
Short name T347
Test name
Test status
Simulation time 104817096679 ps
CPU time 475.36 seconds
Started May 09 02:51:08 PM PDT 24
Finished May 09 02:59:12 PM PDT 24
Peak memory 202680 kb
Host smart-798028b8-784d-41b2-8610-e333f61919fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279622624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.279622624
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2552013019
Short name T617
Test name
Test status
Simulation time 24605854363 ps
CPU time 29.68 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:51:48 PM PDT 24
Peak memory 202176 kb
Host smart-b312ffca-909f-4802-afc2-92122a7aee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552013019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2552013019
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1816103481
Short name T800
Test name
Test status
Simulation time 3647652402 ps
CPU time 2.9 seconds
Started May 09 02:51:03 PM PDT 24
Finished May 09 02:51:12 PM PDT 24
Peak memory 202148 kb
Host smart-c3e44f82-2eac-4705-a896-0d1b6a197c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816103481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1816103481
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2763813252
Short name T705
Test name
Test status
Simulation time 5879550537 ps
CPU time 13.17 seconds
Started May 09 02:51:03 PM PDT 24
Finished May 09 02:51:22 PM PDT 24
Peak memory 202132 kb
Host smart-8a27fa10-442f-4550-bb62-06ac91c4a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763813252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2763813252
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2978156716
Short name T715
Test name
Test status
Simulation time 104764526017 ps
CPU time 103.91 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:53:03 PM PDT 24
Peak memory 211000 kb
Host smart-f23dc06e-5413-4de6-8189-76d085e8e9cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978156716 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2978156716
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.975467525
Short name T655
Test name
Test status
Simulation time 568799264 ps
CPU time 0.76 seconds
Started May 09 02:51:08 PM PDT 24
Finished May 09 02:51:17 PM PDT 24
Peak memory 202052 kb
Host smart-74b6f157-bb0a-4046-a4c4-3e046c47538f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975467525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.975467525
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.520199472
Short name T265
Test name
Test status
Simulation time 168809764248 ps
CPU time 210.04 seconds
Started May 09 02:51:06 PM PDT 24
Finished May 09 02:54:43 PM PDT 24
Peak memory 202348 kb
Host smart-0a1b7cd5-c1e0-4b18-bee6-76f9a945a69b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520199472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.520199472
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3734062318
Short name T567
Test name
Test status
Simulation time 255001270220 ps
CPU time 46.59 seconds
Started May 09 02:51:13 PM PDT 24
Finished May 09 02:52:07 PM PDT 24
Peak memory 202268 kb
Host smart-af192d5f-d77f-45a7-8a71-d186edd7dbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734062318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3734062318
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2557774003
Short name T627
Test name
Test status
Simulation time 162548235979 ps
CPU time 357.55 seconds
Started May 09 02:51:13 PM PDT 24
Finished May 09 02:57:18 PM PDT 24
Peak memory 202276 kb
Host smart-d3a69aaf-53cd-4578-adb3-a74e504f89c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557774003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2557774003
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1611240835
Short name T744
Test name
Test status
Simulation time 162580624751 ps
CPU time 339.87 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:56:59 PM PDT 24
Peak memory 202348 kb
Host smart-22f7df62-334e-400a-8455-8e28fd847dc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611240835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1611240835
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3354816287
Short name T485
Test name
Test status
Simulation time 161059777362 ps
CPU time 154.28 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:53:53 PM PDT 24
Peak memory 202372 kb
Host smart-e762a96d-816c-47b9-874b-b24bd6f2c464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354816287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3354816287
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3757509865
Short name T27
Test name
Test status
Simulation time 162655329294 ps
CPU time 363.08 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:57:22 PM PDT 24
Peak memory 202304 kb
Host smart-f38f5d40-8cf2-43f7-b354-b61a5ae2dd75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757509865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3757509865
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.906971567
Short name T40
Test name
Test status
Simulation time 186177015657 ps
CPU time 70.52 seconds
Started May 09 02:51:13 PM PDT 24
Finished May 09 02:52:31 PM PDT 24
Peak memory 202332 kb
Host smart-f55998cd-b1de-43f5-ab2c-1a6d692af087
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906971567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.906971567
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2107901229
Short name T793
Test name
Test status
Simulation time 201675191234 ps
CPU time 281.75 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:56:00 PM PDT 24
Peak memory 202316 kb
Host smart-19e7ce86-b46f-4be2-ba75-c407267c87e9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107901229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2107901229
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3438629331
Short name T415
Test name
Test status
Simulation time 108569682833 ps
CPU time 422.95 seconds
Started May 09 02:51:12 PM PDT 24
Finished May 09 02:58:23 PM PDT 24
Peak memory 202736 kb
Host smart-1898802b-bf54-434b-bcb8-016a6847ee35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438629331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3438629331
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3760746758
Short name T717
Test name
Test status
Simulation time 34920382669 ps
CPU time 20.65 seconds
Started May 09 02:51:13 PM PDT 24
Finished May 09 02:51:41 PM PDT 24
Peak memory 202128 kb
Host smart-66224691-7c3e-40d2-b4b0-79181fe61e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760746758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3760746758
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3016711441
Short name T646
Test name
Test status
Simulation time 4586984237 ps
CPU time 10.34 seconds
Started May 09 02:51:13 PM PDT 24
Finished May 09 02:51:31 PM PDT 24
Peak memory 202096 kb
Host smart-ac89eb64-b85a-4f52-b37f-4e3bc639b8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016711441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3016711441
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.4281059380
Short name T566
Test name
Test status
Simulation time 5593432592 ps
CPU time 7.68 seconds
Started May 09 02:51:11 PM PDT 24
Finished May 09 02:51:27 PM PDT 24
Peak memory 202204 kb
Host smart-ff513952-5a65-4c72-ab6a-d7086d7b2b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281059380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.4281059380
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.433878108
Short name T296
Test name
Test status
Simulation time 94842289327 ps
CPU time 71.94 seconds
Started May 09 02:51:28 PM PDT 24
Finished May 09 02:52:43 PM PDT 24
Peak memory 211976 kb
Host smart-e711c7de-e5eb-49e3-835a-695a69e69379
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433878108 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.433878108
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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