Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7807	1			T6	20		T7	67		T9	20
testmodes[AdcCtrlTestmodeNormal]	6247	1			T2	2		T4	1		T5	3
testmodes[AdcCtrlTestmodeLowpower]	6172	1			T1	1		T3	18		T4	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4195	1			T6	19		T7	22		T9	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	2003	1			T7	25		T11	8		T26	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1493	1			T7	20		T11	1		T33	10
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1976	1			T7	22		T11	8		T26	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2340	1			T2	1		T5	2		T7	10
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1588	1			T7	23		T11	2		T30	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1519	1			T7	23		T11	1		T33	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1578	1			T4	1		T7	19		T11	3
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2837	1			T3	17		T7	13		T10	14