Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24877

1

T2

1

T3

18

T4

34

auto[ADC_CTRL_FILTER_COND_OUT]

3605

1

T1

17

T2

1

T8

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22142

1

T2

1

T3

18

T4

9

auto[1]

6340

1

T1

17

T2

1

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	304	1			T4	9		T5	5		T160	1
values[1]	710	1			T2	1		T14	33		T16	15
values[2]	684	1			T5	22		T30	2		T72	1
values[3]	758	1			T2	1		T11	2		T13	22
values[4]	762	1			T1	17		T13	26		T49	9
values[5]	556	1			T8	6		T35	7		T166	20
values[6]	559	1			T12	10		T14	16		T114	17
values[7]	710	1			T30	7		T114	32		T108	14
values[8]	738	1			T5	11		T40	5		T114	19
values[9]	3414	1			T4	25		T11	12		T12	10
minimum	19287	1			T3	18		T6	20		T7	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	831	1			T2	1		T5	22		T14	14
values[1]	639	1			T30	2		T72	1		T33	13
values[2]	770	1			T1	17		T2	1		T11	2
values[3]	641	1			T13	26		T49	9		T122	13
values[4]	583	1			T8	6		T14	16		T35	7
values[5]	618	1			T12	10		T114	17		T34	4
values[6]	3007	1			T30	7		T40	5		T73	17
values[7]	736	1			T5	11		T11	12		T114	19
values[8]	981	1			T4	34		T5	5		T12	10
values[9]	226	1			T171	13		T39	7		T172	6
minimum	19450	1			T3	18		T6	20		T7	178

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	1		T5	12		T14	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T16	8		T48	16		T36	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	9		T173	1		T116	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T30	1		T72	1		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	2		T40	4		T147	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	17		T2	1		T13	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T49	5		T128	1		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	15		T122	6		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T35	4		T166	11		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	6		T14	16		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	10		T34	3		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T114	8		T115	14		T49	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1706	1			T30	3		T73	2		T113	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	5		T114	15		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	6		T11	10		T114	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T16	8		T34	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	18		T5	5		T12	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T30	13		T112	3		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T39	6		T174	1		T175	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T171	1		T172	1		T176	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19174	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T14	19		T49	1		T177	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	10		T178	9		T38	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T16	7		T48	11		T36	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T33	4		T173	11		T179	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T30	1		T48	1		T127	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T147	10		T109	10		T131	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	11		T122	14		T180	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T49	4		T128	5		T110	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	11		T122	7		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	3		T166	9		T127	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T128	4		T38	1		T171	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T34	1		T155	2		T127	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T114	9		T181	9		T182	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T30	4		T73	15		T113	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T114	17		T81	12		T183	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	5		T11	2		T114	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T16	23		T153	1		T184	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	16		T16	4		T185	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T185	2		T179	11		T17	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T39	1		T174	3		T175	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T171	12		T172	5		T176	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T33	1		T16	1		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T177	9		T171	3		T186	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T4	6		T5	5		T39	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T160	1		T171	1		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	1		T14	14		T115	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T14	19		T16	8		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	12		T33	9		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T30	1		T72	1		T48	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	2		T40	4		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	1		T13	11		T72	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T49	5		T147	9		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	17		T13	15		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T35	4		T166	11		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T8	6		T122	6		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	10		T34	3		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	16		T114	8		T115	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T30	3		T108	14		T111	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T114	15		T117	1		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	6		T114	12		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	5		T16	8		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1759	1			T4	12		T11	10		T12	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T30	13		T112	3		T117	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19142	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T4	3		T39	1		T174	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T171	12		T172	5		T188	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T184	7		T183	21		T18	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	7		T36	6		T189	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	10		T33	4		T173	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T30	1		T48	12		T127	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T109	10		T131	14		T156	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	11		T122	14		T128	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T49	4		T147	10		T128	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T13	11		T37	1		T118	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T35	3		T166	9		T127	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T122	7		T171	6		T156	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T34	1		T155	2		T127	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T114	9		T128	4		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T30	4		T190	13		T191	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T114	17		T181	9		T191	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	5		T114	7		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T16	23		T153	1		T179	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1114	1			T4	13		T11	2		T73	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T185	2		T17	2		T192	24
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	1		T5	11		T14	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T16	8		T48	12		T36	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T33	10		T173	12		T116	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T30	2		T72	1		T48	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	2		T40	1		T147	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	1		T2	1		T13	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	5		T128	6		T110	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	12		T122	8		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T35	6		T166	10		T127	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T8	1		T14	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	1		T34	3		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T114	10		T115	1		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T30	5		T73	17		T113	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T40	1		T114	18		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	6		T11	7		T114	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T16	25		T34	1		T153	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T4	18		T5	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T30	1		T112	1		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T39	4		T174	4		T175	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T171	13		T172	6		T176	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19323	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T14	1		T49	1		T177	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	11		T14	13		T178	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T16	7		T48	15		T36	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T33	3		T138	10		T170	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T111	18		T17	2		T74	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T40	3		T147	8		T109	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	16		T13	10		T122	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T49	4		T125	13		T193	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	14		T122	5		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T35	1		T166	10		T109	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T8	5		T14	15		T112	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	9		T34	1		T111	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T114	7		T115	13		T49	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T30	2		T129	34		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	4		T114	14		T183	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	5		T11	5		T114	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	6		T184	14		T194	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	16		T5	4		T12	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T30	12		T112	2		T185	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T39	3		T175	13		T164	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T176	3		T195	14		T196	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T184	2		T197	12		T198	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T14	18		T177	9		T199	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T4	4		T5	1		T39	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T160	1		T171	13		T172	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	1		T14	1		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	1		T16	8		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	11		T33	10		T173	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T30	2		T72	1		T48	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	2		T40	1		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	1		T13	12		T72	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T49	5		T147	11		T128	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	1		T13	12		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T35	6		T166	10		T127	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	1		T122	8		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	1		T34	3		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	1		T114	10		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T30	5		T108	1		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T114	18		T117	1		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	6		T114	8		T34	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T40	1		T16	25		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1476	1			T4	14		T11	7		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T30	1		T112	1		T117	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19287	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T4	5		T5	4		T39	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T188	9		T148	10		T200	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	13		T115	7		T108	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	18		T16	7		T36	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T5	11		T33	3		T178	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T48	15		T111	18		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T40	3		T109	10		T131	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	10		T122	10		T31	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T49	4		T147	8		T125	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	16		T13	14		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T35	1		T166	10		T109	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T8	5		T122	5		T156	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	9		T34	1		T132	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	15		T114	7		T115	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T30	2		T108	13		T111	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T114	14		T191	8		T183	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	5		T114	11		T182	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T40	4		T16	6		T184	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T4	11		T11	5		T12	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T30	12		T112	2		T185	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22177

1

T2

1

T3

18

T5

16

auto[ADC_CTRL_FILTER_COND_OUT]

6305

1

T1

17

T2

1

T4

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22456

1

T1

17

T2

1

T3

18

auto[1]

6026

1

T2

1

T5

27

T11

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T201	21		-	-		-	-
values[0]	119	1			T185	7		T139	1		T202	1
values[1]	566	1			T4	9		T14	16		T72	1
values[2]	623	1			T1	17		T13	26		T30	2
values[3]	922	1			T2	1		T8	6		T12	10
values[4]	805	1			T5	27		T11	2		T41	1
values[5]	873	1			T12	10		T16	7		T178	23
values[6]	706	1			T2	1		T5	11		T14	19
values[7]	695	1			T30	13		T34	4		T155	3
values[8]	601	1			T4	25		T14	14		T33	13
values[9]	3264	1			T11	12		T13	22		T30	7
minimum	19287	1			T3	18		T6	20		T7	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	822	1			T4	9		T14	16		T30	2
values[1]	3172	1			T1	17		T2	1		T8	6
values[2]	745	1			T11	2		T12	10		T40	5
values[3]	792	1			T5	22		T12	10		T41	1
values[4]	748	1			T5	16		T16	7		T115	14
values[5]	743	1			T2	1		T14	19		T40	4
values[6]	705	1			T30	13		T35	7		T116	1
values[7]	564	1			T4	25		T13	22		T14	14
values[8]	691	1			T11	12		T30	7		T115	8
values[9]	212	1			T114	19		T153	2		T124	1
minimum	19288	1			T3	18		T6	20		T7	178

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T30	1		T173	1		T116	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T4	6		T14	16		T72	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T34	1		T36	8		T117	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1806	1			T1	17		T2	1		T8	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	10		T40	5		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	2		T49	1		T182	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T41	1		T48	16		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	12		T12	10		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	11		T16	3		T115	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T108	13		T203	12		T132	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T2	1		T72	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T14	19		T40	4		T16	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T116	1		T123	1		T131	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T30	13		T35	4		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T14	14		T114	8		T108	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	12		T13	11		T33	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	10		T115	8		T108	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T30	3		T128	1		T111	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T153	1		T124	1		T74	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T114	12		T125	14		T204	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19143	1			T3	18		T6	20		T7	178
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T30	1		T173	11		T127	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	3		T127	2		T122	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T36	6		T179	11		T171	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1087	1			T13	11		T73	15		T113	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	1		T147	10		T166	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T182	8		T191	12		T205	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T48	11		T81	12		T204	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	10		T127	11		T110	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	5		T16	4		T192	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T119	12		T206	7		T197	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T128	4		T17	2		T184	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T16	7		T34	1		T178	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T131	14		T171	6		T120	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T35	3		T17	5		T156	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T114	9		T207	12		T208	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	13		T13	11		T33	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	2		T170	7		T168	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T30	4		T128	5		T181	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T153	1		T74	2		T209	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T114	7		T125	14		T204	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T201	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T202	1		T210	7		T142	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T185	5		T139	1		T211	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T173	1		T116	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	6		T14	16		T72	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T30	1		T36	8		T117	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	17		T13	15		T49	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	10		T40	5		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T2	1		T8	6		T16	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	5		T41	1		T48	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	12		T11	2		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T16	3		T115	14		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	10		T178	14		T108	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T2	1		T5	6		T72	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T14	19		T40	4		T16	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T116	1		T128	1		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T30	13		T34	3		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	14		T108	14		T182	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	12		T33	9		T114	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T11	10		T114	8		T115	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1797	1			T13	11		T30	3		T73	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19142	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T201	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T210	2		T142	3		T144	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T185	2		T211	13		T212	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T173	11		T127	11		T190	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	3		T127	2		T109	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T30	1		T36	6		T171	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	11		T49	4		T122	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T147	10		T166	9		T179	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T16	23		T34	1		T122	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T48	12		T156	14		T176	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	10		T127	11		T110	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T16	4		T192	14		T81	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T178	9		T179	13		T119	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	5		T17	2		T192	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T16	7		T185	11		T138	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T128	4		T131	14		T171	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T34	1		T155	2		T128	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T182	18		T207	12		T213	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	13		T33	4		T114	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	2		T114	9		T153	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	987	1			T13	11		T30	4		T73	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1