Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24950

1

T1

17

T3

18

T4

25

auto[ADC_CTRL_FILTER_COND_OUT]

3532

1

T2

2

T4

9

T5

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22236

1

T3

18

T4

34

T5

16

auto[1]

6246

1

T1

17

T2

2

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	313	1			T30	13		T16	15		T81	9
values[0]	35	1			T250	11		T277	23		T284	1
values[1]	759	1			T5	22		T114	32		T41	1
values[2]	716	1			T14	14		T72	1		T34	4
values[3]	623	1			T4	25		T14	19		T30	2
values[4]	833	1			T11	12		T14	16		T114	19
values[5]	2955	1			T8	6		T40	4		T73	17
values[6]	882	1			T2	2		T13	22		T147	19
values[7]	508	1			T4	9		T30	7		T153	2
values[8]	600	1			T5	16		T12	10		T13	26
values[9]	971	1			T1	17		T11	2		T12	10
minimum	19287	1			T3	18		T6	20		T7	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	691	1			T114	32		T41	1		T109	22
values[1]	655	1			T14	33		T72	1		T34	4
values[2]	580	1			T4	25		T30	2		T72	1
values[3]	3228	1			T11	12		T14	16		T73	17
values[4]	642	1			T8	6		T40	4		T16	31
values[5]	851	1			T2	2		T13	22		T147	19
values[6]	485	1			T4	9		T5	16		T30	7
values[7]	606	1			T12	10		T13	26		T40	5
values[8]	1078	1			T1	17		T11	2		T12	10
values[9]	83	1			T16	15		T34	4		T17	9
minimum	19583	1			T3	18		T5	22		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T114	15		T41	1		T109	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T185	5		T81	1		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	14		T72	1		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	19		T127	2		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T4	12		T110	1		T31	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T30	1		T72	1		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1688	1			T14	16		T73	2		T113	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T11	10		T114	20		T16	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	6		T40	4		T16	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T108	13		T112	15		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	11		T147	9		T112	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	2		T116	1		T187	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	6		T30	3		T36	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T4	6		T5	5		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	10		T40	5		T33	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	15		T178	14		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T1	17		T11	2		T12	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T48	16		T159	1		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T206	1		T196	10		T246	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T16	8		T34	3		T17	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19215	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T5	12		T115	8		T17	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T114	17		T109	12		T131	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T185	2		T81	12		T204	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T34	1		T120	2		T184	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T127	22		T128	5		T109	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	13		T110	3		T179	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T30	1		T48	1		T179	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T73	15		T113	21		T137	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	2		T114	16		T16	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	23		T177	9		T171	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T183	21		T168	1		T20	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	11		T147	10		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T190	13		T177	4		T156	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T5	5		T30	4		T36	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T4	3		T153	1		T166	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T33	4		T173	11		T49	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	11		T178	9		T38	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T120	10		T277	5		T278	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T48	11		T181	9		T119	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T206	7		T246	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T16	7		T34	1		T17	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T33	1		T16	1		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T5	10		T17	2		T192	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T30	13		T81	9		T249	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T16	8		T169	2		T204	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T284	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T250	11		T277	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T114	15		T41	1		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	12		T115	8		T185	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T14	14		T72	1		T34	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T127	1		T109	11		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	12		T159	1		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	19		T30	1		T72	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	16		T155	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T11	10		T114	12		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T8	6		T40	4		T73	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T114	8		T108	13		T112	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T13	11		T147	9		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	2		T116	1		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T30	3		T36	8		T37	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	6		T153	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	6		T12	10		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	5		T13	15		T178	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T1	17		T11	2		T12	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T34	3		T48	16		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19142	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T206	7		T285	9		T286	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T16	7		T204	3		T176	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T277	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T114	17		T128	4		T109	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	10		T185	2		T17	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T34	1		T120	2		T184	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T127	11		T109	10		T118	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	13		T110	3		T179	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	1		T48	1		T127	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T155	2		T185	11		T179	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	2		T114	7		T16	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T73	15		T113	21		T16	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T114	9		T183	21		T168	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	11		T147	10		T38	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T190	13		T177	4		T156	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T30	4		T36	6		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	3		T153	1		T166	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	5		T33	4		T173	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	11		T178	9		T38	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T120	10		T277	5		T278	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T34	1		T48	11		T181	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T114	18		T41	1		T109	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T185	3		T81	13		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	1		T72	1		T34	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	1		T127	24		T128	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	14		T110	4		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T30	2		T72	1		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T14	1		T73	17		T113	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T11	7		T114	18		T16	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	1		T40	1		T16	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T108	1		T112	1		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T13	12		T147	11		T112	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	2		T116	1		T187	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	6		T30	5		T36	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	4		T5	1		T153	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	1		T40	1		T33	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	12		T178	10		T38	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T1	1		T11	2		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T48	12		T159	1		T181	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T206	8		T196	1		T246	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T16	8		T34	3		T17	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19354	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T5	11		T115	1		T17	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T114	14		T109	9		T131	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T185	4		T287	15		T250	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	13		T184	14		T170	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	18		T109	10		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T4	11		T31	3		T132	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T111	18		T203	11		T132	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T14	15		T129	34		T130	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	5		T114	18		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	5		T40	3		T16	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T108	12		T112	14		T183	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	10		T147	8		T112	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T190	15		T177	10		T156	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T5	5		T30	2		T36	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T4	5		T5	4		T166	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T12	9		T40	4		T33	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	14		T178	13		T125	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T1	16		T12	9		T30	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T48	15		T39	3		T176	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T196	9		T272	12		T288	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T16	7		T34	1		T17	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T148	6		T197	12		T271	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T5	11		T115	7		T17	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T30	1		T81	1		T249	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T16	8		T169	2		T204	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T284	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T250	1		T277	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T114	18		T41	1		T128	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	11		T115	1		T185	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	1		T72	1		T34	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T127	12		T109	11		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	14		T159	1		T110	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	1		T30	2		T72	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	1		T155	3		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T11	7		T114	8		T16	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T8	1		T40	1		T73	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T114	10		T108	1		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	12		T147	11		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	2		T116	1		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T30	5		T36	9		T37	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	4		T153	2		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	6		T12	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	1		T13	12		T178	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T1	1		T11	2		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T34	3		T48	12		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19287	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T30	12		T81	8		T194	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T16	7		T176	3		T289	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T250	10		T277	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T114	14		T109	9		T131	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	11		T115	7		T185	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	13		T184	14		T170	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T109	10		T148	19		T149	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	11		T31	3		T156	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	18		T111	18		T138	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	15		T185	12		T132	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T11	5		T114	11		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T8	5		T40	3		T129	34
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T114	7		T108	12		T112	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	10		T147	8		T112	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T190	15		T177	10		T156	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T30	2		T36	5		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T4	5		T166	10		T122	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	5		T12	9		T40	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	4		T13	14		T178	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T1	16		T12	9		T108	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T34	1		T48	15		T17	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20