Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25194

1

T1

17

T2

1

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3288

1

T2

1

T4

25

T5

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22597

1

T1

17

T3

18

T4

9

auto[1]

5885

1

T2

2

T4

25

T8

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	192	1			T2	1		T35	7		T159	1
values[0]	87	1			T203	12		T197	26		T200	30
values[1]	685	1			T11	2		T72	1		T34	4
values[2]	552	1			T1	17		T5	11		T40	4
values[3]	610	1			T40	5		T33	13		T16	7
values[4]	3052	1			T5	22		T8	6		T11	12
values[5]	873	1			T4	9		T114	17		T48	27
values[6]	838	1			T2	1		T4	25		T16	31
values[7]	626	1			T72	1		T49	9		T36	14
values[8]	811	1			T5	5		T49	9		T155	3
values[9]	869	1			T12	10		T13	48		T14	30
minimum	19287	1			T3	18		T6	20		T7	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	722	1			T72	1		T34	4		T115	8
values[1]	506	1			T1	17		T5	11		T40	4
values[2]	649	1			T8	6		T11	12		T12	10
values[3]	3137	1			T4	9		T5	22		T30	20
values[4]	853	1			T114	17		T16	31		T178	23
values[5]	710	1			T2	1		T4	25		T72	1
values[6]	769	1			T36	14		T116	1		T108	23
values[7]	673	1			T5	5		T49	10		T155	3
values[8]	860	1			T2	1		T12	10		T13	48
values[9]	104	1			T108	13		T122	25		T171	7
minimum	19499	1			T3	18		T6	20		T7	178

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T34	3		T112	15		T17	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T72	1		T115	8		T203	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	17		T5	6		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T40	4		T16	8		T122	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T8	6		T12	10		T14	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	10		T33	9		T114	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1719	1			T4	6		T30	16		T73	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	12		T34	1		T48	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T178	14		T117	1		T156	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T114	8		T16	8		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	1		T72	1		T127	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	12		T49	9		T109	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T36	8		T116	1		T108	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T108	14		T111	19		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	5		T49	5		T147	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T49	1		T155	1		T189	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T13	26		T14	30		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	1		T12	10		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T78	1		T139	1		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T108	13		T122	11		T171	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19204	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T11	2		T171	1		T132	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T34	1		T17	2		T188	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T179	11		T138	10		T183	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	5		T185	2		T118	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T16	7		T122	7		T120	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T16	4		T190	13		T182	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	2		T33	4		T114	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T4	3		T30	4		T73	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	10		T48	11		T192	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T178	9		T156	14		T148	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T114	9		T16	23		T192	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T127	13		T37	1		T177	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	13		T109	12		T265	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T36	6		T185	11		T179	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T131	14		T179	13		T181	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	4		T147	10		T109	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T155	2		T189	11		T128	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	22		T153	1		T128	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T30	1		T114	7		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T122	14		T171	6		T254	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T33	1		T16	1		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T171	12		T180	4		T170	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T168	2		T290	1		T266	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T2	1		T35	4		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T197	13		T200	19		T174	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T203	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T34	3		T112	15		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	2		T72	1		T115	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	17		T5	6		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T40	4		T16	8		T122	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T40	5		T16	3		T115	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T33	9		T41	1		T166	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1684	1			T8	6		T12	10		T14	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	12		T11	10		T114	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T4	6		T156	15		T184	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T114	8		T48	16		T192	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T2	1		T178	14		T127	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	12		T16	8		T109	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T72	1		T36	8		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T49	9		T111	19		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	5		T49	5		T147	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T155	1		T108	14		T189	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T13	26		T14	30		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	10		T30	1		T114	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19142	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T168	1		T290	1		T266	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T35	3		T171	6		T151	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T197	13		T200	11		T174	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T34	1		T262	6		T200	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T171	12		T138	10		T180	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	5		T185	2		T118	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T16	7		T122	7		T179	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T16	4		T190	13		T171	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T33	4		T166	9		T128	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	922	1			T30	4		T73	15		T113	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	10		T11	2		T114	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T4	3		T156	14		T291	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T114	9		T48	11		T192	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T178	9		T127	13		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	13		T16	23		T109	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	6		T185	11		T179	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T131	14		T181	9		T193	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T49	4		T147	10		T109	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T155	2		T189	11		T179	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	22		T153	1		T128	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T30	1		T114	7		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	4		T112	1		T17	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T72	1		T115	1		T203	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	1		T5	6		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T40	1		T16	8		T122	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	1		T12	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	7		T33	10		T114	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T4	4		T30	6		T73	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	11		T34	1		T48	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T178	10		T117	1		T156	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T114	10		T16	25		T192	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T2	1		T72	1		T127	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T4	14		T49	1		T109	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T36	9		T116	1		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T108	1		T111	1		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	1		T49	5		T147	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T49	1		T155	3		T189	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T13	24		T14	2		T153	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	1		T12	1		T30	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T78	1		T139	1		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T108	1		T122	15		T171	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19350	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T11	2		T171	13		T132	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T112	14		T17	1		T188	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T115	7		T203	11		T138	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	16		T5	5		T185	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T40	3		T16	7		T122	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	5		T12	9		T14	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	5		T33	3		T114	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T4	5		T30	14		T129	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	11		T48	15		T184	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T178	13		T156	14		T184	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T114	7		T16	6		T125	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T37	1		T177	9		T216	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	11		T49	8		T109	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T36	5		T108	8		T112	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T108	13		T111	18		T131	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	4		T49	4		T147	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T189	17		T125	11		T216	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	24		T14	28		T111	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	9		T114	11		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T248	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T108	12		T122	10		T292	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T215	5		T197	12		T200	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T132	15		T170	3		T214	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T168	2		T290	2		T266	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T2	1		T35	6		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T197	14		T200	12		T174	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T203	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T34	4		T112	1		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	2		T72	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T5	6		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T40	1		T16	8		T122	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T40	1		T16	6		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T33	10		T41	1		T166	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T8	1		T12	1		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	11		T11	7		T114	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T4	4		T156	15		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T114	10		T48	12		T192	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T2	1		T178	10		T127	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T4	14		T16	25		T109	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T72	1		T36	9		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T49	1		T111	1		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	1		T49	5		T147	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T155	3		T108	1		T189	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	24		T14	2		T153	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	1		T30	2		T114	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19287	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T168	1		T248	12		T199	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T35	1		T292	3		T242	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T197	12		T200	18		T283	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T203	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T112	14		T215	5		T134	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T115	7		T132	15		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	16		T5	5		T185	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T40	3		T16	7		T122	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T40	4		T16	1		T115	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T33	3		T166	10		T31	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T8	5		T12	9		T14	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	11		T11	5		T114	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T4	5		T156	14		T184	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T114	7		T48	15		T125	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T178	13		T37	1		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	11		T16	6		T109	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T36	5		T108	8		T112	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T49	8		T111	18		T131	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	4		T49	4		T147	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T108	13		T189	17		T125	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	24		T14	28		T111	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	9		T114	11		T34	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20