Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25178

1

T2

2

T3

18

T4

25

auto[ADC_CTRL_FILTER_COND_OUT]

3304

1

T1

17

T4

9

T5

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22152

1

T1

17

T3

18

T4

25

auto[1]

6330

1

T2

2

T4

9

T5

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	366	1			T8	6		T13	26		T16	15
values[0]	10	1			T194	3		T264	2		T273	5
values[1]	627	1			T30	2		T72	2		T16	38
values[2]	473	1			T11	2		T178	23		T49	9
values[3]	672	1			T14	33		T40	5		T34	4
values[4]	813	1			T2	1		T4	25		T40	4
values[5]	3191	1			T4	9		T5	22		T14	16
values[6]	601	1			T114	32		T49	9		T147	19
values[7]	578	1			T12	10		T30	20		T34	4
values[8]	716	1			T1	17		T5	5		T11	12
values[9]	1148	1			T2	1		T5	11		T12	10
minimum	19287	1			T3	18		T6	20		T7	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	533	1			T30	2		T72	1		T16	7
values[1]	448	1			T11	2		T178	23		T41	1
values[2]	734	1			T14	33		T40	5		T34	4
values[3]	3179	1			T2	1		T4	25		T5	22
values[4]	960	1			T4	9		T48	2		T147	19
values[5]	469	1			T114	32		T49	9		T127	12
values[6]	644	1			T12	10		T30	20		T34	4
values[7]	718	1			T1	17		T5	5		T11	12
values[8]	1127	1			T2	1		T5	11		T8	6
values[9]	175	1			T160	1		T187	1		T38	9
minimum	19495	1			T3	18		T6	20		T7	178

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T30	1		T34	1		T36	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T72	1		T16	3		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T11	2		T49	5		T123	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T178	14		T41	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T14	19		T40	5		T34	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	14		T122	11		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1737	1			T2	1		T4	12		T5	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T114	12		T127	1		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T147	9		T109	11		T132	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	6		T48	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T49	9		T127	1		T17	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T114	15		T184	15		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T30	16		T173	1		T115	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	10		T34	3		T108	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	10		T12	10		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	17		T5	5		T13	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T2	1		T5	6		T8	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T16	8		T115	8		T108	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T160	1		T38	2		T293	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T187	1		T38	3		T169	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19182	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T16	8		T124	1		T188	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T30	1		T36	6		T110	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T16	4		T153	1		T155	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T49	4		T148	14		T271	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T178	9		T127	11		T125	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T34	1		T35	3		T166	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T122	14		T231	11		T156	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T4	13		T5	10		T73	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T114	7		T127	2		T181	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T147	10		T109	10		T138	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T4	3		T48	1		T128	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T127	11		T17	2		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T114	17		T184	12		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T30	4		T173	11		T48	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T34	1		T122	7		T177	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	2		T119	3		T168	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	11		T179	16		T176	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T5	5		T13	11		T33	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T16	7		T131	14		T179	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T38	3		T197	13		T267	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T38	1		T205	3		T243	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T33	1		T16	1		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T16	23		T188	10		T206	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T8	6		T13	15		T160	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T16	8		T160	1		T187	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T273	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T194	3		T264	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T30	1		T72	1		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T72	1		T16	11		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	2		T49	5		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T178	14		T155	1		T112	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	19		T40	5		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	14		T41	1		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T2	1		T4	12		T40	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T122	11		T231	1		T177	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1730	1			T5	12		T14	16		T73	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T4	6		T114	12		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T49	9		T147	9		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T114	15		T128	1		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T30	16		T173	1		T115	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	10		T34	3		T108	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T11	10		T49	1		T179	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	17		T5	5		T179	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T2	1		T5	6		T12	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T13	11		T115	8		T108	27
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19142	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T13	11		T171	3		T182	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T16	7		T179	13		T172	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T264	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	1		T36	6		T185	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T16	27		T153	1		T120	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T49	4		T110	3		T148	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T178	9		T155	2		T183	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	1		T35	3		T166	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T127	11		T156	14		T125	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T4	13		T189	11		T185	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T122	14		T231	11		T177	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T5	10		T73	15		T113	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	3		T114	7		T48	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T147	10		T127	11		T17	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T114	17		T128	4		T182	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T30	4		T173	11		T48	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T34	1		T122	7		T177	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	2		T179	11		T119	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T179	16		T171	6		T266	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T5	5		T33	4		T114	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	11		T131	14		T118	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T30	2		T34	1		T36	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T72	1		T16	6		T153	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	2		T49	5		T123	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T178	10		T41	1		T127	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	1		T40	1		T34	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	1		T122	15		T231	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T2	1		T4	14		T5	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T114	8		T127	3		T181	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T147	11		T109	11		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T4	4		T48	2		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T49	1		T127	12		T17	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T114	18		T184	13		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T30	6		T173	12		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T34	4		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	7		T12	1		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	1		T5	1		T13	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T2	1		T5	6		T8	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T16	8		T115	1		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T160	1		T38	5		T293	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T187	1		T38	2		T169	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19342	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T16	25		T124	1		T188	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T36	5		T112	14		T184	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T16	1		T217	13		T294	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T49	4		T148	6		T271	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T178	13		T112	2		T132	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	18		T40	4		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T14	13		T122	10		T156	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T4	11		T5	11		T14	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T114	11		T177	9		T132	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T147	8		T109	10		T132	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	5		T37	1		T190	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T49	8		T17	1		T39	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T114	14		T184	14		T250	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T30	14		T115	13		T48	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	9		T108	8		T122	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	5		T12	9		T168	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	16		T5	4		T13	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T5	5		T8	5		T13	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T16	7		T115	7		T108	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T197	12		T272	9		T267	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T38	2		T216	10		T205	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T185	12		T295	1		T296	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T16	6		T188	9		T194	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T8	1		T13	12		T160	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T16	8		T160	1		T187	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T273	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T194	2		T264	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T30	2		T72	1		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T72	1		T16	31		T153	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	2		T49	5		T110	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T178	10		T155	3		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T14	1		T40	1		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	1		T41	1		T127	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T2	1		T4	14		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T122	15		T231	12		T177	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T5	11		T14	1		T73	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T4	4		T114	8		T48	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T49	1		T147	11		T127	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T114	18		T128	5		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T30	6		T173	12		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	1		T34	4		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T11	7		T49	1		T179	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	1		T5	1		T179	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T2	1		T5	6		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T13	12		T115	1		T108	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19287	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T8	5		T13	14		T182	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T16	7		T216	10		T205	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T273	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T194	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T36	5		T112	14		T185	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T16	7		T188	9		T217	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T49	4		T148	6		T261	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T178	13		T112	2		T183	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	18		T40	4		T34	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T14	13		T132	2		T156	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	11		T40	3		T189	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T122	10		T177	9		T132	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T5	11		T14	15		T129	34
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	5		T114	11		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T49	8		T147	8		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T114	14		T182	8		T243	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T30	14		T115	13		T48	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	9		T108	8		T122	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	5		T168	1		T19	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T1	16		T5	4		T134	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T5	5		T12	9		T33	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T13	10		T115	7		T108	25

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20