Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24888

1

T1

17

T2

1

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3594

1

T2

1

T4

34

T5

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22435

1

T1

17

T2

1

T3

18

auto[1]

6047

1

T2

1

T4

25

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	178	1			T16	7		T49	9		T116	1
values[0]	29	1			T132	3		T254	9		T297	14
values[1]	701	1			T2	1		T14	33		T33	13
values[2]	689	1			T1	17		T16	31		T178	23
values[3]	564	1			T5	22		T8	6		T12	10
values[4]	643	1			T12	10		T30	15		T114	32
values[5]	905	1			T11	12		T35	7		T36	14
values[6]	607	1			T2	1		T5	5		T14	16
values[7]	652	1			T5	11		T11	2		T30	7
values[8]	2935	1			T4	34		T73	17		T113	24
values[9]	1292	1			T13	22		T40	4		T72	1
minimum	19287	1			T3	18		T6	20		T7	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	753	1			T1	17		T2	1		T14	14
values[1]	582	1			T12	10		T178	23		T48	2
values[2]	555	1			T5	22		T8	6		T12	10
values[3]	791	1			T30	15		T114	32		T49	9
values[4]	788	1			T11	12		T35	7		T36	14
values[5]	738	1			T5	5		T14	16		T72	1
values[6]	2859	1			T2	1		T4	9		T5	11
values[7]	800	1			T4	25		T114	19		T16	15
values[8]	1016	1			T13	22		T40	4		T72	1
values[9]	109	1			T41	1		T49	1		T231	12
minimum	19491	1			T3	18		T6	20		T7	178

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	17		T16	8		T117	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	1		T14	14		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	10		T178	14		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T203	12		T187	1		T118	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	12		T8	6		T13	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	10		T114	8		T147	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T114	15		T110	1		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T30	14		T49	9		T166	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T11	10		T35	4		T36	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T116	1		T127	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T72	1		T34	3		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	5		T14	16		T115	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1629	1			T2	1		T30	3		T73	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	6		T5	6		T11	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T16	8		T48	16		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T4	12		T114	12		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T13	11		T40	4		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T72	1		T16	3		T115	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T49	1		T231	1		T252	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T41	1		T134	8		T253	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19173	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T14	19		T33	9		T131	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T16	23		T171	6		T193	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T34	1		T173	11		T153	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T178	9		T48	1		T128	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T118	11		T184	7		T291	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T5	10		T13	11		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T114	9		T147	10		T179	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T114	17		T110	3		T125	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T30	1		T166	9		T119	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	2		T35	3		T36	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T127	11		T128	4		T192	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T34	1		T185	11		T171	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T122	14		T38	1		T191	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T30	4		T73	15		T113	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T4	3		T5	5		T109	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T16	7		T48	11		T127	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	13		T114	7		T128	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T13	11		T155	2		T127	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T16	4		T49	4		T171	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T231	11		T252	12		T210	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T134	4		T253	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T33	1		T16	1		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T33	4		T131	14		T120	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T127	1		T298	11		T247	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T16	3		T49	5		T116	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T132	3		T254	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T297	14		T299	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T117	1		T181	1		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T2	1		T14	33		T33	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	17		T16	8		T178	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T203	12		T187	1		T118	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	12		T8	6		T12	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T114	8		T147	9		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T114	15		T110	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	10		T30	14		T49	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T11	10		T35	4		T36	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T116	1		T127	1		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T2	1		T72	1		T111	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	5		T14	16		T122	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T30	3		T34	3		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	6		T11	2		T115	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1679	1			T73	2		T113	3		T129	37
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	18		T114	12		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T13	11		T40	4		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T72	1		T41	1		T115	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19142	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T127	11		T298	4		T210	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T16	4		T49	4		T134	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T254	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T181	9		T171	6		T74	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T33	4		T34	1		T173	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	23		T178	9		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T118	11		T182	18		T184	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T5	10		T13	11		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T114	9		T147	10		T191	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T114	17		T110	3		T125	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T30	1		T166	9		T179	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	2		T35	3		T36	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T127	11		T128	4		T17	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T171	3		T192	10		T193	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T122	14		T38	1		T176	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T30	4		T34	1		T185	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	5		T185	2		T179	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	983	1			T73	15		T113	21		T16	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T4	16		T114	7		T109	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	373	1			T13	11		T155	2		T127	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T128	5		T177	4		T171	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	1		T16	25		T117	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	1		T14	1		T34	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	1		T178	10		T48	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T203	1		T187	1		T118	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T5	11		T8	1		T13	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	1		T114	10		T147	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T114	18		T110	4		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T30	3		T49	1		T166	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	7		T35	6		T36	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T116	1		T127	12		T128	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T72	1		T34	3		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	1		T14	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T2	1		T30	5		T73	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	4		T5	6		T11	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T16	8		T48	12		T127	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	14		T114	8		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T13	12		T40	1		T155	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T72	1		T16	6		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T49	1		T231	12		T252	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T41	1		T134	5		T253	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19347	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T14	1		T33	10		T131	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	16		T16	6		T193	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	13		T156	4		T182	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T12	9		T178	13		T109	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T203	11		T184	2		T148	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	11		T8	5		T13	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	9		T114	7		T147	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T114	14		T125	12		T250	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T30	12		T49	8		T166	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	5		T35	1		T36	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T125	11		T216	10		T148	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T34	1		T111	22		T185	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	4		T14	15		T115	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T30	2		T129	34		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T4	5		T5	5		T109	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	7		T48	15		T122	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	11		T114	11		T108	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T13	10		T40	3		T112	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T16	1		T115	13		T49	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T252	13		T210	6		T196	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T134	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T132	2		T248	7		T255	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T14	18		T33	3		T131	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T127	12		T298	5		T247	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T16	6		T49	5		T116	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T132	1		T254	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T297	1		T299	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T117	1		T181	10		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	1		T14	2		T33	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T16	25		T178	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T203	1		T187	1		T118	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T5	11		T8	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T114	10		T147	11		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T114	18		T110	4		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	1		T30	3		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T11	7		T35	6		T36	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T116	1		T127	12		T128	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T2	1		T72	1		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	1		T14	1		T122	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T30	5		T34	3		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	6		T11	2		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T73	17		T113	24		T129	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T4	18		T114	8		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	451	1			T13	12		T40	1		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T72	1		T41	1		T115	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19287	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T298	10		T210	6		T300	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T16	1		T49	4		T134	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T132	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T297	13		T299	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T219	10		T74	1		T218	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	31		T33	3		T131	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	16		T16	6		T178	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T203	11		T182	14		T184	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T5	11		T8	5		T12	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T114	7		T147	8		T191	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T114	14		T125	12		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	9		T30	12		T49	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T11	5		T35	1		T36	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	2		T125	11		T183	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T111	4		T186	2		T301	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	4		T14	15		T122	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T30	2		T34	1		T111	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	5		T115	7		T108	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T129	34		T16	7		T130	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	16		T114	11		T108	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T13	10		T40	3		T112	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T115	13		T108	12		T112	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20