Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25178

1

T1

17

T2

1

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3304

1

T2

1

T4

9

T5

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22452

1

T2

2

T3

18

T5

16

auto[1]

6030

1

T1

17

T4

34

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	363	1			T5	5		T40	4		T41	1
values[0]	59	1			T160	1		T207	13		T169	2
values[1]	732	1			T1	17		T4	25		T12	10
values[2]	2966	1			T12	10		T73	17		T113	24
values[3]	568	1			T13	22		T173	12		T35	7
values[4]	637	1			T34	4		T36	14		T122	13
values[5]	742	1			T4	9		T5	11		T178	23
values[6]	601	1			T11	12		T30	13		T72	1
values[7]	626	1			T2	1		T13	26		T30	2
values[8]	965	1			T8	6		T14	16		T30	7
values[9]	936	1			T2	1		T5	22		T11	2
minimum	19287	1			T3	18		T6	20		T7	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	680	1			T1	17		T4	25		T12	10
values[1]	2997	1			T12	10		T73	17		T113	24
values[2]	504	1			T13	22		T173	12		T128	6
values[3]	630	1			T34	4		T178	23		T36	14
values[4]	789	1			T4	9		T5	11		T115	14
values[5]	543	1			T11	12		T30	15		T72	1
values[6]	770	1			T2	1		T13	26		T33	13
values[7]	956	1			T5	22		T8	6		T14	16
values[8]	922	1			T2	1		T5	5		T14	33
values[9]	145	1			T11	2		T108	14		T112	3
minimum	19546	1			T3	18		T6	20		T7	178

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	17		T4	12		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	10		T40	5		T114	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1619	1			T73	2		T113	3		T129	37
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	10		T114	12		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T128	1		T187	1		T131	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T13	11		T173	1		T111	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T178	14		T36	8		T122	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T34	3		T138	11		T125	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T115	14		T48	1		T116	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	6		T5	6		T49	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	10		T30	13		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T30	1		T72	1		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T33	9		T155	1		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	1		T13	15		T185	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T8	6		T30	3		T72	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	12		T14	16		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T2	1		T14	19		T16	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	5		T14	14		T40	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T11	2		T203	12		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T108	14		T112	3		T231	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19204	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T127	1		T207	1		T169	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	13		T153	1		T38	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T114	17		T109	10		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	932	1			T73	15		T113	21		T137	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T114	7		T16	4		T35	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T128	5		T131	14		T190	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T13	11		T173	11		T19	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T178	9		T36	6		T122	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T34	1		T138	10		T125	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T48	1		T189	11		T17	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T4	3		T5	5		T147	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T11	2		T192	14		T184	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T30	1		T34	1		T179	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T33	4		T155	2		T177	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	11		T185	2		T192	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T30	4		T114	9		T16	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	10		T127	11		T122	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T16	7		T119	3		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T48	11		T110	3		T181	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T229	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T231	11		T81	12		T18	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T33	1		T16	1		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T127	11		T207	12		T296	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T41	1		T203	12		T160	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	5		T40	4		T108	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T160	1		T238	3		T302	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T207	1		T169	2		T255	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	17		T4	12		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	10		T40	5		T114	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1665	1			T73	2		T113	3		T129	37
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	10		T114	12		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T128	1		T187	1		T190	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	11		T173	1		T35	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	8		T122	6		T185	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T34	3		T138	11		T125	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T178	14		T115	14		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	6		T5	6		T49	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	10		T30	13		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T72	1		T34	3		T147	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T33	9		T155	1		T177	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	1		T13	15		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	6		T30	3		T114	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T14	16		T108	13		T122	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T2	1		T11	2		T14	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	12		T14	14		T48	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19142	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T39	1		T205	3		T277	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T81	12		T18	8		T303	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T238	3		T234	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T207	12		T255	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	13		T153	1		T38	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T114	17		T127	11		T109	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T73	15		T113	21		T137	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T114	7		T16	4		T49	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T128	5		T190	13		T119	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	11		T173	11		T35	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T36	6		T122	7		T185	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T34	1		T138	10		T125	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T178	9		T48	1		T189	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T4	3		T5	5		T197	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T11	2		T17	5		T184	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T34	1		T147	10		T179	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T33	4		T155	2		T177	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	11		T30	1		T185	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T30	4		T114	9		T166	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T122	14		T109	12		T179	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T16	30		T119	3		T183	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	10		T48	11		T127	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	1		T4	14		T153	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	1		T40	1		T114	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T73	17		T113	24		T129	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T12	1		T114	8		T16	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T128	6		T187	1		T131	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T13	12		T173	12		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T178	10		T36	9		T122	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T34	3		T138	11		T125	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T115	1		T48	2		T116	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	4		T5	6		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T11	7		T30	1		T192	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T30	2		T72	1		T34	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T33	10		T155	3		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	1		T13	12		T185	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T8	1		T30	5		T72	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T5	11		T14	1		T127	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T2	1		T14	1		T16	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	1		T14	1		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T11	2		T203	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T108	1		T112	1		T231	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19371	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T127	12		T207	13		T169	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	16		T4	11		T38	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T12	9		T40	4		T114	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T129	34		T130	13		T235	32
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	9		T114	11		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T131	12		T190	15		T217	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T13	10		T111	4		T19	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T178	13		T36	5		T122	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T34	1		T138	10		T125	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T115	13		T189	17		T112	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	5		T5	5		T49	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	5		T30	12		T184	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T156	4		T216	10		T236	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T33	3		T177	10		T184	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	14		T185	4		T156	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T8	5		T30	2		T114	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	11		T14	15		T108	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T14	18		T16	7		T115	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	4		T14	13		T40	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T203	11		T229	15		T304	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T108	13		T112	2		T18	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T191	11		T149	2		T266	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T261	12		T224	12		T296	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T41	1		T203	1		T160	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T5	1		T40	1		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T160	1		T238	6		T302	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T207	13		T169	2		T255	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	1		T4	14		T153	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T40	1		T114	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T73	17		T113	24		T129	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	1		T114	8		T16	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T128	6		T187	1		T190	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	12		T173	12		T35	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	9		T122	8		T185	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T34	3		T138	11		T125	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T178	10		T115	1		T48	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	4		T5	6		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	7		T30	1		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T72	1		T34	4		T147	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T33	10		T155	3		T177	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	1		T13	12		T30	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T8	1		T30	5		T114	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T14	1		T108	1		T122	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T2	1		T11	2		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	11		T14	1		T48	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19287	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T203	11		T39	3		T184	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T5	4		T40	3		T108	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T255	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	16		T4	11		T125	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	9		T40	4		T114	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T129	34		T130	13		T235	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	9		T114	11		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T190	15		T132	7		T170	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T13	10		T35	1		T111	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T36	5		T122	5		T185	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T34	1		T138	10		T125	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T178	13		T115	13		T189	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	5		T5	5		T49	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	5		T30	12		T17	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T147	8		T132	2		T156	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T33	3		T177	10		T168	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T13	14		T185	4		T216	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	5		T30	2		T114	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T14	15		T108	12		T122	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T14	18		T16	13		T115	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	11		T14	13		T48	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20