Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24799

1

T2

2

T3

18

T4

34

auto[ADC_CTRL_FILTER_COND_OUT]

3683

1

T1

17

T5

11

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21742

1

T1

17

T2

2

T3

18

auto[1]

6740

1

T4

25

T5

11

T7

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	761	1			T7	4		T11	2		T33	8
values[0]	52	1			T153	2		T17	9		T261	13
values[1]	676	1			T12	10		T13	26		T30	7
values[2]	2815	1			T14	16		T73	17		T113	24
values[3]	822	1			T5	22		T11	12		T12	10
values[4]	729	1			T2	1		T4	9		T5	16
values[5]	542	1			T14	19		T155	3		T147	19
values[6]	749	1			T1	17		T11	2		T16	38
values[7]	692	1			T13	22		T173	12		T115	8
values[8]	621	1			T4	25		T8	6		T14	14
values[9]	1238	1			T2	1		T40	5		T72	1
minimum	18785	1			T3	18		T6	20		T7	174

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	660	1			T12	10		T13	26		T30	7
values[1]	3023	1			T5	22		T14	16		T73	17
values[2]	632	1			T4	9		T5	11		T11	12
values[3]	744	1			T2	1		T5	5		T72	1
values[4]	558	1			T14	19		T155	3		T147	19
values[5]	745	1			T1	17		T11	2		T13	22
values[6]	716	1			T14	14		T33	13		T114	32
values[7]	686	1			T4	25		T8	6		T40	5
values[8]	1031	1			T2	1		T72	1		T34	5
values[9]	232	1			T114	19		T190	29		T177	15
minimum	19455	1			T3	18		T6	20		T7	178

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	10		T30	3		T49	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	15		T153	1		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1712	1			T5	12		T14	16		T73	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T109	11		T123	1		T112	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	6		T11	10		T12	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	6		T30	13		T122	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	1		T5	5		T115	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T72	1		T159	1		T187	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T155	1		T147	9		T108	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	19		T122	6		T109	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	11		T127	1		T177	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T1	17		T11	2		T16	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T173	1		T115	8		T131	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	14		T33	9		T114	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	12		T8	6		T40	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T114	8		T36	8		T116	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T2	1		T72	1		T34	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T128	1		T156	15		T182	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T114	12		T190	16		T177	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T78	1		T216	11		T222	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19190	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T111	19		T177	10		T182	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T30	4		T185	11		T179	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	11		T153	1		T171	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T5	10		T73	15		T113	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T109	10		T171	6		T120	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T4	3		T11	2		T30	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	5		T122	14		T38	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T189	11		T128	4		T191	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T231	11		T38	3		T207	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T155	2		T147	10		T191	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T122	7		T109	12		T110	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T13	11		T127	11		T177	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T16	27		T178	9		T128	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T173	11		T131	14		T119	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T33	4		T114	17		T35	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	13		T34	1		T125	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T114	9		T36	6		T127	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T34	1		T48	11		T49	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T128	4		T156	14		T182	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T114	7		T190	13		T177	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T257	7		T305	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T33	1		T16	1		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T177	9		T193	7		T306	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	596	1			T7	4		T11	2		T33	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T194	4		T260	1		T266	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T17	4		T261	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T153	1		T259	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	10		T30	3		T40	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	15		T111	19		T177	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T14	16		T73	2		T113	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T123	1		T120	1		T125	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	12		T11	10		T12	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T30	13		T122	11		T109	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	1		T4	6		T5	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	6		T72	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T155	1		T147	9		T108	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	19		T122	6		T109	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T127	1		T177	1		T227	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	17		T11	2		T16	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	11		T173	1		T115	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T127	1		T128	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	12		T8	6		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	14		T33	9		T114	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T2	1		T40	5		T72	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T36	8		T128	1		T117	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18640	1			T3	18		T6	20		T7	174
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T179	13		T18	8		T298	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T194	16		T260	11		T266	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T17	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T153	1		T259	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T30	4		T185	11		T179	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	11		T177	9		T171	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	894	1			T73	15		T113	21		T137	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T120	2		T125	13		T170	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	10		T11	2		T30	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T122	14		T109	10		T171	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T4	3		T189	11		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	5		T231	11		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T155	2		T147	10		T128	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T122	7		T109	12		T110	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T127	11		T177	1		T168	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T16	27		T178	9		T179	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	11		T173	11		T131	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T127	2		T128	5		T138	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	13		T34	1		T125	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T33	4		T114	26		T35	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T114	7		T34	1		T48	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T36	6		T128	4		T156	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	1		T30	5		T49	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	12		T153	2		T171	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T5	11		T14	1		T73	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T109	11		T123	1		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T4	4		T11	7		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	6		T30	1		T122	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T2	1		T5	1		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T72	1		T159	1		T187	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T155	3		T147	11		T108	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	1		T122	8		T109	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	12		T127	12		T177	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T1	1		T11	2		T16	31
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T173	12		T115	1		T131	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T14	1		T33	10		T114	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	14		T8	1		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T114	10		T36	9		T116	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T2	1		T72	1		T34	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T128	5		T156	15		T182	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T114	8		T190	14		T177	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T78	1		T216	1		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19350	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T111	1		T177	10		T182	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T12	9		T30	2		T185	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	14		T125	12		T170	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T5	11		T14	15		T129	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T109	10		T112	2		T219	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T4	5		T11	5		T12	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	5		T30	12		T122	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	4		T115	13		T189	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T243	8		T186	2		T271	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T147	8		T108	25		T191	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T14	18		T122	5		T109	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	10		T168	1		T148	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	16		T16	7		T178	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T115	7		T131	12		T250	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	13		T33	3		T114	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	11		T8	5		T40	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T114	7		T36	5		T132	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T48	15		T49	4		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T156	14		T182	14		T183	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T114	11		T190	15		T177	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T216	10		T222	10		T305	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T40	3		T17	2		T156	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T111	18		T177	9		T193	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	615	1			T7	4		T11	2		T33	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T194	20		T260	12		T266	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T17	7		T261	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T153	2		T259	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	1		T30	5		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	12		T111	1		T177	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T14	1		T73	17		T113	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T123	1		T120	3		T125	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	11		T11	7		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T30	1		T122	15		T109	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	1		T4	4		T5	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	6		T72	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T155	3		T147	11		T108	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	1		T122	8		T109	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T127	12		T177	2		T227	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T1	1		T11	2		T16	31
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	12		T173	12		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T127	3		T128	6		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T4	14		T8	1		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	1		T33	10		T114	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T2	1		T40	1		T72	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T36	9		T128	5		T117	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18785	1			T3	18		T6	20		T7	174
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T18	4		T298	10		T218	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T266	2		T222	10		T292	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T17	2		T261	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T259	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	9		T30	2		T40	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	14		T111	18		T177	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T14	15		T129	34		T130	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T125	12		T170	3		T219	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	11		T11	5		T12	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T30	12		T122	10		T109	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	5		T5	4		T115	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T5	5		T38	2		T186	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T147	8		T108	25		T191	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	18		T122	5		T109	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T168	1		T307	2		T251	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	16		T16	7		T178	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	10		T115	7		T131	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T138	10		T81	8		T197	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T4	11		T8	5		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T14	13		T33	3		T114	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T40	4		T114	11		T48	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T36	5		T132	15		T156	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20