Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22181

1

T2

1

T3

18

T5

16

auto[ADC_CTRL_FILTER_COND_OUT]

6301

1

T1

17

T2

1

T4

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

17

T2

1

T3

18

auto[1]

6043

1

T2

1

T5

27

T11

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	199	1			T108	9		T111	19		T124	1
values[0]	48	1			T139	1		T211	26		T212	4
values[1]	611	1			T4	9		T14	16		T72	1
values[2]	645	1			T1	17		T13	26		T30	2
values[3]	975	1			T2	1		T8	6		T11	2
values[4]	821	1			T5	27		T41	1		T48	27
values[5]	783	1			T12	10		T115	14		T108	13
values[6]	682	1			T2	1		T5	11		T14	19
values[7]	721	1			T30	13		T16	15		T34	4
values[8]	609	1			T4	25		T14	14		T33	13
values[9]	3101	1			T11	12		T13	22		T30	7
minimum	19287	1			T3	18		T6	20		T7	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	578	1			T14	16		T30	2		T72	1
values[1]	3198	1			T1	17		T2	1		T8	6
values[2]	682	1			T11	2		T12	10		T40	5
values[3]	863	1			T5	27		T12	10		T41	1
values[4]	715	1			T5	11		T72	1		T16	7
values[5]	748	1			T2	1		T14	19		T40	4
values[6]	704	1			T30	13		T34	4		T35	7
values[7]	538	1			T4	25		T13	22		T14	14
values[8]	712	1			T11	12		T30	7		T114	19
values[9]	198	1			T153	2		T125	28		T204	11
minimum	19546	1			T3	18		T4	9		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T30	1		T173	1		T116	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	16		T72	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T34	1		T36	8		T117	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1808	1			T1	17		T2	1		T8	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	10		T40	5		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	2		T49	1		T182	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	5		T41	1		T48	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	12		T12	10		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	6		T72	1		T16	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T108	13		T203	12		T185	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T2	1		T128	1		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T14	19		T40	4		T16	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T116	1		T123	1		T131	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T30	13		T34	3		T35	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	14		T114	8		T108	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	12		T13	11		T33	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	10		T115	8		T108	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T30	3		T114	12		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T153	1		T74	3		T260	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T125	14		T204	1		T19	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19210	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T4	6		T127	1		T185	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T30	1		T173	11		T231	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T109	22		T37	1		T38	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T36	6		T179	11		T171	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1076	1			T13	11		T73	15		T113	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T48	1		T147	10		T166	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T182	8		T191	12		T205	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T48	11		T81	12		T204	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	10		T127	11		T110	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	5		T16	4		T192	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T185	11		T119	12		T206	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T128	4		T17	2		T184	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T16	7		T178	9		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T131	14		T171	6		T120	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T34	1		T35	3		T17	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T114	9		T182	18		T207	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	13		T13	11		T33	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	2		T170	7		T168	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T30	4		T114	7		T128	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T153	1		T74	2		T260	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T125	14		T204	10		T308	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T33	1		T16	1		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T4	3		T127	2		T185	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T108	9		T124	1		T240	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T111	19		T132	3		T125	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T139	1		T142	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T211	13		T212	3		T198	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T173	1		T116	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	6		T14	16		T72	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T30	1		T34	1		T36	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	17		T13	15		T49	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	10		T40	5		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T2	1		T8	6		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	5		T41	1		T48	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	12		T127	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T115	14		T159	1		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	10		T108	13		T203	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T2	1		T5	6		T72	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T14	19		T40	4		T178	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T116	1		T123	1		T131	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T30	13		T16	8		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	14		T108	14		T182	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	12		T33	9		T114	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	10		T114	8		T115	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1721	1			T13	11		T30	3		T73	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19142	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T170	6		T168	1		T260	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T125	14		T309	1		T246	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T142	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T211	13		T212	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T173	11		T127	11		T190	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T4	3		T127	2		T109	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T30	1		T36	6		T171	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	11		T49	4		T122	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T48	1		T147	10		T166	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T16	23		T34	1		T122	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T48	11		T156	14		T81	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	10		T127	11		T110	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T192	14		T243	9		T149	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T119	12		T238	3		T271	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	5		T16	4		T128	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T178	9		T185	11		T138	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T131	14		T171	6		T120	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T16	7		T34	1		T155	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T182	18		T207	12		T213	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T4	13		T33	4		T114	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	2		T114	9		T153	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	971	1			T13	11		T30	4		T73	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T30	2		T173	12		T116	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	1		T72	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T34	1		T36	9		T117	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1441	1			T1	1		T2	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	1		T40	1		T48	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T11	2		T49	1		T182	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T41	1		T48	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	11		T12	1		T127	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	6		T72	1		T16	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T108	1		T203	1		T185	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	1		T128	5		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T14	1		T40	1		T16	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T116	1		T123	1		T131	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T30	1		T34	4		T35	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	1		T114	10		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	14		T13	12		T33	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	7		T115	1		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T30	5		T114	8		T128	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T153	2		T74	4		T260	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T125	15		T204	11		T19	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19356	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T4	4		T127	3		T185	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T125	12		T214	6		T310	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	15		T109	19		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T36	5		T183	13		T215	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1443	1			T1	16		T8	5		T13	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	9		T40	4		T147	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T182	8		T191	8		T205	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	4		T48	15		T216	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	11		T12	9		T218	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	5		T16	1		T115	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T108	12		T203	11		T185	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T17	1		T184	2		T19	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T14	18		T40	3		T16	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T131	12		T216	10		T219	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T30	12		T35	1		T49	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T14	13		T114	7		T108	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T4	11		T13	10		T33	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	5		T115	7		T108	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T30	2		T114	11		T111	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T74	1		T220	9		T201	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T125	13		T222	10		T218	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T190	15		T277	5		T223	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T4	5		T185	4		T300	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T108	1		T124	1		T240	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T111	1		T132	1		T125	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T139	1		T142	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T211	14		T212	3		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T173	12		T116	1		T127	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	4		T14	1		T72	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T30	2		T34	1		T36	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	1		T13	12		T49	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	1		T40	1		T48	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T2	1		T8	1		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	1		T41	1		T48	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T5	11		T127	12		T110	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T115	1		T159	1		T192	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	1		T108	1		T203	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	1		T5	6		T72	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T14	1		T40	1		T178	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T116	1		T123	1		T131	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T30	1		T16	8		T34	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	1		T108	1		T182	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	14		T33	10		T114	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	7		T114	10		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1336	1			T13	12		T30	5		T73	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19287	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T108	8		T170	3		T168	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T111	18		T132	2		T125	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T142	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T211	12		T212	1		T198	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T190	15		T125	12		T277	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T4	5		T14	15		T109	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T36	5		T183	13		T215	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	16		T13	14		T49	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	9		T40	4		T147	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T8	5		T16	6		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	4		T48	15		T111	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	11		T182	8		T218	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T115	13		T219	7		T217	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	9		T108	12		T203	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T5	5		T16	1		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	18		T40	3		T178	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T131	12		T216	10		T219	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T30	12		T16	7		T49	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T14	13		T108	13		T182	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	11		T33	3		T114	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	5		T114	7		T115	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1356	1			T13	10		T30	2		T114	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20