Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T30	2		T173	12		T116	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	4		T14	1		T72	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T34	1		T36	9		T117	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1454	1			T1	1		T2	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	1		T40	1		T48	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	2		T49	1		T182	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T41	1		T48	12		T81	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	11		T12	1		T127	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	7		T16	6		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T108	1		T203	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	1		T72	1		T128	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T14	1		T40	1		T16	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T116	1		T123	1		T131	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T30	1		T35	6		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	1		T114	10		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	14		T13	12		T33	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	7		T115	1		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T30	5		T128	6		T111	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T153	2		T124	1		T74	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T114	8		T125	15		T204	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19288	1			T3	18		T6	20		T7	178
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T190	15		T125	12		T214	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	5		T14	15		T122	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T36	5		T183	13		T215	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1439	1			T1	16		T8	5		T13	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	9		T40	4		T147	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T182	8		T191	8		T205	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T48	15		T216	13		T217	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	11		T12	9		T218	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	9		T16	1		T115	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T108	12		T203	11		T132	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T17	1		T184	2		T219	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	18		T40	3		T16	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T131	12		T182	14		T216	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T30	12		T35	1		T112	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T14	13		T114	7		T108	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T4	11		T13	10		T33	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	5		T115	7		T108	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T30	2		T111	18		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T74	1		T220	9		T221	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T114	11		T125	13		T222	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T201	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T202	1		T210	3		T142	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T185	3		T139	1		T211	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T173	12		T116	1		T127	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	4		T14	1		T72	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T30	2		T36	9		T117	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	1		T13	12		T49	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	1		T40	1		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T2	1		T8	1		T16	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T41	1		T48	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T5	11		T11	2		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T16	6		T115	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	1		T178	10		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T2	1		T5	6		T72	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T14	1		T40	1		T16	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T116	1		T128	5		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T30	1		T34	4		T155	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	1		T108	1		T182	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	14		T33	10		T114	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	7		T114	10		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1361	1			T13	12		T30	5		T73	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19287	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T201	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T210	6		T142	3		T144	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T185	4		T211	12		T212	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T190	15		T125	12		T223	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	5		T14	15		T109	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T36	5		T183	13		T215	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	16		T13	14		T49	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	9		T40	4		T147	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	5		T16	6		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	4		T48	15		T111	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	11		T182	8		T224	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T16	1		T115	13		T219	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	9		T178	13		T108	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T5	5		T17	1		T184	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T14	18		T40	3		T16	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T131	12		T216	10		T18	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T30	12		T112	2		T17	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T14	13		T108	13		T182	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	11		T33	3		T114	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	5		T114	7		T115	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1423	1			T13	10		T30	2		T114	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20