Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24843

1

T2

1

T3

18

T4

34

auto[ADC_CTRL_FILTER_COND_OUT]

3639

1

T1

17

T2

1

T8

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22220

1

T3

18

T4

9

T5

38

auto[1]

6262

1

T1

17

T2

2

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T160	1		T19	1		T237	1
values[0]	8	1			T238	6		T139	1		T239	1
values[1]	701	1			T2	1		T14	33		T16	15
values[2]	734	1			T5	22		T30	2		T33	13
values[3]	672	1			T2	1		T11	2		T13	22
values[4]	809	1			T1	17		T13	26		T49	9
values[5]	561	1			T8	6		T166	20		T127	12
values[6]	507	1			T14	16		T114	17		T34	4
values[7]	796	1			T12	10		T30	7		T114	32
values[8]	741	1			T5	11		T11	12		T40	5
values[9]	3645	1			T4	34		T5	5		T12	10
minimum	19287	1			T3	18		T6	20		T7	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	938	1			T2	1		T5	22		T14	33
values[1]	645	1			T30	2		T72	1		T33	13
values[2]	860	1			T1	17		T2	1		T11	2
values[3]	567	1			T13	26		T49	9		T122	13
values[4]	616	1			T8	6		T14	16		T35	7
values[5]	584	1			T12	10		T114	17		T34	4
values[6]	3056	1			T30	7		T40	5		T73	17
values[7]	741	1			T5	11		T11	12		T114	19
values[8]	889	1			T4	25		T5	5		T12	10
values[9]	284	1			T4	9		T240	1		T39	7
minimum	19302	1			T3	18		T6	20		T7	178

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	1		T5	12		T14	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T14	19		T16	8		T178	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T72	1		T33	9		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T30	1		T127	1		T111	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T11	2		T40	4		T147	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	17		T2	1		T13	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T49	5		T128	1		T109	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	15		T122	6		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T35	4		T166	11		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	6		T14	16		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	10		T34	3		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T114	8		T115	14		T49	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1704	1			T30	3		T73	2		T113	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T40	5		T114	15		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	6		T114	12		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	10		T16	8		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	12		T5	5		T12	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T30	13		T112	3		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T4	6		T39	6		T186	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T240	1		T172	1		T19	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19145	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T171	1		T202	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	10		T183	21		T18	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T16	7		T178	9		T48	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T33	4		T173	11		T179	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T30	1		T127	11		T231	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T147	10		T122	14		T131	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	11		T128	4		T180	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	4		T128	5		T109	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	11		T122	7		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T35	3		T166	9		T127	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T38	1		T171	6		T194	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T34	1		T155	2		T127	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T114	9		T181	9		T182	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T30	4		T73	15		T113	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T114	17		T81	12		T183	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	5		T114	7		T191	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	2		T16	23		T153	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	13		T16	4		T185	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T185	2		T179	11		T171	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T4	3		T39	1		T186	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T172	5		T176	7		T195	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T33	1		T16	1		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T171	3		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T19	1		T161	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T160	1		T237	1		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T238	3		T239	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T139	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	1		T14	14		T115	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	19		T16	8		T36	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	12		T33	9		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T30	1		T178	14		T48	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	2		T40	4		T72	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	1		T13	11		T72	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T49	5		T147	9		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	17		T13	15		T122	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T166	11		T127	1		T109	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	6		T159	1		T117	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T34	3		T41	1		T35	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	16		T114	8		T115	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	10		T30	3		T108	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T114	15		T117	1		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	6		T114	12		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	10		T40	5		T16	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1778	1			T4	18		T5	5		T12	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T30	13		T112	3		T117	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19142	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T241	9		T242	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T238	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T184	7		T183	21		T18	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T16	7		T36	6		T189	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	10		T33	4		T173	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T30	1		T178	9		T48	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T122	14		T109	10		T131	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	11		T128	4		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T49	4		T147	10		T128	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	11		T122	7		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T166	9		T127	11		T109	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T171	6		T156	14		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T34	1		T35	3		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T114	9		T38	1		T182	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T30	4		T190	13		T191	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T114	17		T181	9		T191	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	5		T114	7		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	2		T16	23		T153	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T4	16		T73	15		T113	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T185	2		T171	12		T192	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	1		T5	11		T14	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T14	1		T16	8		T178	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T72	1		T33	10		T173	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T30	2		T127	12		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T11	2		T40	1		T147	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	1		T2	1		T13	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	5		T128	6		T109	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	12		T122	8		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T35	6		T166	10		T127	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	1		T14	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	1		T34	3		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T114	10		T115	1		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T30	5		T73	17		T113	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T40	1		T114	18		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	6		T114	8		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	7		T16	25		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	14		T5	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T30	1		T112	1		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T4	4		T39	4		T186	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T240	1		T172	6		T19	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19295	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T171	4		T202	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	11		T14	13		T115	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T14	18		T16	7		T178	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T33	3		T138	10		T170	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T111	18		T17	2		T215	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T40	3		T147	8		T122	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	16		T13	10		T31	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T49	4		T109	10		T125	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	14		T122	5		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T35	1		T166	10		T109	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T8	5		T14	15		T112	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	9		T34	1		T111	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T114	7		T115	13		T49	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T30	2		T129	34		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T40	4		T114	14		T183	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	5		T114	11		T191	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	5		T16	6		T125	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	11		T5	4		T12	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T30	12		T112	2		T185	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T4	5		T39	3		T186	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T176	3		T195	14		T244	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T184	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T19	1		T161	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T160	1		T237	1		T241	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T238	6		T239	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T139	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	1		T14	1		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	1		T16	8		T36	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T5	11		T33	10		T173	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T30	2		T178	10		T48	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	2		T40	1		T72	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	1		T13	12		T72	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T49	5		T147	11		T128	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	1		T13	12		T122	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T166	10		T127	12		T109	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	1		T159	1		T117	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	3		T41	1		T35	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	1		T114	10		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	1		T30	5		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T114	18		T117	1		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	6		T114	8		T34	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T11	7		T40	1		T16	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T4	18		T5	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	425	1			T30	1		T112	1		T117	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19287	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T242	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	13		T115	7		T108	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	18		T16	7		T36	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	11		T33	3		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T178	13		T48	15		T111	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T40	3		T122	10		T109	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	10		T31	3		T215	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T49	4		T147	8		T156	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	16		T13	14		T122	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T166	10		T109	9		T81	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T8	5		T132	2		T156	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T34	1		T35	1		T132	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T14	15		T114	7		T115	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	9		T30	2		T108	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T114	14		T191	8		T183	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	5		T114	11		T182	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	5		T40	4		T16	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T4	16		T5	4		T12	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T30	12		T112	2		T185	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20