Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24857

1

T1

17

T2

1

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3625

1

T2

1

T4

34

T5

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22493

1

T1

17

T2

1

T3

18

auto[1]

5989

1

T2

1

T4

25

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	38	1			T116	1		T245	14		T246	23
values[0]	22	1			T247	1		T174	4		T248	8
values[1]	679	1			T2	1		T14	33		T33	13
values[2]	705	1			T1	17		T13	26		T16	31
values[3]	599	1			T5	22		T8	6		T12	10
values[4]	585	1			T12	10		T30	13		T114	32
values[5]	1025	1			T11	12		T14	16		T30	2
values[6]	541	1			T2	1		T5	5		T72	1
values[7]	597	1			T5	11		T11	2		T34	4
values[8]	2956	1			T4	34		T30	7		T73	17
values[9]	1448	1			T13	22		T40	4		T72	1
minimum	19287	1			T3	18		T6	20		T7	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	879	1			T1	17		T2	1		T14	33
values[1]	655	1			T12	10		T13	26		T178	23
values[2]	473	1			T5	22		T8	6		T12	10
values[3]	844	1			T30	15		T114	32		T49	9
values[4]	804	1			T11	12		T35	7		T36	14
values[5]	675	1			T5	16		T14	16		T72	1
values[6]	2880	1			T2	1		T4	34		T11	2
values[7]	842	1			T13	22		T114	19		T16	15
values[8]	882	1			T40	4		T72	1		T16	7
values[9]	216	1			T115	14		T49	1		T231	12
minimum	19332	1			T3	18		T6	20		T7	178

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	17		T16	8		T117	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	1		T14	33		T33	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	10		T13	15		T178	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T48	1		T203	12		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T5	12		T8	6		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	10		T114	8		T147	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T114	15		T159	1		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T30	14		T49	9		T166	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	10		T35	4		T36	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T116	1		T127	1		T189	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	6		T72	1		T34	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	5		T14	16		T115	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1642	1			T2	1		T30	3		T73	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	18		T11	2		T123	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	11		T16	8		T48	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T114	12		T34	1		T108	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T40	4		T16	3		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T72	1		T41	1		T49	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T49	1		T231	1		T249	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T115	14		T171	1		T250	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19160	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T251	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T16	23		T181	9		T171	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T33	4		T34	1		T173	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	11		T178	9		T128	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	1		T118	11		T184	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T5	10		T37	1		T119	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T114	9		T147	10		T179	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T114	17		T110	3		T125	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	1		T166	9		T119	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	2		T35	3		T36	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T127	11		T189	11		T128	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	5		T34	1		T185	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T122	14		T38	1		T191	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T30	4		T73	15		T113	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T4	16		T179	11		T120	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	11		T16	7		T48	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T114	7		T128	5		T109	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T16	4		T155	2		T127	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T49	4		T81	12		T180	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T231	11		T252	12		T210	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T171	12		T134	4		T253	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T33	1		T16	1		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T251	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T116	1		T245	1		T246	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T174	1		T248	8		T254	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T247	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T117	1		T181	1		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	1		T14	33		T33	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	17		T13	15		T16	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T48	1		T203	12		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T5	12		T8	6		T12	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T114	8		T147	9		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T114	15		T110	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	10		T30	13		T49	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T11	10		T36	8		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T14	16		T30	1		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	1		T72	1		T35	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	5		T122	11		T31	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	6		T34	3		T111	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	2		T115	8		T108	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1663	1			T30	3		T73	2		T113	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	18		T114	12		T108	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	412	1			T13	11		T40	4		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T72	1		T34	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19142	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T245	13		T246	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T174	3		T254	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T181	9		T171	6		T74	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T33	4		T34	1		T173	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	11		T16	23		T178	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T48	1		T182	18		T191	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T5	10		T37	1		T177	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T114	9		T147	10		T118	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T114	17		T110	3		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T166	9		T179	16		T119	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	2		T36	6		T17	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T30	1		T127	11		T189	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T35	3		T190	13		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T122	14		T38	1		T193	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T5	5		T34	1		T185	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T185	2		T179	11		T191	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T30	4		T73	15		T113	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T4	16		T114	7		T109	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T13	11		T16	4		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T49	4		T128	5		T177	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T1	1		T16	25		T117	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	1		T14	2		T33	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	1		T13	12		T178	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T48	2		T203	1		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T5	11		T8	1		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	1		T114	10		T147	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T114	18		T159	1		T110	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T30	3		T49	1		T166	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	7		T35	6		T36	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T116	1		T127	12		T189	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	6		T72	1		T34	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	1		T14	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T2	1		T30	5		T73	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	18		T11	2		T123	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	12		T16	8		T48	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T114	8		T34	1		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T40	1		T16	6		T155	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T72	1		T41	1		T49	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T49	1		T231	12		T249	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T115	1		T171	13		T250	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19301	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T251	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	16		T16	6		T132	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	31		T33	3		T131	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	9		T13	14		T178	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T203	11		T184	2		T18	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T5	11		T8	5		T40	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	9		T114	7		T147	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T114	14		T125	12		T184	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T30	12		T49	8		T166	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	5		T35	1		T36	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T189	17		T125	11		T216	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	5		T34	1		T111	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	4		T14	15		T115	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T30	2		T129	34		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	16		T81	8		T19	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	10		T16	7		T48	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T114	11		T108	8		T109	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T40	3		T16	1		T112	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T49	4		T108	12		T170	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T252	13		T210	6		T196	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T115	13		T250	6		T134	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T255	12		T256	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T251	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T116	1		T245	14		T246	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T174	4		T248	1		T254	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T247	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T117	1		T181	10		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	1		T14	2		T33	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	1		T13	12		T16	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T48	2		T203	1		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T5	11		T8	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T114	10		T147	11		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T114	18		T110	4		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	1		T30	1		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T11	7		T36	9		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T14	1		T30	2		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	1		T72	1		T35	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	1		T122	15		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	6		T34	3		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	2		T115	1		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T30	5		T73	17		T113	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	18		T114	8		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	440	1			T13	12		T40	1		T16	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T72	1		T34	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19287	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T246	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T248	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T132	2		T219	10		T74	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	31		T33	3		T131	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	16		T13	14		T16	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T203	11		T182	14		T191	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T5	11		T8	5		T12	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T114	7		T147	8		T138	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T114	14		T125	12		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	9		T30	12		T49	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T11	5		T36	5		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	15		T189	17		T17	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T35	1		T111	4		T190	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	4		T122	10		T31	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	5		T34	1		T111	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T115	7		T108	13		T185	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T30	2		T129	34		T16	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	16		T114	11		T108	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T13	10		T40	3		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T115	13		T49	4		T108	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20