Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24872

1

T1

17

T2

2

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3610

1

T5

11

T8

6

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21682

1

T2

2

T3

18

T4

9

auto[1]

6800

1

T1

17

T4

25

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	515	1			T7	4		T11	2		T33	8
values[0]	90	1			T153	2		T185	24		T17	9
values[1]	638	1			T12	10		T13	26		T30	7
values[2]	2821	1			T14	16		T73	17		T113	24
values[3]	865	1			T5	22		T11	12		T12	10
values[4]	652	1			T2	1		T4	9		T5	16
values[5]	587	1			T14	19		T155	3		T147	19
values[6]	695	1			T1	17		T11	2		T16	38
values[7]	696	1			T13	22		T33	13		T173	12
values[8]	680	1			T4	25		T8	6		T14	14
values[9]	1458	1			T2	1		T40	5		T72	1
minimum	18785	1			T3	18		T6	20		T7	174

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	792	1			T12	10		T13	26		T30	7
values[1]	3106	1			T5	22		T14	16		T73	17
values[2]	525	1			T4	9		T5	11		T11	12
values[3]	781	1			T2	1		T5	5		T72	1
values[4]	523	1			T14	19		T155	3		T147	19
values[5]	762	1			T1	17		T11	2		T13	22
values[6]	734	1			T33	13		T114	49		T173	12
values[7]	680	1			T4	25		T14	14		T40	5
values[8]	970	1			T2	1		T8	6		T72	1
values[9]	281	1			T114	19		T190	29		T177	15
minimum	19328	1			T3	18		T6	20		T7	178

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	10		T13	15		T30	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T153	1		T123	1		T111	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1715	1			T5	12		T73	2		T113	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T14	16		T49	9		T108	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T4	6		T11	10		T12	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	6		T30	13		T122	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	1		T5	5		T189	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T72	1		T115	14		T187	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T147	9		T127	1		T108	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T14	19		T155	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	17		T182	9		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	2		T13	11		T16	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T33	9		T114	23		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T35	4		T181	1		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	12		T34	6		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	14		T40	5		T36	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T2	1		T72	1		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T8	6		T37	3		T156	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T114	12		T190	16		T177	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T257	1		T229	16		T258	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19143	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T214	7		T259	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	11		T30	4		T185	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T153	1		T179	11		T177	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T5	10		T73	15		T113	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T109	10		T171	6		T120	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T4	3		T11	2		T30	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	5		T122	14		T38	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T189	11		T128	4		T191	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T231	11		T38	3		T207	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T147	10		T127	11		T122	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T155	2		T109	12		T179	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T182	8		T191	12		T168	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	11		T16	27		T178	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T33	4		T114	26		T173	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T35	3		T181	9		T138	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T4	13		T34	2		T252	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T36	6		T127	11		T119	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T48	11		T49	4		T128	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T37	1		T156	14		T81	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T114	7		T190	13		T177	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T257	7		T229	12		T258	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T214	5		T259	14		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	503	1			T7	4		T11	2		T33	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T260	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T185	13		T17	4		T261	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T153	1		T214	7		T259	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	10		T13	15		T30	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T111	19		T179	1		T177	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T73	2		T113	3		T129	37
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	16		T49	9		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	12		T11	10		T12	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T108	9		T122	11		T109	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T2	1		T4	6		T5	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	6		T30	13		T72	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T147	9		T108	27		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	19		T155	1		T109	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	17		T127	1		T122	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	2		T16	11		T178	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T33	9		T173	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	11		T128	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	12		T114	23		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	6		T14	14		T35	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	430	1			T2	1		T72	1		T114	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T40	5		T36	8		T37	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18640	1			T3	18		T6	20		T7	174
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T260	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T185	11		T17	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T153	1		T214	5		T259	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	11		T30	4		T119	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T179	11		T177	9		T171	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	903	1			T73	15		T113	21		T137	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T120	2		T170	7		T262	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	10		T11	2		T30	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T122	14		T109	10		T171	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	3		T189	11		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	5		T231	11		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T147	10		T128	4		T110	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T155	2		T109	12		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T127	11		T122	7		T177	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T16	27		T178	9		T179	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T33	4		T173	11		T127	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	11		T128	5		T138	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	13		T114	26		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T35	3		T127	11		T181	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T114	7		T34	1		T48	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T36	6		T37	1		T156	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	1		T13	12		T30	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T153	2		T123	1		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T5	11		T73	17		T113	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	1		T49	1		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T4	4		T11	7		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	6		T30	1		T122	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T2	1		T5	1		T189	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T72	1		T115	1		T187	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T147	11		T127	12		T108	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	1		T155	3		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	1		T182	9		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T11	2		T13	12		T16	31
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T33	10		T114	28		T173	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T35	6		T181	10		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	14		T34	7		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	1		T40	1		T36	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T2	1		T72	1		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T8	1		T37	3		T156	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T114	8		T190	14		T177	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T257	8		T229	13		T258	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19288	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T214	6		T259	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	9		T13	14		T30	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T111	18		T177	9		T170	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T5	11		T129	34		T130	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	15		T49	8		T108	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T4	5		T11	5		T12	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	5		T30	12		T122	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	4		T189	17		T191	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T115	13		T219	10		T243	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T147	8		T108	25		T122	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T14	18		T109	9		T183	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	16		T182	8		T191	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	10		T16	7		T178	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T33	3		T114	21		T115	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T35	1		T138	10		T81	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	11		T34	1		T203	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	13		T40	4		T36	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T48	15		T49	4		T185	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	5		T37	1		T156	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T114	11		T190	15		T177	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T229	15		T258	6		T198	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T214	6		T259	13		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	503	1			T7	4		T11	2		T33	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T260	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T185	12		T17	7		T261	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T153	2		T214	6		T259	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	1		T13	12		T30	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T111	1		T179	12		T177	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T73	17		T113	24		T129	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	1		T49	1		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	11		T11	7		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T108	1		T122	15		T109	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	1		T4	4		T5	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	6		T30	1		T72	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T147	11		T108	2		T128	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T14	1		T155	3		T109	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	1		T127	12		T122	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T11	2		T16	31		T178	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T33	10		T173	12		T127	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T13	12		T128	6		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	14		T114	28		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	1		T14	1		T35	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	412	1			T2	1		T72	1		T114	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T40	1		T36	9		T37	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18785	1			T3	18		T6	20		T7	174
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T185	12		T17	2		T261	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T214	6		T259	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	9		T13	14		T30	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T111	18		T177	9		T193	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T129	34		T130	13		T235	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	15		T49	8		T170	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	11		T11	5		T12	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T108	8		T122	10		T109	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T4	5		T5	4		T189	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	5		T30	12		T115	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T147	8		T108	25		T191	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	18		T109	9		T183	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	16		T122	5		T191	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T16	7		T178	13		T112	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T33	3		T131	12		T182	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	10		T138	10		T81	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T4	11		T114	21		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	5		T14	13		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T114	11		T48	15		T49	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T40	4		T36	5		T37	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20