Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28482

1

T1

17

T2

2

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24960

1

T2

2

T3

18

T5

38

auto[ADC_CTRL_FILTER_COND_OUT]

3522

1

T1

17

T4

34

T12

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22059

1

T1

17

T3

18

T5

11

auto[1]

6423

1

T2

2

T4

34

T5

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24412

1

T1

17

T2

2

T3

18

auto[1]

4070

1

T4

16

T5

15

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	51	1			T216	11		T263	1		T232	39
values[0]	58	1			T153	2		T194	3		T264	2
values[1]	569	1			T30	2		T72	1		T16	38
values[2]	480	1			T11	2		T72	1		T34	1
values[3]	660	1			T14	33		T40	5		T34	4
values[4]	839	1			T2	1		T4	25		T40	4
values[5]	3137	1			T4	9		T5	22		T14	16
values[6]	638	1			T114	32		T147	19		T127	12
values[7]	517	1			T12	10		T30	20		T34	4
values[8]	829	1			T1	17		T5	5		T11	12
values[9]	1417	1			T2	1		T5	11		T8	6
minimum	19287	1			T3	18		T6	20		T7	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	711	1			T30	2		T72	1		T16	38
values[1]	409	1			T11	2		T72	1		T178	23
values[2]	780	1			T14	33		T40	5		T34	4
values[3]	3168	1			T2	1		T5	22		T14	16
values[4]	961	1			T4	34		T48	2		T147	19
values[5]	503	1			T114	32		T49	9		T127	12
values[6]	641	1			T12	10		T30	20		T34	4
values[7]	730	1			T1	17		T5	5		T11	12
values[8]	990	1			T2	1		T5	11		T8	6
values[9]	277	1			T160	1		T187	1		T38	5
minimum	19312	1			T3	18		T6	20		T7	178

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

4186

1

T1

16

T4

16

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T30	1		T72	1		T34	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T16	11		T153	1		T117	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T11	2		T159	1		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T72	1		T178	14		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T14	19		T40	5		T35	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	14		T34	3		T122	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1710	1			T2	1		T5	12		T14	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T40	4		T127	1		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T147	9		T132	8		T138	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T4	18		T48	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T49	9		T127	1		T17	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T114	15		T184	15		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T30	13		T173	1		T115	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	10		T30	3		T34	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	5		T11	10		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T1	17		T12	10		T13	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T2	1		T5	6		T8	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T16	8		T115	8		T108	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T160	1		T187	1		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T169	2		T216	11		T205	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19155	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T255	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T30	1		T36	6		T110	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T16	27		T153	1		T265	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T227	2		T148	14		T200	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T178	9		T49	4		T155	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T35	3		T166	9		T17	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T34	1		T122	14		T128	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T5	10		T73	15		T113	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T127	2		T37	1		T181	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T147	10		T138	10		T156	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T4	16		T48	1		T128	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T127	11		T17	2		T192	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T114	17		T184	12		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T173	11		T48	11		T179	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T30	4		T34	1		T122	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	2		T119	7		T168	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	11		T179	16		T266	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T5	5		T13	11		T33	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	7		T131	14		T179	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T38	3		T267	11		T268	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T205	3		T197	13		T149	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T255	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T216	11		T263	1		T232	23
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T248	1		T196	4		T269	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T153	1		T194	3		T264	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T30	1		T72	1		T36	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T16	11		T117	2		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	2		T34	1		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T72	1		T178	14		T49	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	19		T40	5		T35	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	14		T34	3		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	1		T189	18		T185	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T4	12		T40	4		T122	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1720	1			T5	12		T14	16		T73	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	6		T48	1		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T147	9		T127	1		T17	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T114	15		T159	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T30	13		T173	1		T115	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	10		T30	3		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T5	5		T11	10		T48	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	17		T108	13		T179	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T2	1		T5	6		T8	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	392	1			T12	10		T13	11		T16	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19142	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T232	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T269	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T153	1		T264	1		T270	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T30	1		T36	6		T185	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T16	27		T188	10		T206	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T110	3		T148	14		T200	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T178	9		T49	4		T155	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T35	3		T166	9		T119	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T34	1		T127	11		T128	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T189	11		T185	2		T17	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	13		T122	14		T231	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T5	10		T73	15		T113	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T4	3		T48	1		T127	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T147	10		T127	11		T17	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T114	17		T128	4		T190	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T173	11		T192	14		T204	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T30	4		T34	1		T122	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	2		T48	11		T179	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T179	16		T171	6		T148	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T5	5		T13	11		T33	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T13	11		T16	7		T131	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T16	1		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T30	2		T72	1		T34	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T16	31		T153	2		T117	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T11	2		T159	1		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T72	1		T178	10		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T14	1		T40	1		T35	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	1		T34	3		T122	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T2	1		T5	11		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T40	1		T127	3		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T147	11		T132	1		T138	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T4	18		T48	2		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T49	1		T127	12		T17	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T114	18		T184	13		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T30	1		T173	12		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	1		T30	5		T34	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	1		T11	7		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	1		T12	1		T13	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	366	1			T2	1		T5	6		T8	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T16	8		T115	1		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T160	1		T187	1		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T169	2		T216	1		T205	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19288	1			T3	18		T6	20		T7	178
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T255	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T36	5		T112	14		T185	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T16	7		T188	9		T217	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T227	4		T148	6		T271	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T178	13		T49	4		T112	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	18		T40	4		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T14	13		T34	1		T122	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T5	11		T14	15		T114	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T40	3		T37	1		T177	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T147	8		T132	7		T138	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	16		T109	10		T190	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T49	8		T17	1		T39	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T114	14		T184	14		T243	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T30	12		T115	13		T48	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	9		T30	2		T108	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	4		T11	5		T168	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	16		T12	9		T13	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	5		T8	5		T13	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	7		T115	7		T108	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T272	9		T267	15		T268	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T216	10		T205	3		T197	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T272	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T255	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T216	1		T263	1		T232	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T248	1		T196	1		T269	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T153	2		T194	2		T264	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T30	2		T72	1		T36	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	31		T117	2		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	2		T34	1		T110	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T72	1		T178	10		T49	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	1		T40	1		T35	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	1		T34	3		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T2	1		T189	12		T185	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	14		T40	1		T122	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T5	11		T14	1		T73	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T4	4		T48	2		T127	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T147	11		T127	12		T17	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T114	18		T159	1		T128	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T30	1		T173	12		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	1		T30	5		T34	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T5	1		T11	7		T48	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	1		T108	1		T179	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	428	1			T2	1		T5	6		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T12	1		T13	12		T16	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19287	1			T3	18		T6	20		T7	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T216	10		T232	22		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T196	3		T269	12		T273	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T194	1		T274	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T36	5		T112	14		T185	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T16	7		T188	9		T217	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T148	6		T149	5		T261	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T178	13		T49	4		T112	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	18		T40	4		T35	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T14	13		T34	1		T132	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T189	17		T185	4		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	11		T40	3		T122	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T5	11		T14	15		T114	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	5		T109	10		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T147	8		T17	1		T39	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T114	14		T190	15		T182	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T30	12		T115	13		T49	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	9		T30	2		T108	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	4		T11	5		T48	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	16		T108	12		T148	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T5	5		T8	5		T13	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T12	9		T13	10		T16	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24296

1

T1

1

T2

2

T3

18

auto[1]

auto[0]

4186

1

T1

16

T4

16

T5

20